Lecture 2 집적회로란 : 무어의법칙, 집적화의장점, 종류, 반도체칩의일생 원광대학교이재철 http://edu.idec.or.kr
Semiconductor? Conductor: Low resistivity Easily conducts Electrical Current Metals(copper, gold, sliver, etc.) Insulator: High resistivity Blocks Electrical Current Compounds(Wood, Rubber, etc.) Semiconductor: Intermediate resistivity Medium Electrical Conductivity
Why? The behavior of valence electron Insulator: Many but Bound to nucleus Conductor: Few and Free from nucleus Semiconductor: Just in between: 전자 양성자중성자 Nucleus
The Silicon Atom 14 electrons occupying the 1st 3 energy levels: 1s, 2s, 2p orbitals filled by 10 electrons 3s, 3p orbitals filled by 4 electrons Each has one electron and is capable of forming a bond with a neighboring atom
Semiconductor Materials Elemental Semiconductor A Single Element Si, Ge Compound Semiconductor Two or More Elements III-V: GaAs, InP, GaN, AlxGa1-xAs 1 H 수소 3 Li 리튬 11 Na 나트륨 I II III IV V VI VII 0 4 Be 베릴륨 12 Mg 마그네슘 전자의개수 원소기호 5 B 붕소 13 Al 알루미늄 31 Ga 갈륨 6 C 탄소 14 Si 실리콘 32 Ge 게르마늄 7 N 질소 15 P 인 33 As 비소 8 O 산소 16 S 황 9 F 불소 17 Cl 염소 2 He 헬륨 10 Ne 네온 18 Ar 아르곤
Electronic Properties of Si Silicon is a semiconductor material. Pure Si has relatively high resistivity at room temperature. There are 2 types of mobile charge-carriers in Si: Conduction electrons are negatively charged. Holes are positively charged. They are an absence of electrons. The concentration of conduction electrons & holes in a semiconductor can be affected in several ways: by adding special impurity atoms (dopants) by applying an electric field by changing the temperature by irradiation
Intrinsic Semiconductor Silicon: 4 Valence Electrons Si Si Si Si Si Si Si Si Si Diamond Structure 2D Model
n-type Small number (~ ppm) of Impurities of Group V(e.g. P, As) 인원자 ( 도너 ) Si Si Si 공유결합 자유전자 Si P Si 자유전자 도너 Si Si Si
p-type Small number (~ ppm) of Impurities of Group III(e.g. B, In) 공유결합 붕소원자 ( 억셉터 ) 정공 Si Si Si B Si Si 정공 억셉터 Si Si Si
pn Junction Diode Schematic diagram p-type n-type I D Circuit symbol net acceptor concentration N A net donor concentration N D + V D Physical structure: + I D metal SiO 2 SiO 2 V D p-type Si n-type Si metal
p-n n Junction Diode Depletion layer formation by diffusion Diffusion due to difference of density p 형 n 형 공핍층 B B B P P B B B P P B B B B B P P P B B B B B P P P B P P B P P pn 접합에서캐리어의확산 공핍층의형성
Depletion Region When the junction is first formed, mobile carriers diffuse across the junction (due to the concentration gradients) Holes diffuse from the p side to the n side, leaving behind negatively charged immobile acceptor ions Electrons diffuse from the n side to the p side, leaving behind positively charged immobile donor ions A region depleted of mobile carriers is formed at the junction. The space charge due to immobile ions in the depletion region establishes an electric field that opposes carrier diffusion.
Electric Field and Built-In Potential φ 0 p + + + + + n No net current flows across the junction when the externally applied voltage is 0 V. electric field (V/cm) potential (V) distance kt φ 0 ln q kt q N N A = 2 ni distance D ln( 10) = 60 mv for T = 300K built-in potential φ 0
Effect of Applied Voltage V D p + + + + + n The quasi-neutral p and n regions have low resistivity, whereas the depletion region has high resistivity. Thus, when an external voltage V D is applied across the diode, almost all of this voltage is dropped across the depletion region. (Think of a voltage divider circuit.) If V D > 0 (forward bias), the potential barrier to carrier diffusion is reduced by the applied voltage. If V D < 0 (reverse bias), the potential barrier to carrier diffusion is increased by the applied voltage.
Equilibrium & Reverse Bias I 물 ( 정공 ) 수조 (p 형 ) 수로 (n 형 ) 공핍층 Vz 항복역방향순방향 V 평형상태의 pn 접합 역방향바이어스
Forward Bias As V D increases, the potential barrier to carrier diffusion across the junction decreases*, and current increases exponentially. V D > 0 p + + + + + n I D (Amperes) V D (Volts) * Hence, the width of the depletion region decreases.
Forward Bias 물 ( 정공 ) 양극 (Anode) 음극 (Cathode) 수로 (n 형 ) 전류 공핍층 수조 (p 형 ) 순방향바이어스
I-V Characteristic / kt Exponential diode equation: I = I ( e D 1) D S qv I D (A) kt q = 0.026 Volts for T = 300K I S is the diode saturation current function of n i2, A D, N A, N D, length of quasi-neutral regions typical range of values: 10-14 to 10-17 A/μm 2 Note that e 0.6/0.026 = 10 10 and e 0.72/0.026 = 10 12 V D (V) I D is in the ma range for V D in the range 0.6 to 0.7 V, typically.
Why are pn Junctions Important for ICs? Transistors are made of pn junctions Electrical isolation of transistors located next to each other at the surface of a Si wafer. MOS transistor structure contains reverse-biased diodes. The junction capacitance of these diodes can limit the performance (operating speed) of digital circuits
Device Isolation using pn Junctions regions of n-type Si a b n n n n n p-type Si No current flows if voltages are applied between n-type regions, because two pn junctions are back-to-back n-region a n-region p-region => n-type regions isolated in p-type substrate and vice versa b
Junction Isolation Transistor A Transistor B n n n n p-type Si We can build large circuits consisting of many transistors without worrying about current flow between devices. The p-n junctions isolate the transistors because there is always at least one reverse-biased p-n junction in every potential current path.
Transistors Transistors are three terminal devices that replaced vacuum tubes. They are solid state devices that are used for Amplification Switching Detecting Light The three terminals are the Emitter, Base, Collector (BJT) Source, Gate, Drain (FET)
Transistors Bipolar: Both Hole and Electron are used Unipolar: Only Hole or Electron is used J-FET: Junction Field Effect Transistor MOSFET:Metal-Oxide-Semiconductor TFT: Thin Film Transistor
The BJT Bipolar Junction Transistors are made with n-type and p-type semiconductors. There are two types: npn and pnp. Circuit Symbols E 에미터 N P N C 컬렉터 E 에미터 P N P C 컬렉터 B 베이스 B 베이스 npn 트랜지스터 pnp 트랜지스터
Discrete BJT 보호산화막 에미터베이스 컬렉터
Integrated BJT B E B C 보호산화막 에미터베이스컬렉터 p ISO n 매몰층 p ISO p 기판
Two diodes forward biased reverse biased. 공핍층 공핍층 물 ( 정공 ) 수로 (n 형 ) 수조 (p 형 )
Two Diodes in Connection 공핍층 공핍층 Iforward Ireverse No transistor action
Very thin base width I E αi E ( 1 α ) I E R V F The collector current I C is almost equal to I E, and collector current is controlled by the E-B junction bias. The loss, i.e. α < 1 corresponds to the recombination of holes in base. V R
BJT in Equilibrium 전자 정공 전자 에미터 (n 형 ) 베이스 (p 형 ) 컬렉터 (n 형 ) 물 ( 전자 ) 장벽 ( 베이스 ) 수조 ( 에미터 ) 수조 ( 컬렉터 )
BJT in Active Region I E V EB - + - + I B V BE V CB V BE 에미터 V C 컬렉터
BJT Characteristics
BJT Applications Analog Circuit: Amplifier Digital Circuit: Switch
BJT Advantages Linear Characteristics Large gm Good for Analog Circuits Disadvantages Large Power Consumption Cannot be Scaled Large Space for Isolation Incompatible with CMOS Digital Limited Usage Now
Field Effect Transistor (FET) An electric field is applied normal to the surface of the semiconductor (by applying a voltage to an overlying gate electrode), to modulate the conductance of the semiconductor Modulate drift current flowing between 2 contacts ( source and drain ) by varying the voltage on the gate electrode
JFET 접합형전계효과트랜지스터 (JFET) 의심벌과구조 게이트 (G) D D G G 소스 (S) 드레인 (D) S N-channel S P-channel + - A 공핍층 - +
JFET p 형게이트 p 형게이트 p 형게이트 소스 전자 공핍층 n 형 드레인 소스 공핍층 n 형 드레인 소스 전자 공핍층 n 형 드레인 선형영역 차단영역 포화영역 드레인전류 선형영역 포화영역 게이트전압 차단영역 소스드레인전압
MOSFET D G S N-channel D G S P-channel
MOSFET Cross-section section 알루미늄배선 게이트 절연막 소스 드레인 필드산화막
Cutoff 소스 게이트 Metal Oxide 드레인 소스 게이트 ++++++++++++ 드레인 n Semiconductor n ------------ 공핍층 공핍층 공핍층 공핍층 p 형기판 p 형기판 Without a gate-to-source voltage applied, no current can flow between the source and drain regions. Above a certain gate-to-source voltage (threshold voltage V T ), a conducting layer of mobile electrons is formed at the Si surface beneath the oxide. These electrons can carry current between the source and drain.
Linear Region V GS V DS The MOSFET behaves as a resistor when V DS is low: Drain current I D increases linearly with V DS Resistance R DS between SOURCE & DRAIN depends on V GS R DS is lowered as V GS increases above V T Source Gate +++++++++++++++++ I D Drain I D V GS = 2 V V GS = 1 V > V T V DS I DS = 0 if V GS < V T
Saturation Region As V DS increases above V GS V T V DSAT, the length of the pinch-off region ΔL increases: extra voltage (V DS V Dsat ) is dropped across the distance ΔL the voltage dropped across the inversion-layer resistor remains V Dsat the drain current I D saturates 소스 게이트 +++++++++++++++++ 채널 드레인 공핍층 공핍층 p 형기판
I-V V Relations ID (ma) 2 1 Triode VDS=VGS-VT Saturation VGS=5V VGS=4V VGS=3V VGS=2V VGS=1V 0.0 1.0 2.0 3.0 4.0 5.0 VDS (V) I D as a function of V DS Square Dependence 0.020 I D 0.010 I D Subthreshold Current 0.0 1.0 2.0 3.0 VGS (V) as a function of V GS (for V DS =5v) NMOS Enhancement Transistor : W=100um, L=20um
선형 (Linear ) 영역 Triode, Nonsaturated V GS > V T, V DS < V GS -V T β I = V V V V 2 2 2 [ ( ) ] D GS T DS DS Device Transconductance Process Transconductance β = K' W L K'= μ C = n ox n Aspect Ratio ox μ ε t ox
포화 (Saturation) 영역 V S =0 V GS >V T0 + n + 채널 n + I D + V DS V DS (V GS -V T0 ) V B =0 p(na) V GS > V T, V DS > V GS -V T 1 I = β V V 2 ( ) D GS T 2
Switch Model of NMOS Transistor V GS Gate Source (of carriers) Drain (of carriers) Open (off) (Gate = 0 ) Closed (on) (Gate = 1 ) R on V GS < V T V GS > V T @ Linear Region R ON β ( V V ) K' ( V V )W GS 1 T = 1 GS T L
Switch Model of PMOS Transistor V GS Gate Source (of carriers) Drain (of carriers) Open (off) (Gate = 1 ) Closed (on) (Gate = 0 ) R on V GS > V DD V T V GS < V DD V T
Deep Submicron Issues Threshold Variations Subthreshold Conduction Parasitic Resistances
Future Device
Impact of Interconnect Parasitics Interconnect parasitics reduce reliability affect performance and power consumption Classes of parasitics Capacitive Resistive Inductive
Interconnect: # of Wiring Layers # of metal layers is steadily increasing due to: T ins ρ = 2.2 μω-cm M6 Increasing die size and device count: we need more wires and longer wires to connect everything W S M5 Rising need for a hierarchical wiring network; local wires with high density and global wires with low RC H M4 3.5 Minimum Widths (Relative) 4.0 Minimum Spacing (Relative) 3.0 3.5 substrate M3 M2 M1 poly 0.25 μm wiring stack 2.5 2.0 1.5 1.0 0.5 0.0 1.0μ 0.8μ 0.6μ 0.35μ 0.25μ M5 M4 M3 M2 M1 Poly 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1.0μ 0.8μ 0.6μ 0.35μ 0.25μ M5 M4 M3 M2 M1 Poly
Semiconductor Design Architecture Design Circuit Design Layout Design PhotoMask
Si Wafer 모래 단결정실리콘잉고트 잉고트자르기 연마 고순도실리콘봉 광택내기 다결정실리콘잉고트 단결정잉고트제조 ( 쵸크랄스키방법 ) 완성된웨이퍼
Lithography: Basic Concept 실리콘기판 레지스트현상하기 얇은막입히기 얇은막걷어내기 원판복사하기 레지스트입히기 레지스트벗겨내기
Wafer Processing 실리콘웨이퍼 열처리 완성된웨이퍼 표면단결정기르기 ( 에피택시 ) 모양내기 얇은막입히기 불순물집어넣기 웨이퍼칩 ( 다이 ) 검사
완성된반도체칩단면도 알루미늄배선 게이트 절연막 소스 드레인 필드산화막
Assembly & Packaging 칩검사 칩 ( 다이 ) 잘라내기 봉합하기 도선연결하기 다이붙이기 완성된반도체칩
Photoresist(PR) ) Coating Positive : Exposed Pattern is Removed Negative: Unexposed Pattern is Removed
Stepper Exposure UV: 436 nm (G-Line), 405 nm (H-line), 365 nm (I-line) Excimer Laser: 248 nm, 193 nm UV
Development & Etch
Process Lithography Optical, E-Beam, X-Ray Etch Wet,Dry Diffusion/Oxidation Thin Film Metal, Oxide, Nitride, etc.
Bipolar IC
Bipolar IC: Cross-section section 보호산화막 에미터베이스컬렉터 p ISO n 매몰층 p ISO p 기판
Buried Layer n 매몰층 p 기판 n 에피 n 매몰층
ISO p ISO p ISO
Base p 베이스
Emitter Emitter n 에미터 n 컬렉터
Contact
Metal Al
PAD
The MOS Transistor Poly Gate(G) V G } Field Oxide Source (s) V S Drain (D) VD Channel Stop t ox L p + n + n + p + p(n a ) Bulk(B) V B
The MOS Transistor(Cross-section) section) Gate Oxide Gate Source Polysilicon Drain n + n + Field-Oxide (SiO 2 ) p+ stopper P-substrate Bulk contact Cross-Section of NMOS Transistor
Silicon Gate n-mosfetn p- Type Substrate Initial Oxidation, Nitride Deposition Active Mask Channel Stop Doping/Field Oxidation Gate Oxidation Polysilicon Deposition Poly Mask n+ Doping/ CVD Oxide Contact Mask Metal Mask
Silicon Gate n-mos n (1) Si 3 N 4 Initial Oxide p Sub Initial Oxide and Nitride Thin Film Active Mask FOX Si 3 N 4 FOX p Sub Field Oxide
Silicon Gate n-mos n (2) FOX FOX p Sub Active Area Gate Oxide FOX FOX p Sub Gate Oxide
Silicon Gate n-mos n (3) Poly Mask FOX FOX p Sub Arsenic ions Poly Silicon Gate FOX n+ n+ p Sub FOX n+ n+ Source & Drain Implant
Silicon Gate n-mos n (4) Contact Mask CVD Oxide FOX n+ n+ FOX p Sub Metal Mask Contact FOX n+ n+ p Sub FOX Metal
Advanced Metallization
Advanced Metallization
Chemical Mechanical Polishing (CMP) Chemical mechanical polishing is used to planarize the surface of a wafer at various steps in the process of fabricating an integrated circuit. interlevel dielectric (ILD) layers shallow trench isolation (STI) copper metallization IC with 5 layers of Al wiring damascene process Oxide Isolation of Transistors p+ n p+ SiO 2 n+ p n+ p
Interconnect Impact on Chip
Assembly Wafer Test -->Wafer Yield Die Separation-Scribing Die Attach Die Bonding Thermal, Ultrasonic Molding Package Test --> Package Yield Total Yield