Product Manual

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1 Product Manual ELS - MB500A (Xilinx FPGA XC6SLX50-FG8 EVM 보드 ) Embedded and Logic Solution elogics 이로직스 RM607-, Digital Empire, #685,Gasan-dong, 서울특별시금천구가산동 568번지 Geumcheon-gu Seoul, Korea. (Zip: 50-0) 디지털엠파이어 607-호 ( 우 : 5-050) Phone: (0) 6-57 전화 : (0) 6-57 Fax: (0)6-575 팩스 : (0)6-575 naaman@paran.com naaman@paran.com elogics All rights reserved

2 ELS-MB500A Manual V..0 [0-0-08] ELS-500A Manual Version Version Description Date Who 0.9 Initial Create Elogics 0.99 버그수정 Elogics.0 CHIP 교체 Elogics

3 ELS-MB500A Manual V..0 [0-0-08] 목차. 제품설명 제품사양 하드웨어사양 소프트웨어사양 전기적사양 제품구성 보드사진및구성도 보드사진 보드 BLOCK DIAGRAM 기능설명 The overview of MicroBlaze is as follows: 소프트프로세서 ( 마이크로브레이즈 ) Bus 구조 HDMI 출력설명 응용및실습분야 ELS-MB500A 회로도 USB 회로도 : USB. FTRL CHIP 을사용했다 FPGA DDR 회로도 6Bit 8Mbyte DDR 메모리 Gbps 이더넷회로도 /00 이더넷회로도 업보드확장콘넥터회로도 업보드확장콘넥터회로도...

4 ELS-MB500A Manual V..0 [0-0-08] 7.6. DVI OUT 회로도 System Clock generation 회로도....V 50Mhz OSC....5V 00MhZ LVDS OSC 기본장착 (clock+, clock-) Reset 회로 전원회로 Configuration Prom 회로 콘넥터설명 USB Console 포트로사용됨 CN6 RJ 5 JACK Gbps 이더넷콘넥터 J9 RJ 5 JACK 0/00 bps 이더넷콘넥터 J,CN7 DC Jack 5V (DC 입력 ) J0. Xilinx Jtag J8 UP Board 콘넥터 (.V I/O) J7 (.8V,.V I/O 선택 ) UP Board 콘넥터 B:.8V, B9:.V( 디폴트 ) BEAD : BANK0 전원선택스위치 ( 개중 개만선택한다.) 디폴트.V P. MINI HDMI 콘넥터 ( TMDS.V I/O) Xilinx Tool 을이용한 FPGA 내용변경하기 Example Project 개의 LED 와 DIP Switch 사용예제

5 ELS-MB500A Manual V..0 [0-0-08]. 제품설명 ELS-500A은 Xilinx사의스파르탄시리즈중 XC6S5,5,75,50-FG8패키지로제작된 FPGA EVM보드입니다. 보드내에 On chip PHY 0/00/000bps, Local Bus 0/00Mbps 이더넷, 8Mbyte DDR(6Bit) 메모리, LVDS 00Mhz OSC, MINI HDMI TX, USBSERIAL등이내장되어있다. 또한사용자가포트를확장할수있도록 80핀 IO포트가 개있습니다. 구동전원은 5V A 전원으로동작하며, 보드동작을표시하기위한 LED등이있습니다. 기존에스파르탄 용으로제작된 MB500 업그레이드버전이기때문에 I/O 포트를호환되도록설계하였으며, 최대 XC6S50-FG56 칩으로구매시최대 500만게이트용량까지사용할수있는장점이있습니다.. 제품사양.. 하드웨어사양 FPGA : Xilinx XC6SLX5,5,75,50-FG8(50~500) 만게이트사용할수있음 DDR-6Bit 8Mbyte M88E-Gbps 이더넷 LAN90 0/00Mbps 이더넷 Single USBSerial Port FPGA Configuration EEPROM(SPI PROM) DC Power 5V 입력 bit dip switch bit LED, 전원표시 LED 업보드확장콘넥터 (x0xx.0mm) 보드사이즈 : 5mm x 90mm.5V LVDS 00Mhz, 50Mhz OSC 전원스위치.. 소프트웨어사양 ISE., EDK ( 예제코드 ), ISE.5 이상지원됨 제공소스 : 마이크로브레이즈예제기본, SP60를수정한소스 DVI OUT 소스 마이크로브레이즈 LWIP 테스트소스코드 Serial Uart Source 코드.. 전기적사양 5V A DC 아답터 ( 메인전원 ).V FPGA CORE 전원.8V DDR 메모리전원.5V 이덧넷 I/O 전원.V 주변 I/O 전원 5

6 ELS-MB500A Manual V..0 [0-0-08]. 제품구성 구분 수량 비고 ELS-MB500A, USB Cable 판매 제품설명서 이로직스 회로도 PDF, ORCAD 원본 ( 이메일발송 ) Webhard 제공소스 - 영상처리필터소스 (SB60) Webhard - 마이크로브레이즈예제코드 6

7 CY9 LAN 90 array res JTAG ELS-MB500A Manual V..0 [0-0-08]. 보드사진및구성도.. 보드사진.. 보드 BLOCK DIAGRAM PWR SW.V DCJACK.5V.8V USB XC6S-5/5/00/50 FG56 DDR SDRAM 90mm RJ-5 0 RJ-5 88E CFG FLASH XCS08F 05mm 7

8 ELS-MB500A Manual V..0 [0-0-08] 5. 기능설명 본제품은 Xilinx 사에서제공되는 ISE Tool를이용한 VHDL,Velog H/W 개발언어를이용한여러가지 IP(UART, HDMI, DSP BLOCK, MAC) 를실습할수있으며, 또한 EDK Tool을사용하여 FPGA내부에마이크로브레이즈마이컴을내장하는방법과예제프로그램을테스트할수있는 EVM 보드입니다. 단지교육용만아니라여러가지용도로응용할수있도록확장 I/O 포트가내장되어있습니다.. 6. The overview of MicroBlaze is as follows: 6.. 소프트프로세서 ( 마이크로브레이즈 ) -bit, RISC Processor -bit, fixed length instruction generic bit registers -Stage Pipeline Instruction cache and data cache Hardware multiplier Hardware debug logic supported 6.. Bus 구조 The bus consists of the following three bus types. FPGA Internal LMB A dedicated bus used to connect the Micro Blaze and BRAM (FPGA internal memory). FPGA Internal OPB A bus used to connect multiple peripheral IP cores. When customizing, peripheral cores are added to this bus. FPGA External Bus A bus used to connect external memory devices through OPB EMC and OPB DDR SDRAM.,AXI BUS 지원 6.. HDMI 출력설명 HDMI(DVI) 출력은 MB500A에서영상처리된데이터를 DVI 포트로모니터에표시하기위해서사용되며, MB500A보드내에 FRAME BUFFER가있으며, 메모리에저장된내용을 80x0x70Hz로모니터에디스플레이됩니다. 지원해상도 80x0x70Hz DVI 모니터 DUAL BIT RGB 출력 R/A 콘넥터전기적사양 BIT DUAL RGB DATA(.V) HSYNC, DISPLAY EN, PCLK (.V) DDC 데이터는지원하지않음 8

9 UX60-MB-5ST, miniusb Type AB AGND GND GND GND 0uF/0V PGB00060MR PGB00060MR G G 6 7 VOUT 0uF/0V 7 ELS-MB500A Manual V..0 [0-0-08] 6.. 응용및실습분야 네트워크 JPG DID 광고용모니터 영상처리실습등 이더넷 MAC 코딩실습 UART 코딩실습 기타등등 ELS-MB500A 회로도 7.. USB 회로도 : USB. FTRL CHIP 을사용했다. VCCV5 USB_5V VB D- D+ ID 5 G USB USB_5V C95 D9 C USB_D- USB_D+ D OSCO OSCI NC NC USBDM USBDP RESET TEST VCCIO VCC 0 U TXD RXD 5 RTS CTS DTR DSR 9 DCD 0 6 RI CBUS CBUS CBUS CBUS CBUS0 FT_TXD FT_RXD ST_RXD ST_TXD ST_RXD ST_TXD FTRL 9

10 C76 C77 C78 C79 C06 C07 C08 C09 C0 C C C R79 NA C9 C95 C96 C97 C98 C99 C00 C0 R7.7K R75.7K R76.7K R77.7K R7.7K R78.7K R59 7 R60 7 R6 7 R6 7 R6 7 R6 7 R65 7 R66 7 CT50 uf/6v 0.00uF 9 uf/6v uf/6v uf/6v uf/6v GND0 GND BEAD CT5 uf/6v 0.00uF CT9 uf/6v ELS-MB500A Manual V..0 [0-0-08] 7.. FPGA DDR 회로도 6Bit 8Mbyte DDR 메모리 DDR_VREF U6C USER_SW C9 J0 DDR_DB B0 IO_LP_A5_ IO_LP_GCLK5_MDQ_ J DDR_DB5 IO_LN_A_VREF_ IO_LN_GCLK_MDQ5_ K DDR_DB6 G6 IO_LP_A_MDQ6_ K DDR_DB7 G7 IO_L9P_ IO_LN_A_MDQ7_ L0 DDR_DQS0_P F6 IO_L9N_ IO_L5P_A_MDQS_ L DDR_DQS0_M F7 IO_L0P_ IO_L5N_A0_MDQSN_ M DDR_DB B IO_L0N_ IO_L6P_FCB_B_M_DQ_ M DDR_DB 8V_IO9P B IO_L9P_ IO_L6N_FOE_B_M_DQ_ N0 DDR_DB0 8V_IO9N A0 IO_L9N_ IO_L7P_FWE_B_MDQ_ N DDR_DB 8V_IO0P A IO_L0P_ IO_L7N_LDC_MDQ_ P DDR_DB8 8V_IO0N K6 IO_L0N_ IO_L8P_HDC_MDQ8_ P DDR_DB9 J6 IO_LP_ IO_L8N_MDQ9_ R0 DDR_DB0 H6 IO_LN_ IO_L9P_MDQ0_ R DDR_DB H7 IO_L8P_ IO_L9N_MDQ_ T DDR_DQS_P DDR_A D9 IO_L8N_VREF_ IO_L50P_MUDQS_ T DDR_DQS_M FPGA_SCL D0 IO_L9P_A_MA_ IO_L50N_MUDQSN_ U0 DDR_DB FPGA_SDA F8 IO_L9N_A_MA_ IO_L5P_MDQ_ U DDR_DB DDR_A F9 IO_L0P_A_MRESET_ IO_L5N_MDQ_ V DDR_DB DDR_CKE D IO_L0N_A0_MA_ IO_L5P_MDQ_ V DDR_DB5 DDR_A D IO_LP_A9_MCKE_ IO_L5N_MDQ5_ M9 USER_SW DDR_A8 C0 IO_LN_A8_MA_ IO_L5P_ N9 IO_LP_A7_MA8_ IO_L5N VREF_ DDR_A9 C M6 DDR_A0 G9 IO_LN_A6_MA9_ IO_L58P_ L5 DDR_A F0 IO_LP_A5_MA0_ IO_L58N_ P9 TERM_P DDR_WE H9 IO_LN_A_MA_ IO_L59P_ P0 TERM_N DDR_BA H8 IO_LP_A_MWE_ IO_L59N_ W0 USER_SW DDR_A7 E0 IO_LN_A_MBA_ IO_L60P_ W USER_SW0 DDR_A E IO_L5P_A_MA7_ IO_L60N_ L7 DDR_BA0 IO_L6P_ XEINT J7 IO_L5N_A0_MA_ K8 DDR_BA IO_L6N_ XEINT K7 IO_L6P_A9_MBA0_ U9 DDR_A0 F IO_L6N_A8_MBA_ IO_L70P_ V0 DDR_A F IO_L7P_A7_MA0_ IO_L70N_ M7 CLK_DDRA H0 IO_L7N_A6_MA_ IO_L7P_ M8 IO_L8P_A5_MCLK_ IO_L7N_ CLK_DDRA# J9 P7 DDR_A G0 IO_L8N_A_MCLKN_ IO_L7P_ N6 DDR_OPT G IO_L9P_MA_ IO_L7N_ P8 DDR_A5 IO_L7P_ IC_SCL K0 IO_L9N_MODT_ R9 DDR_A6 IO_L7N_ IC_SDA K9 IO_L0P_GCLK_MA5_ T9 DDR_RAS IO_L7P_AWAKE_ XEINT H IO_L0N_GCLK0_MA6_ T0 DDR_CAS IO_L7N_DOUT_BUSY_ XEINT H IO_LP_GCLK9_MRASN_ DDR_DQM M0 IO_LN_GCLK8_MCASN_ DDR_DQM0 L9 IO_LP_GCLK7_MUDM_ IO_LN_GCLK6_MLDM_ XC6S5-FG8 org SPARTAN-6 FG8 + DDR_A0 DDR_A DDR_A DDR_A DDR_A DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A0 DDR_A DDR_A DDR_A CLK_DDRA CLK_DDRA# DDR_CKE DDR_CS DDR_RAS DDR_CAS VCC.8V DDR_WE VCC.8V U0 AE NC NC DDR_DQM0 DDR_DQM R87 0K DDR_BA DDR_BA DDR_VREFM R88 0K LENGTH SAME A G8 DDR_DB0 E VDDL DQ0 G DDR_DB J9 VDD DQ H7 DDR_DB M9 VDD DQ H DDR_DB R VDD DQ H DDR_DB J VDD DQ H9 DDR_DB5 A9 VDDL DQ5 F DDR_DB6 C VDDQ DQ6 F9 DDR_DB7 C VDDQ DQ7 C8 DDR_DB8 C7 VDDQ DQ8 C DDR_DB9 C9 VDDQ DQ9 D7 DDR_DB0 E9 VDDQ5 DQ0 D DDR_DB G VDDQ6 DQ D DDR_DB G VDDQ7 DQ D9 DDR_DB G7 VDDQ8 DQ B DDR_DB G9 VDDQ9 DQ B9 DDR_DB5 VDDQ0 DQ5 M8 A8 DDR_DQS0_M M A0 UDQS# B7 DDR_DQS0_P M7 A UDQS E8 DDR_DQS_M N A LDQS# F7 DDR_DQS_P N8 A LDQS N A N7 A5 P A6 R P8 A7 RFU R7 P A8 RFU M A9 P7 A0 K9 DDR_OPT R A ODT R8 A A A/RFU VSS E J8 VSS J K8 CK VSS N K CK# VSS P9 L8 CKE VSS5 A7 K7 CS# VSSQ B L7 RAS# VSSQ B8 K CAS# VSSQ D WE# VSSQ D8 F VSSQ5 E7 B LDM VSSQ6 F UDM VSSQ7 F8 L VSSQ8 H L BA0 VSSQ9 DDR_BA0 H8 L BA VSSQ0 J7 BA VSSDL J VREF KTG6QQ-HC(L)E6-667 네트길이조정 DDR_A RAA DDRVREF DDR_A RAB DDR_A6 RAC5 6 DDR_A5 RAD7 8 DDR_A RAA C DDR_A RAB DDR_A0 RAC5 6 C DDR_A0 RAD7 8 DDR_A8 RA5A C5 DDR_A9 RA5B DDR_A7 RA5C5 6 C6 DDR_A RA5D7 8 DDR_A RA6A C7 DDR_BA RA6B DDR_BA0 RA6C5 6 DDR_CAS RA6D7 8 DDR_A RA7A DDRVREF DDR_WE RA7B DDR_RAS RA7C5 6 C8 DDR_BA RA7D7 8 C9 C50 C5 C5 VCC.8V C55 C56 C57 C58 C59 C60 C6 C6 + X7R X7R X7R X7R X7R X7R X7R X7R R 7 TERM_P R 7 x TERM_N R89 CLK_DDRA CLK_DDRA# 00 R 7 DDR_CS R5 7 DDR_CKE R90 7 DDR_OPT VCC.8V R R K FPGA_SCL K FPGA_SDA.V VCC.8V VCC.8V DDR_VREF B6 U VCC.8V + org R85 0K R86 0K RP 8 0K SW USER_SW USER_SW USER_SW USER_SW0 VCC.8V C8 X7R C78 CT5+ 0.0uF C67.7uF SD VDDQ 5 6 AVIN PVIN 7 VSENSE VREF 8 VTT LP996/7MR xct5 + B7 VTT_DDRV.0V@A BEAD CT0 CT + + SW/SMD-/SM_ 7.. Gbps 이더넷회로도 VCCV5.7K R55.7K R56 U7 * Routing Length Same * LVDS SIGNAL( Pair SIGNAL) -> P/N PHY_AVDD0 CN6 PHY_MDIO PHY_MDC 5 MDIO MDC MDIO_P MDIO_N TD0_P TD0_N.7K R57 에러수정 PHY_INT PHY_RESET_B PHY_CRS PHY_COL.99K R58 PHY_RXCLK PHY_RXER PHY_RXCTL_RXDV VCC.V +CT uf/6v VCCV5 +CT uf/6v PHY_RXD0 PHY_RXD PHY_RXD PHY_RXD PHY_RXD PHY_RXD5 PHY_RXD6 PHY_RXD7 PHY_GTXCLK PHY_TXCLK PHY_TXER PHY_TXEN PHY_TXD0 PHY_TXD PHY_TXD PHY_TXD PHY_TXD PHY_TXD5 PHY_TXD6 PHY_TXD7 VCCV CLK5 INIT_B COMA RESET_B RSET CRS COL RXCLK RXER RXDV RXD0 RXD RXD RXD RXD RXD5 RXD6 RXD7 GTXCLK TXCLK TXER TXEN TXD0 TXD TXD TXD TXD TXD5 TXD6 TXD7 TDI TMS TRST_B TDO TCK NC_50 VDDOX_7 VDDOX_ VDD_ VDDO_0 VDD_ VDD_5 VSS9 VSS9 VSS8 VSS8 VSS66 VSS65 VSS6 VSS60 VSS58 VSS55 VSS5 VSS8 VSS5 VSS VSS0 VSS8 VSS VSS VSS5 VSS9 VSS 6 MDI_P MDI_N 7 56 MDI_P MDI_N 57 6 MDI_P MDI_N 6 5 HSDAC_P HSDAC_N 5 0 SCLK_P SCLK_N 09 SIN_P SIN_N 07 SOUT_P SOUT_N 05 SEL_OSC XTAL 75 XTAL 00 LED_LINK0 99 LED_LINK00 98 LED_LINK000 LED_DPLX 95 LED_RX 9 LED_TX 9 88 CONFIG0 87 CONFIG 86 CONFIG 8 CONFIG 8 CONFIG 80 CONFIG5 79 CONFIG6 0 AVDD_0 6 AVCC_6 59 AVDD_59 5 AVDD_5 9 AVDD_9 AVDD_ 89 VDDOH_89 97 VDDOH_97 7 VDDOH_7 8 DVDD_8 7 DVDD_7 96 DVDD_96 90 DVDD_90 85 DVDD_85 78 DVDD_78 7 DVDD_7 DVDD_ 7 DVDD_7 DVDD_ 6 DVDD_6 DVDD_ 7 VSS_7 9 VSS_9 6 VSS_6 VSS_ 08 VSS_08 06 VSS_06 0 VSS_0 0 VSS_0 0 VSS_0 7 VSS_7 TOP ROUTING C89 C90 C9 C9 C88 pf 0.0uF 0.0uF 0.0uF 0.0uF 5MHz Y C9 pf VCCV5BOTTOM PLACE PHY_LED_LINK0 LED0 SMD_LED(608) PHY_LED_LINK00 K R67 PHY_LED_LINK000 LED SMD_LED(608) K R68 PHY_LED_DUPLEX LED SMD_LED(608) PHY_LED_RX K R69 PHY_LED_TX LED SMD_LED(608) K R70 PHY_CFG0 LED SMD_LED(608) K R7 LED5 SMD_LED(608) VCCV5 K R7 PHY_LED_RX VCCV5 PHY_AVDD0 VCCV5 PHY_CFG0 VCC.V 에러수정 VCCV5 PHY_AVDD0 B BEAD +C80 uf/6v SMD-CT(5) 6 TD_P TD_N RJ-5 5 TD_P TD_N 7 8 TD_P TD_N 9 0 VCC TCGND SHIELD HFJ-G0E/ B BEAD M88E X 0

11 ELS-MB500A Manual V..0 [0-0-08] 0/00 이더넷회로도 7.. 업보드확장콘넥터회로도 R9 K R0 0K R5.7K + C68 uf/6v VCCV5 VCCV5 ETN_.V VCCV5 VCCV5.V LED_A 7 LED_B 7 ERXD- 7 ETXD- 7 ERXD+ 7 ETXD+ 7 ERXD+ ERXD- VCCV5 R7 K VCCV5 R05 K VCCV5.V ETXD- ETXD+ + C69 uf/6v VDD_8CORE C70 C7 C pf C pf Y6 5MHz VCCV5 BA U8 LAN90 / LAN9 VDD8CORE GPIO0/nLED GPIO/nLED GPIO/nLED 5 VDDA 5 TPO+ 5 TPO- TPI+ 8 TPI- 7 VDDREG PME nreset nrd 5 nwr 6 VDD8CORE 7 ncs 7 EXRES 50 AMDIX_EN 5 FIFO_SEL IRQ VDD8A 5 D5 9 D 0 D D D D0 5 D9 6 D8 7 VDDVARIO 8 A A A 0 A 9 A5 8 A6 7 A7 6 VDDVARIO D7 8 D6 9 D5 D D D D 5 D0 6 VDDVARIO 0 VDDVARIO 56 XTAL/CLKIN 55 XTAL 5 VDDA 6 VDDA 9 VSS(PAD) 57 TEST EECLK 0 EEDIO/GPO/TX_EN/TX_CLK 8 EECS 9 BWE BOE SYS_RST BA BA BA BA7 BA6 BA5 BA BD BD BD0 BD9 BD5 BD6 BD8 BD BD7 BD BD5 BD BD BD BD BD0 INT_ETH ETH_CS B BEAD R R6 K R.7K R9.K R9 K C6 R9 K R97 0K C6 INIT_65P LENGTH SAME LENGTH SAME J8 CON80A SPARTAN-6 FG8 U6D XC6S5-FG8 IO_L8P_ V IO_L8N_ W IO_L7P_ Y6 IO_L7N_ W5 IO_L9P_ AA6 IO_L9N_ AB6 IO_L5P_ Y7 IO_LN_D_ AB8 IO_LP_CMPCLK_ AA IO_LN_CMPMOSI_ AB IO_LP_ T8 IO_LN_VREF_ T7 IO_L5P_ Y9 IO_L5N_ AB9 IO_L6P_ W8 IO_LP_D_ AA8 IO_LN_D0_ V5 IO_L6N_ Y8 IO_L7P_ T6 IO_L7N_ T5 IO_L8P_ U7 IO_L5N_ AB7 IO_L8N_ U6 IO_L9P_ V9 IO_L9N_ V8 IO_L0P_ R6 IO_L6P_ AA IO_L6N_VREF_ AB IO_L0N_ R5 IO_LP_ V7 IO_LN_ W7 IO_L0P_ W IO_L0N_ Y IO_LP_ Y5 IO_LN_ AB5 IO_LP_ T IO_LN_ U IO_LP_ T IO_LN_ R IO_L9P_GCLK_ W IO_L9N_GCLK_ Y IO_LP_GCLK9_ Y IO_LN_GCLK8_ AB IO_L0P_ R IO_L0N_ T IO_LP_ AA0 IO_LN_ AB0 IO_LP_ V IO_LN_ W IO_LP_ Y9 IO_N_ AB9 IO_LP_ W0 IO_LN_ Y0 IO_L5P_ AA8 IO_L5N_ AB8 IO_L6P_ W8 IO_L6N_ V7 IO_L7P_ W9 IO_L7N_ Y8 IO_L8P_D7_ Y7 IO_L8N_RDWR_B_VREF AB7 IO_L9P_D_ AA6 IO_L9N_D_ AB6 IO_L50P_ U9 IO_L50N_ V9 IO_L5P_ T8 IO_L5N_ U8 IP_L5P_ T0 IO_L5N_ U0 IO_L5P_ W6 IO_L5N_ Y6 IO_L5P_ Y5 IO_L5N_ AB5 IO_L57P_ AA IO_L57N_ AB IO_L58P_ Y IO_L58N_ AB IO_L59P_ R9 IO_L59N_ R8 IO_L60P_ T7 IO_L60N_ R7 IO_L6P_D5_ W IO_L6N_D6_ Y IO_L6P_ U6 IO_L6N_ V5 IO_L6P_D8_ AA IO_L6N_D8_ AB IO_L65P_INIT_B_ T6 IO_L0P_GCLK_ Y IO_L0N_GCLK0_ AB IO_LP_GCLK_ AA IO_LN_GCLK0_ AB BUG FIX FPGA_CLK LVDS_P5 LVDS_N LVDS_N LVDS_P6 LVDS_N6 LVDS_N5 LVDS_P6 LVDS_P0 LVDS_N0 LVDS_P5 LVDS_N5 LVDS_P LVDS_P LVDS_N LVDS_P LVDS_N LVDS_N6 LVDS_P LVDS_N LVDS_P LVDS_P0 LVDS_N0 LVDS_P5 LVDS_N LVDS_P LVDS_N LVDS_P LVDS_N DSS_D5 DSS_D0 LVDS_N7 LVDS_P7 LVDS_N6 LVDS_P6 LVDS_N5 DSS_D DSS_D DSS_D9 LVDS_P50 LVDS_N9 LVDS_P9 LVDS_N8 LVDS_P8 DSS_D DSS_D7 LVDS_P6 LVDS_N6 LVDS_P6 LVDS_N5 LVDS_P5 LVDS_N50 DSS_D DSS_D DSS_PCLK+ LVDS_N5 LVDS_P5 LVDS_P7 LVDS_N7 LVDS_N6 DSS_D8 DSS_D0 LVDS_N9 LVDS_P6 LVDS_N6 LVDS_P8 LVDS_N8 DSS_D6 DSS_ACBIAS LVDS_P58 LVDS_N57 LVDS_P0 LVDS_N0 LVDS_P57 LVDS_P9 LVDS_N60 LVDS_P60 LVDS_N59 LVDS_P59 LVDS_N58 LVDS_P LVDS_N LVDS_P LVDS_N DSS_HSYNC DSS_VSYNC LVDS_N LVDS_P LVDS_P LVDS_N LVDS_N LVDS_N6 LVDS_P6 LVDS_P0 LVDS_N0 LVDS_P5 LVDS_P57 LVDS_N57 LVDS_P LVDS_P LVDS_N LVDS_P LVDS_N5 LVDS_N LVDS_P0 LVDS_N0 LVDS_P59 LVDS_P7 LVDS_N6 LVDS_N59 LVDS_N7 LVDS_P50 LVDS_P60 LVDS_P LVDS_N60 LVDS_N LVDS_P6 LVDS_N8 LVDS_P8 LVDS_P5 LVDS_N5 LVDS_N50 LVDS_N8 LVDS_P LVDS_N LVDS_N6 LVDS_P6 LVDS_P5 LVDS_P9 LVDS_N9 LVDS_P9 LVDS_N9 LVDS_P8 LVDS_P5 LVDS_N5 LVDS_N5 LVDS_P5 LVDS_N5 LVDS_N LVDS_P6 LVDS_N6 LVDS_P7 LVDS_N7 LVDS_N6 LVDS_P LVDS_N LVDS_P LVDS_N0 LVDS_P0 LVDS_P6 LVDS_N6 LVDS_P6 LVDS_N LVDS_P58 LVDS_N58 VCC. BANK IO_LP_ LVDS_P EXT_CLK EXT_CLK INIT_65P R7 0K.V FPGA_CLK SMD& DIP 겸용.V Y MHz CLK VCC NC GND R98

12 ELS-MB500A Manual V..0 [0-0-08] 7.5. 업보드확장콘넥터회로도 7.6. DVI OUT 회로도 LVDS0_NN6 LVDS0_NP6 LVDS0_N LVDS0_P J7 CON80A SPARTAN-6 FG8 U6A XC6S5-FG8 IO_LN_0 C6 IO_LP_0 B6 IO_LN_0 A6 IO_L5P_0 C7 IO_LN_0 A5 IO_LP_0 C5 IO_LN_VREF_0 A IO_LP_0 D6 IO_L7P_GCLK_0 B IO_L7N_GCLK_0 A IO_L5N_0 A7 IO_L6P_0 B8 IO_L6N_0 A8 IO_L7P_0 D9 IO_L7N_0 C8 IO_L8P_0 C9 IO_L8N_VREF_0 A9 IO_LP_0 E8 IO_LN_0 F8 IO_L5P_0 G8 IO_L5P_GCLK7_0 C IO_L5N_GCLK6_0 A IO_L6P_GCLK5_0 D IO_L6N_GCLK_0 C IO_L5N_0 F9 IO_L6P_0 G9 IO_L6N_0 H0 IO_L7P_0 E0 IO_L7N_0 F0 IO_L8P_0 G IO_L8N_0 H IO_LP_0 D7 IO_LN_0 D8 IO_LP_0 D0 IO_LN_0 C0 IO_LP_GCLK9_0 B0 IO_LN_GCLK8_0 A0 IO_LP_HSWAPEN_0 A IO_L8P_0 C IO_L8N_VREF_0 A IO_L5N_0 D IO_L6P_0 H IO_L6N_0 G IO_L7P_0 E IO_L7N_0 F5 IO_L8P_0 F IO_LP_0 E IO_LN_0 D IO_LP_0 H IO_L8N_0 H IO_L9P_0 D IO_L9N_0 C IO_LN_0 F IO_L50P_0 B IO_L50N_0 A IO_L5P_0 C5 IO_L5N_0 A5 IO_L6P_0 D5 IO_L6N_VREF_0 C6 IO_L6P_SCP7_0 B6 IO_L6N_SCP6_0 A6 IO_L6P_SCP5_0 C7 IO_L6N_SCP_0 A7 IO_L65P_SCP_0 B8 IO_L65N_SCP_0 A8 IO_L66P_SCP_0 E6 IO_L66N_SCP0_0 D7 IO_L5P_0 F 5V R09 0K LVDS0_P5 LVDS0_N5 LVDS0_NN7 LVDS0_NP7 R0 0K LVDS0_P7 LVDS0_N7 R 0K LVDS0_P6 LVDS0_N LVDS0_P LVDS0_N6 LVDS0_NP8 LVDS0_NN8 LVDS0_NP LVDS0_N LVDS0_P LVDS0_N R8 0 LVDS0_N5 LVDS0_P LVDS0_N LVDS0_P LVDS0_N LVDS0_N8 LVDS0_P7 LVDS0_N7 LVDS0_P6 LVDS0_N6 LVDS0_P5 LVDS0_N LVDS0_P LVDS0_P LVDS0_N LVDS0_P8 LVDS0_P6 LVDS0_N5 LVDS0_P5 LVDS0_N LVDS0_P LVDS0_N LVDS0_N8 LVDS0_P8 LVDS0_N7 LVDS0_P7 LVDS0_N6 LVDS0_N5 LVDS0_P5 LVDS0_N LVDS0_P LVDS0_P LVDS0_P8 LVDS0_N7 LVDS0_P7 LVDS0_N6 LVDS0_P6 LVDS0_P5 LVDS0_N50 LVDS0_P50 LVDS0_N9 LVDS0_P9 LVDS0_N8 LVDS0_N6 LVDS0_P6 LVDS0_P6 LVDS0_N6 LVDS0_N5 LVDS0_N66 LVDS0_P65 LVDS0_N65 LVDS0_P6 LVDS0_N6 LVDS0_P LVDS0_P66 LVDS0_NN R 0K VCC. &.8V SELECT BLOCK LVDS0_NN5 LVDS0_NP5 LVDS0_P9 LVDS0_P6 LVDS0_N9 LVDS0_N LVDS0_N LVDS0_N6 LVDS0_N LVDS0_P LVDS0_P6 LVDS0_N6 LVDS0_N50 LVDS0_P50 LVDS0_P6 LVDS0_N6 LVDS0_P6 LVDS0_N5 LVDS0_P5 LVDS0_N6 LVDS0_N LVDS0_P LVDS0_N5 LVDS0_P5 LVDS0_N7 LVDS0_P7 LVDS0_N5 LVDS0_P5 LVDS0_P6 LVDS0_N6 LVDS0_N65 LVDS0_P65 LVDS0_N8 LVDS0_P8 LVDS0_N8 LVDS0_P8 LVDS0_N8 LVDS0_P8 LVDS0_P LVDS0_N66 LVDS0_P66 LVDS0_N7 LVDS0_P7 LVDS0_N LVDS0_P LVDS0_P LVDS0_NP6 LVDS0_NN6 bug XEINT VCC.8V 8V_IO0P XEINT 8V_IO0N VCC.8V XEINT VCC.8V XEINT VCC.8V LVDS0_NP7 LVDS0_NN7 LVDS0_NN8 LVDS0_NP8 LVDS0_NN LVDS0_NP 8V_IO9P 8V_IO9N LVDS0_P LVDS0_N LVDS0_N LVDS0_P LVDS0_NN5 LVDS0_NP5 SW KEY_F SW5 KEY_F SW6 KEY_F SW7 KEY_F P MINI_HDMI DAT+ DAT- DAT_S DAT+ 5 DAT_S DAT- 6 DAT0+ 8 DAT0_S 0 DAT0-9 CLK+ CLK- CLK_S CBL_CEC SCL 5 SDA 6 DDC/CEC GND 7 +5V 8 HPLG 9 T 0 T T T NC 7 R5 R R TVDD DVI_CLK+ MSEN C 0V.V R.7K 5V DDC_IC_SCL IC_SCL IC_SDA VCC.8V IC_SCL C0 0V DDC_IC_SDA IC_SDA DVI_DATA DSS_D5 DSS_D0 DSS_D9 DSS_HSYNC DVI_+5v R.7K DVI_DATA0 U TFP0 tq6-0x0-0.5 PD0 6 PD 6 PD 6 PD 60 PD 59 PD5 58 PD6 55 PD7 5 PD8 5 PD9 5 PD0 5 PD 50 PD 7 PD 6 PD 5 PD5 PD6 PD7 PD8 PD9 0 PD0 9 PD 8 PD 7 PD 6 TXD0+ 5 TXD0- TXD+ 8 TXD- 7 TXD+ TXD- 0 TFADJ 9 TXC+ TXC- DK 7 DK 8 IDCK+ 57 IDCK- 56 DE VSYNC 5 HSYNC BSEL/SCL 5 DSEL/SDA HTPLG/EDGE 9 NC 9 RSVD DKEN 5 VREF TGND TGND 6 TGND 0 DVDD DVDD DGND 6 PGND 7 PVDD 8 TVDD TVDD 9 DGND 8 MSEN DK 6 ISEL/RESET PD 0 DVDD DGND 6 C 0V DVI_DATA.V TXD0- ISEL DVI_HSYNC DVI_DATA9 BSEL DSS_D TXD+ DSS_D R0.7K L8 BEAD DVI_DSEL DVI_DATA L0 BEAD C9 0V TXC- R8.7K TFADJ L9 BEAD R 0K,060 x DVI_DATA R.7K C8 0V DSS_VSYNC TVDD DSS_D7 DVI_DATA8 TXD+ t RT RXEF00 x FUSE-LITTEL_5 DVI_VSYNC DSS_PCLK+ DSS_D R7.7K TXD0+ DSS_D.V R0.7K R.7K DSS_D0 DSS_D C5 0V.V.V DVI_DATA7 C7 0V DSS_D8 DVI_DVDD DVI_DATA0 TXD-.V DVI_PVDD 0_NC DVI_DATA6 TXC+ DVI_DEN C6 0V DVI_VREF DVI_DATA5 DKEN DSS_ACBIAS TXD- HTPLG R9.7K R6 50 DVI_DATA DSS_D6 Adjusted for.9v U TXS00 (DCU) x A 5 B 8 VCCA VCCB 7 OE 6 GND A B R6.7K DDC IC Interface R.7K Internal 0K Pullups. R5.7K DK DK DK QFP6/0.5M Mini HDMI Interface Place Close to the OMAP Processor. 00Ma

13 ELS-MB500A Manual V..0 [0-0-08] 7.7. System Clock generation 회로도.V 50Mhz OSC.5V 00MhZ LVDS OSC 기본장착 (clock+, clock-) 7.8. Reset 회로 Positive Level reset 입력 ( H: Reset, L: Normal) VCCV5 C0 SW9 KEY_F R0 PWR_nRST R K 7.9. 전원회로 BUG.V FPGA CORE 공급회로 :.V 6A 전원공급.5V 이더넷공급회로 : Gbps 이더넷및.5V I/O 전원공급.V I/O 공급회로 :.V I/O 전원공급 7.0. Configuration Prom 회로 ST 사의 MP5P6 Serial Prom 을사용했다.

14 ELS-MB500A Manual V..0 [0-0-08] 8. 콘넥터설명 8.. USB Console 포트로사용됨 Pin 설명 Pin Name Number VCC USB 전원 5V 500mA USB - USB Negative Signal USB + USB Positive Signal GND Ground 8.. CN6 RJ 5 JACK Gbps 이더넷콘넥터 Pin 설명 Pin Name Number TD0_P G TX0 Positive Transmit TD0_N G TX0 Negative Transmit TD_P G TX Positive Transmit TD_N G TX Negative Transmit 5 TD_P G TX Positive Transmit 6 TD_N G TX Negative Transmit 7 TD_P G TX Positive Transmit 8 TD_N G TX Negative Transmit 8.. J9 RJ 5 JACK 0/00 bps 이더넷콘넥터 Pin 설명 Pin Name Number TD0_P TX0 Positive Transmit TD0_N TX0 Negative Transmit TD TAB 5 6 RXD TAB 7 RD0_N RX0 Negative Transmit

15 ELS-MB500A Manual V..0 [0-0-08] 8 RD0_P RX0 Negative Transmit 8.. J,CN7 DC Jack 5V (DC 입력 ) 본제품은 5V@A 아답터전원으로사용한다 J0. Xilinx Jtag Pin Number Pin Name 설명 VCC. V GND Ground TCK JTAG Clock TDO JTAG Data Out 5 TDI JTAG Data In 6 TMS JTAG Mode Set 5

16 ELS-MB500A Manual V..0 [0-0-08] 8.6. J8 UP Board 콘넥터 (.V I/O) Num I/O BANK FPGA NC P Num I/O BANK FPGA NC P LVDS_N BANK LVDS_P BANK LVDS_N5 BANK LVDS_P5 BANK 5 LVDS_N BANK 6 LVDS_P BANK 7 LVDS_N6 BANK 8 LVDS_P6 BANK 9 LVDS_N5 BANK 0 LVDS_P5 BANK LVDS_N9 BANK LVDS_P9 BANK LVDS_N7 BANK LX75,LX00 LVDS_P7 BANK LX75,LX00 5 LVDS_N BANK 6 LVDS_P BANK 7 GND 8 GND 9 LVDS_N BANK 0 LVDS_P BANK LVDS_N6 BANK LVDS_P6 BANK LVDS_N0 BANK LX75 LVDS_P0 BANK LX75 5 LVDS_N0 BANK 6 LVDS_P0 BANK 7 LVDS_N8 BANK LX75 8 LVDS_P8 BANK LX75 9 LVDS_N BANK 0 LVDS_P BANK INIT_65P BANK EXT_CLK BANK LVDS_N0 BANK LX75 LVDS_P0 BANK LX75 5 LVDS_N BANK 6 LVDS_P BANK 7 LVDS_N BANK 8 LVDS_P BANK 9 GND 0 GND LVDS_N BANK LX75 LVDS_P BANK LX75 LVDS_N BANK LVDS_P BANK 5 LVDS_N50 BANK LX75 6 LVDS_P50 BANK LX75 7 LVDS_N BANK 8 LVDS_P BANK 9 LVDS_N59 BANK LX75 50 LVDS_P59 BANK LX75 5 LVDS_N7 BANK LX75 5 LVDS_P7 BANK LX75 5 LVDS_N5 BANK 5 LVDS_P5 BANK 55 LVDS_N60 BANK LX75 56 LVDS_P60 BANK LX75 57 LVDS_N6 BANK LX75 58 LVDS_P6 BANK LX75 59 LVDS_N8 BANK 60 LVDS_P8 BANK 6 LVDS_N5 BANK LX75 6 LVDS_P5 BANK LX75 6 GND 6 GND 65 LVDS_N9 BANK 66 LVDS_P9 BANK 67 LVDS_N6 BANK 68 LVDS_P6 BANK 69 LVDS_N5 BANK LX75 70 LVDS_P5 BANK LX75 7 LVDS_N6 BANK 7 LVDS_P6 BANK 7 LVDS_N57 BANK 7 LVDS_P57 BANK 75 LVDS_N58 BANK 76 LVDS_P58 BANK 77 LVDS_N6 BANK 78 LVDS_P6 BANK 79 GND 80 GND 6

17 ELS-MB500A Manual V..0 [0-0-08] 8.7. J7 (.8V,.V I/O 선택 ) UP Board 콘넥터 B:.8V, B9:.V( 디폴트 ) Num I/O BANK FPGA NC Num I/O BANK FPGA NC VCC5 BANK0 VCC5 BANK0 LVDS0_N BANK0 LVDS0_P BANK0 5 LVDS0_N BANK0 6 LVDS0_P BANK0 7 LVDS0_N BANK0 8 LVDS0_P BANK0 9 LVDS0_N BANK0 0 LVDS0_P BANK0 LVDS0_N BANK0 LVDS0_P BANK0 LVDS0_N5 BANK0 LVDS0_P5 BANK0 5 LVDS0_N7 BANK0 6 LVDS0_P7 BANK0 7 LVDS0_N6 BANK0 8 LVDS0_P6 BANK0 9 LVDS0_N8 BANK0 0 LVDS0_P8 BANK0 LVDS0_N BANK0 LVDS0_P BANK0 LVDS0_N5 BANK0 LVDS0_P5 BANK0 5 LVDS0_N6 BANK0 6 LVDS0_P6 BANK0 7 GND 8 GND 9 LVDS0_N7 BANK0 0 LVDS0_P7 BANK0 LVDS0_N8 BANK0 LVDS0_P8 BANK0 LVDS0_N BANK0 LVDS0_P BANK0 5 LVDS0_N6 BANK0 6 LVDS0_P6 BANK0 7 LVDS_N9_.8 BANK.8V IO 8 LVDS_P9_V.8 BANK.8V IO 9 LVDS0_N BANK0 0 LVDS0_P BANK0 LVDS0_N7 BANK0 LVDS0_P7 BANK0 LVDS0_N5 BANK0 LVDS0_P5 BANK0 5 LVDS0_N BANK0 LX5,LX75 6 LVDS0_P BANK0 LX5,LX75 7 LVDS0_N BANK0 LX5 8 LVDS0_P BANK0 LX5 9 LVDS0_N8 BANK0 50 LVDS0_P8 BANK0 5 LVDS0_N5 BANK0 LX5 5 LVDS0_P5 BANK0 LX5 5 GND 5 GND 55 LVDS0_N6 BANK0 LX5 56 LVDS0_P6 BANK0 LX5 57 LVDS0_N50 BANK0 58 LVDS0_P50 BANK0 59 LVDS0_N9 BANK0 60 LVDS0_P9 BANK0 6 LVDS0_N7 BANK0 LX5 6 LVDS0_P7 BANK0 LX5 6 LVDS0_N8 BANK0 LX5 6 LVDS0_P8 BANK0 LX5 65 LVDS0_N5 BANK0 66 LVDS0_P5 BANK0 67 LVDS_N0_.8 BANK.8V IO 68 LVDS_P0_.8V BANK.8V IO 69 LVDS0_N6 BANK0 70 LVDS0_P6 BANK0 7 LVDS0_N6 BANK0 7 LVDS0_P6 BANK0 7 LVDS0_N6 BANK0 7 LVDS0_P6 BANK0 75 LVDS0_N66 BANK0 76 LVDS0_P66 BANK0 77 LVDS0_N65 BANK0 78 LVDS0_P65 BANK0 79 GND 80 GND 7

18 ELS-MB500A Manual V..0 [0-0-08] 8.8. BEAD : BANK0 전원선택스위치 (개중 개만선택한다.) 디폴트.V Num I/O BANK VCC.V +.V.8V +.8V 8.9. P. MINI HDMI 콘넥터 ( TMDS.V I/O) Pin 설명 Pin Name Number DATA Ground TMDS GROUND DATA+ TMDS DATA PLUS DATA- TMDS DATA MINUS DATA Ground TMDS GROUND 5 DATA+ TMDS DATA PLUS 6 DATA- TMDS DATA MINUS 7 DDC/CEC GROUND DDC RETURN GROUND 8 DATA0+ TMDS DATA0 PLUS 9 DATA0- TMDS DATA0 MINUS 0 DATA0 GROUND TMDS GROUND CLK+ TMDS CLOCK PLUS CLK- TMDS CLOCK MINUS CLK GROUND TMDS CLOCK GROUND CBL/CEC CEC 5 DDC SCL DDC CLOCK 6 DDC SDA DDC DATA 7 NC NC 8 DVI +5V DVI OUT 5V 9 HPLG HOT PLUG 8

19 ELS-MB500A Manual V..0 [0-0-08] 8.0. Xilinx Tool 을이용한 FPGA 내용변경하기 jtag tool을이용하여 FPGA 내용을사용자 logic으로변경할수있다 Bit File을만들기아래그림에서 Generate Programming File를더블클릭하면 Synthesis -> Implement -> Bitfile 생성이되며, 개발시필요한 bit file이생성된다 PROM FILE 만들기 Configure Taget Device -> Generate Target PROM/ACE File 을클릭한다. 9

20 ELS-MB500A Manual V..0 [0-0-08] ISE IMPACT 프로그램이실행된다. 여기서 Create PROM File Formatter 를클릭한다. Configure Single FPGA -> -> Auto Select PROM -> 순으로클릭한다. Output File Name : 생성될 file 이름 Output File Location : bit file 위치한디렉토리 0

21 ELS-MB500A Manual V..0 [0-0-08] 하단에 OK 을클릭한다. OK 을누르면 Bitfile 에서생성된 file 을 load 한다. 또다른 device Add 을할창이띄면 No 한다 -> 다음은 OK 을누른다. Geneare File 을실행한다. 여기서사용자 mcs 파일이생성되었다.

22 ELS-MB500A Manual V..0 [0-0-08] 생성된 Bit,mcs File 다운로드하기 J 콘넥터순서 : VCC, GND, TCK,TDI.TDO, TMS Flashlink보드와 usb jtag, 제공된프린터 jtag tool 을연결한다. Usb cable을연결한다. Boundary Scan을클릭한다. 마우스우측 button 을누른후 Initialize Chain 을클릭한다.

23 ELS-MB500A Manual V..0 [0-0-08] 클릭하면우측에 XILINX IC 모양과 SPI/BPI 창이뜬다. SPI/BPI 을클릭한다. 클릭하면위에서생성된 *.MCS 파일을 LOAD 한다. MB500A 보드에 MP5P6, MP5P6 가실장되어있어서이것을선택한다. 녹색으로표시된 FLASH ICON 을클릭한다. 다음에 Program 을선택하여 Write 을진행하며 Wirte 가완료시성공메시지가표시된다.

24 ELS-MB500A Manual V..0 [0-0-08]

25 ELS-MB500A Manual V..0 [0-0-08] 9. Example Project 9.. 개의 LED와 DIP Switch 사용예제 상태표시 LED,LED,LED,LED Option를설정하기위한 DIP SWICH SW,SW,SW,SW 예제소스 : 제공된프로젝트를 led blink open 한다. 5

26 ELS-MB500A Manual V..0 [0-0-08] module ledtest_top 9.. ( 9.5. sys_clk_pin, 9.6. sys_rst_pin_i, 9.7. leds 9.8. ); 9.9. // 9.0. parameter CLOCK_FREQ = ; // 50 Mhz parameter ONE_SECOND = CLOCK_FREQ; // second 9.. parameter HALF_SECOND = ONE_SECOND / ; // / second 9.. parameter ONE_MILLI_SECOND = ONE_SECOND / 000; // One msec // port 9.7. input sys_clk_pin; 9.8. input sys_rst_pin_i; 9.9. output [:0] leds; wire sys_rst_pin; assign sys_rst_pin = sys_rst_pin_i; 9.5. // DCM Clock Generating 9.6. wire dcm_clk_w; // buffered clk 9.7. wire dcm_clk_half_w; // / buffered clk clk_dcm Inst_clk_dcm 9.0. ( 9...clkin_in (sys_clk_pin), 9...rst_in (sys_rst_pin), 9...clkdv_out (dcm_clk_half_w), 6

27 ELS-MB500A Manual V..0 [0-0-08] 9...clkin_ibufg_out (CLKIN_IBUFG_OUT), 9.5..clk0_out (dcm_clk_w), 9.6..locked_out (LOCKED_OUT) 9.7. ); // Led 9.. //assign dcm_clk_out = dcm_clk_w; 9.. reg dir_r; // 0 : left, : right 9.. reg [7:0] leds_r; 9.. reg [:0] led_count_r; reg [:0] count_r; 9.7. /* 9.8. always@(posedge sys_clk_pin ) begin 9.9. if (sys_rst_pin) begin count_r <= 0; 9.5. end 9.5. else 9.5. count_r <= count_r + ; end */ always@(posedge sys_rst_pin or posedge dcm_clk_w) begin //always@(posedge sys_clk_pin ) begin 9.6. if (sys_rst_pin) begin 9.6. dir_r <= 0; 9.6. leds_r <= 8'b ; 9.6. led_count_r <= ; count_r <= 0; end else begin //count_r <= count_r + ;

28 ELS-MB500A Manual V..0 [0-0-08] if ( count_r >= ONE_MILLI_SECOND * 'b)begin //dip_sw[6:0] ) begin 9.7. led_count_r <= led_count_r + ; if (dir_r == 'b0) 9.7. leds_r <= leds_r << ; else leds_r <= leds_r >> ; count_r <= 0; end else count_r <= count_r + ; if (led_count_r == 'b000) begin 9.8. dir_r <= ~dir_r; 9.8. led_count_r <= ; end end end // 0 : On, : Off assign leds[:0] = ~leds_r[:0]; 9.9. //assign leds[:0] = ~count_r[5:]; 9.9. //assign leds[:0] = {sys_clk_pin,sys_rst_pin_i,sys_clk_pin,sys_rst_pin_i}; NET sys_clk_pin LOC="Y" IOSTANDARD=LVCMOS; # 50Mhz //NET sys_rst_pin_i LOC="H8" SLEW=SLOW IOSTANDARD=LVCMOS5; NET sys_rst_pin_i LOC="L7" SLEW=SLOW IOSTANDARD=LVCMOS8; NET leds<0> LOC="AB0"; NET leds<> LOC="AA0"; NET leds<> LOC="U"; NET leds<> LOC="U"; #NET dip_sw<0> #NET dip_sw<> #NET dip_sw<> #NET dip_sw<> #NET dip_sw<> #NET dip_sw<5> LOC=M; LOC=M; LOC=M; LOC=M; LOC=L; LOC=L; 8

29 ELS-MB500A Manual V..0 [0-0-08] #NET dip_sw<6> LOC=L; #NET dip_sw<7> LOC=L6; #NET dcm_clk_out LOC=C; ; 위프로젝트를임플리먼트를실행후 bit File을다운로드한다. 그러면 LED가깜박이는것을볼수있다 SB60프로젝트실습하기 Windows응용프로그램설치하기 ( 아래프로그램은 XP에서만지원됨 WIN7은지원되지않음 ) d: \project\mb500a\sp60_brd_application\baserefdisetup_0_6.msi 이파일을설치한다. 설치후실행하면아래와같다. 9

30 ELS-MB500A Manual V..0 [0-0-08] SP60 프로젝트컴파일및 bit 파일만들기 d:\project\mb500a\dsp8a\dsp8a.xise를더블클릭한다. 임플리먼트를실행하고 bit, MCS파일을생성한다. 생성된 BIT파일을다운로드한다. G BIT 이더넷통신모드로동작을한다. 위에빨강색으로표시된 Not connected FPGA 메시지가 connected FPGA로바뀐다. Select Image에서영상처리해야할이미지파일을선택한다. 아래메뉴에 show display를클릭한다. 설치된 os에따라이미지가표시되지않을수있다. 이경우에는영문 windows XP를설치하여테스트하면된다. 이미지실행모두가 AUTO 와 Manual를선택하면서실행하면된다 DVI 모니터로출력하기 (SUB BOARD ) 단 ) DVI서브보드를구입한보드에한함 (SB600), 또는 MB500A MB500A보드에 HDMI 케이블을연결한다. 연결시영상처리결과를모니터로통해서볼수있다. 0. EDK 활용 0.. EDK 사용법은 CD 에제공된 Xilinx_Embedded_Processor.pdf 파일을참조합니다. 제공된 C/D 에서 D:\sale_project\LOGIC_PROGRAM\edk_LWIP 5\system.xmp 를더 블클릭하면위와같이프로젝트가 OPEN 됩니다. 0

31 ELS-MB500A Manual V..0 [0-0-08] 위예제는메모리테스트프로젝트입니다. 여기에사용자로직및응용프로그램을코 딩하여사용하면됩니다.