Flip-Flops c h a p t e r 07 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11
292
flip flop Q Q Q 1 Q 0 set ON preset Q 0 Q 1 resetoff clear Q Q 1 2 SET RESET SET RESET 7 1 crossednand SET RESET SET RESET activelow Q 1 SET 0 SET RESET LOW Q Q Q 1 Q 0 SET 0RESET 1 NAND 7 2 NAND 0 1 Q 1 Q 0 7 2 SET 1 RESET 1 7 3 7 4 RESET 0SET 1 7 3 SET 1 Q 0 RESET 293
0SET 1 RESET Q 1 0 NAND SET RESET 7 5 0 Q Q 1 NAND SET RESET 7 6 294
7 8 NOR SET RESET HIGH 7 9 RESET 0 SET 1 Q 1 NOR 1 0 7 9 7 10 SET 0 RESET 0 Q Q NOR Q 0 SET 0 RESET 1 7 11 NOR SET RESET SET 1 RESET 1 7 12 295
0 Q Q NOR SET RESET 7 13 296
7 6 NAND SET RESET 7 13 NOR SET RESET Q Q SET RESET NOR SET RESET HIGH NAND SET RESET LOW NOR HIGH 1 NANDLOW 0 297
single pole switch bounce 7 16 7 16 clocked 7 17 single pole double throw SET RESET 7 18NAND SET RESET 298
7 20 NAND SET RESET crossed NAND gated SET RESET flip flop SET RESET SET RESET NAND 0 NAND 1 NAND SET RESET 0 1 7 21 299
NAND SET 1 RESET 0 Q 1 Q 0 SET 0 RESET 1Q 0 Q 1 1Q Q SET RESET 300
NAND SET RESET SET RESET 1 Q 1 Q 1 SET RESET 7 24 SET RESET D SET RESET SET RESET D data SET RESET clock 1D 1 0 Q 0 Q Q D D 1 D Q D transparent D flip 301
flop 0 0 7 25 D D 2 ON OFF D 2 latch Q Q D 7 27 8 2 2 D strobe Q Q D TTL IC 7475 4 D 7 27 302
7 30 NAND D master slave D flip flop SET RESET D 303
D Q falling edge D negative edge triggeredd 7 31 1 D ON QD SET RESET OFF 0 OFF Q 1 0 OFF Q 1 Q Q Q Q 0OFF D Q D 7 32 positive edge rising edge 7 32 CLEAR PRESET D 0 1 PRESET LOW Q 1 1 CLEAR LOW Q 0 0 PRESET CLEAR LOW 0 PRESET CLEAR SET RESET SET RESET 304
7 33 D D LOW. TTL 7474 IC 4013 HIGHSETRESET CMOS 7 34 7474 IC 7 35 D SET RESET 7475latch D 74LS74 LOW 74LS174 74LS175 305
LOW 74LS273 20 8 D 1 74LS273 74LS27916 DIP dual in line package NAND SET RESET 306
MC14042B IC OR 4 CMOS IC 6 HIGH LOW 307
MC14043B MC14044B IC 3 tri state SET RESET SET RESET3 1 0 3 high impedancehiz HiZ IC MC14514B MC14515B 4 16 decoder D 4 16 MC74F803 4 D IC MC54 74F378 ENABLE D MC54 74F259 ENABLE 7 D D A 0 A 1 A 2 2 A 2 D Q 308
D D 7 38 D enable inhibit D D 309
one shot one shots VHDL very high speed hardware description language END VHDL key word VHDLcomment CPLD 2 2 19 3 3 10PLD 2 ieee LIBRARY ieee USE ieee std logic 1164 all D D clkin STD LOGIC Q1 Q2 Q1 Q2 Q1 OUT STD LOGIC Q2 Q1 Q Q2 Q Q1 Q2 BUFFER STD LOGIC 310
clk HIGHQ1 D 200 ns clk LOW D 0 400 ns clk LOW D 1500 ns Dclk LOW transd.vhd LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY transd IS PORT (D, clk : IN STD_LOGIC; Q1, Q2 : BUFFER STD_LOGIC); END transd; ARCHITECTURE a OF trans D IS BEGIN PROCESS (D, clk, Q1) -- IF PROCESS. BEGIN IF clk = '0' THEN --clk LOW,. Q1 <= Q1 ; Q2 <= NOT Q1; ELSEIF clk ='1' THEN --clk HIGH,. 311
END IF; END PROCESS; END a; Q1 <= D; Q2 <= NOT D; IF ELSIF ELSE IF clk PROCESS PROCESS END PROCESS IF ELSIF IF clk0, Q1, D 01 ENTITY set_reset IS PORT (set,res : IN STD_LOGIC; Q1,Q2 : BUFFER STD_LOGIC); END set_reset; ARCHITECTURE a OF set_reset IS BEGIN PROCESS (set, res, Q1) BEGIN Q2 <= NOT Q1; 312
IF (set = '0' AND res = '1') THEN Q1 <= '1'; Q2 <= '0'; ELSIF (set = '1' AND res = '0') THEN Q1 <= '0' ; Q2 <= '1' ; ELSIF (set = '0' AND res = '0') THEN Q1 <= '0'; Q2 <= '1'; END IF; END PROCESS; END a; LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY set_reset IS PORT (set,res : IN STD_LOGIC; Q1,Q2 : BUFFER STD_LOGIC); END set_reset; ARCHITECTURE a OF set_reset IS BEGIN PROCESS (set, reset, Q1) BEGIN Q2 <= NOT Q1; IF (set = '0' AND res = '1') THEN --. Q1 <= '1'; Q2 <= '0'; ELSIF (set = '1' AND res = '0' ) THEN --. Q1 <= '0'; Q2 <= '1'; ELSIF (set = '0' AND res = '0' ) THEN -- Q1 <= '1'; Q2 <= '1'; END IF ; END PROCESS ; END a; 313
7 41 7 41 optocoupler NAND NAND SET RESET 1,000 Hz 500 Hz 314
IC volt ohm milliammetervom VOM U19 1,000 Hz ON OFF VOM U23 0 1 V 1000 Hz 500 Hz U2A NAND U22 500 Hz U2 1 3 8 V U2A U22 U23 U2 74LS00 ICPC IC U23 pull down U23 IC IC IC IC ICIC ac coupling50 mv cm IC 500 Hz IC V CC U22 500 Hz TTL 500 Hz R 3 330 W R 3 500 Hz 315
R 3 R 3 45 V R 3 R 3 heat shrink tube SET RESET U15 LOW LOW S2 U15 R 3 316
2 1 Q Q NAND SET RESET LOW NOR SET RESET HIGH SET RESET SET RESET SET RESET NAND NOR enable inhibit Q Q D SET RESET SET RESET Q 1 0PRESET CLEAR D SET RESET D 7 42 317
1NAND SET RESET 2NAND SET RESET 3NAND D 4NAND NOR 5 6NOR SET RESET 7NOR SET RESET 8 CMOS D IC IC 9 5 D 10 5 D 11NOR D 12 13 LOW CLEAR PRESET D 14 SET RESET LOW 0 NAND SET RESET Q 0 1 15NOR 1674LS279 IC 1774LS0874LS00 74LS04 IC D 18 74LS02 IC NOR D 19 D 1CLOCK 1 0 D Q 20 D 318
21 logic probe 22 TTL 1 23 TTL 0 24 TTL 1 5 V IC 25 SET RESET LOW NAND SET RESET Q Q 26 25 IC 27 7 38 D NOR 28OR D 29 7 30 7 30 30 29 31 NOR set reset VHDL 32SET RESET VHDL 33 4 ENTITY set_reset IS PORT (set,reset : IN STD_LOGIC; Q1,Q2 : BUFFER STD_LOGIC); END set_reset; ARCHITECTURE a OF set_reset IS BEGIN PROCESS (set, res, Q1) BEGIN Q2 = NOT Q1; IF (set = '0' AND res = '1') THEN Q1 <= '1'; Q2 <= '0'; ELSIF (set = '1' AND res = '0') THEN Q1 <= '0'; Q2 <= '1'; ELSIF (set = '0' AND res = '0') THEN Q1 <= '1'; Q2 <= '1'; END IF; END PROCESS; 319
END a; 34 4 Library ieee; USE ieee.std_logic_1164.all; ENTITY transp IS BEGIN PORT (D,clk : IN STD_LOGIC; Q1,Q2 : OUT STD_LOGIC); END transp; ARCHITECTURE a OF trans IS BEGIN IF clk = '0' THEN Q1 <= Q1; Q2 <= NOT Q1; ELSIF clk = '1' THEN Q1 <= D; Q2 <= NOT D; END IF; END a; >>> SET RESET D >>> 7400 4 NAND IC 3 7408 4 AND IC 1 1 >>> 1. 74LS00 74HCT00 4 NAND IC 2. CLEAR PRESET D 74LS08 74HCT08 IC74LS00 74HTC00 IC 320
3. 2 4. 3 5. 6. CLEAR PRESET HIGH Q D D 1 khz TTL Q Q 8 1. IC 2. 3. NAND 4. 3 NAND NAND SET RESET >>> Multisim D Multisim >>> 1. Multisimtoolbox SET RESET NAND D 2. 7B 1 ms9b 3. 4. ON OFF 321
8.1 8.2 8.3 8.4 8.5 8.6 8.7 Master-Slave D and JK Flip-Flops c h a p t e r 08
324
8 1 D NAND Q toggle Q 1 Q0 Q 1 Q D 8 2 8 1 D HIGH D D 0 Q 0 OFF 0 OFFQ Q ns Q Q Q Q D 1 LOW OFF Q Q 1 1 0 OFF ns D 1 Q 325
NAND propagation delay OFF OFF Q 8 2 Q Q 1 2 10 JK JK flip flop 8 4 NAND JK JK JK Q Q K J J K 1 J K Q PRESET CLEAR LOW Q 1 0 LOW PRESET CLEAR JK PRESET LOW Q 1 PRESET 1 Q 1 Q 0 CLEAR PRESET SET PRESET NAND SET RESET CLEAR 326
CLEAR PRESET JK NAND SET RESET JK CLEAR PRESET 0 J K 0 0OFF NAND 0 1 NAND J K 0JK JK J 1 0K Q J K 1 1 HIGH NAND Q Q Q K Q J 327
JK Q CLEAR PRESET LOW CLEAR PRESET JK J K 1 J K J K J K 0 Q 8 5 JKCLEARPRESET JK Q Q CLEAR PRESET Q Q CLK Q Q CLK J K 8 4 328
8 7 nonoverlapping clock JK CP CP' 1 2180 CP CP' 329
JK CP AND enable CP AND AND Q Q enable AND AND 8 7 330
8 9JK shift counter A Q Q B J K B Q Q C J K CP A Q Q B Q Q B Q Q C Q Q C Q Q A J K Q K Q J CP A Q Q CPC Q Q CLEAR LOW Q 0 Q 1 CLEAR LOW HIGH CP A Q 0 C Q 331
CP A 1 CP A Q 1 B Q CP B Q 1 C CP A Q 0 A JK 5 CP B Q 0 6 CP Q 0 8 9 CP 1CP 0 120 A 1 CP B 1CP C 1 CPCP 6 CP 8 10 332
333
8 12 JK 74LS73 CLEAR JK 74LS76 7476 CLEAR PRESET JK IC 14 IC CLEAR PRESET CLOCK CLEAR 74LS78 JK 74LS109 334
JK IC IC JK JK Altera JK_FF vhd JK_FF.vhd JK VHDL 2 ieee LIBRARY ieee; USE ieee.std_logic_1164.all; Q1 Q2HIGH LOW Q2 Q1 Q1 Q2 Q1 Q2 ENTITY JK_FF IS PORT(J,K,clk:IN STD_LOGIC; Q1,Q2:BUFFER STD_LOGIC); END JK_FF; 335
7 transd HIGH LOW HIGH LOW VHDL clk EVENT clk HIGH LOW LOW HIGH clk EVENT AND clk= 0 HIGH LOW IF THEN HIGH LOW IF THEN PROCESS ARCHITECTURE a OF JK_FF IS BEGIN PROCESS (J,K,clk,Q1,Q2) BEGIN IF (clk'event AND clk = '0' ) THEN IF J K Q1 IF J<='0' AND K<='0' THEN Q1<=Q1; ELSIF J<='1' AND K<='0' THEN Q1<='1'; ELSIF J<='0' AND K<='1' THEN Q1<='0'; ELSIF J<='1' AND K<='1' THEN Q1<=Q2; -- -- -- -- 2 END IF IF IF PROCESS Q2 Q1 END a; END IF; END IF; Q2 <= NOT Q1; END PROCESS; JK_FF.vwfvector waveform file vwf 8 15 Q1 HIGH LOW Q2 Q1 CPLD J K S1 HD1 Q1 Q2 HD2 LED S3S4 S5 CPLD 336
LED CPLD S3 S4 S5 JK_FF.vhd Library ieee; USE ieee.std_logic_1164.all; ENTITY JK_FF IS PORT (J,K,clk:IN STD_LOGIC; Q1,Q2:BUFFER STD_LOGIC); END JK_FF; ARCHITECTURE a OF JK_FF IS BEGIN PROCESS (J,K,clk,Q1,Q2) BEGIN IF (clk'event AND clk = '0') THEN -- IF J<='0' AND K<='0' THEN -- Q1<=Q1; ELSIF J<='1' AND K<='0' THEN -- Q1<='1'; ELSIF J<='0' AND K<='1' THEN -- Q1<='0'; ELSIF J<='1' AND K<='1' THEN -- Q1<=Q2; END IF; -- IF END END IF; Q2 <= NOT Q1; --Q2 Q1 END PROCESS; END a; JK JK_pre_clr.vhd 3 IF IF pre clr pre clr HIGH IF LOW 337
HIGH IF clk EVENT AND clk1 THEN IF J K 3 END IF JK_pre_clr.vhd Library ieee; USE ieee.std_logic_1164.all; ENTITY JK_pre_clr IS PORT (J,K,clk,pre,clr:IN STD_LOGIC; Q1,Q2:BUFFER STD_LOGIC); END JK_pre_clr; ARCHITECTURE a OF JK_pre_clr IS BEGIN PROCESS (J,K,clk,Q1,Q2,pre,clr) BEGIN IF pre <='0' THEN -- Q1<='1'; Q2<='0'; ELSIF clr <='0' THEN -- Q1<='0'; Q2<='1'; ELSIF (PRE<='1' AND clr<='1') THEN IF (clk EVENT AND clk = '1') THEN -- (+) IF (J='0' AND K='0') THEN -- Q1<=Q1; ELSIF (J='1' AND K='0') THEN -- Q1<='1'; ELSIF (J='0' AND K='1') THEN -- Q1<='0'; ELSIF (J='1' AND K='1') THEN -- Q1<=Q2; END IF; END IF; END IF; Q2<= NOT Q1; --Q2 Q1 END PROCESS; END a; 8 16 JK_pre_clr.vhd Q1 LOW HIGH Q2 Q1 338
8 17 1 NAND U6B U6A SET RESET JK U7A JK J K HIGH CLEAR CLEAR AND AND U7BU9AU9B JK U7A Q ON OFF AND U7BU9A U9B 8 17 JK U7A Q 1U6C9 CLOCK IC8 NAND 2 JK CLOCK OFF JK U7A CLOCK 339
340
6 time sweep 50 ns cm storage single sweep U6D11 LOW U6D11 JK U7A 13 JK 341
IC solder sucker JK cold solder joint Q D Q D D JK J K JK 1JK Q Q CLEAR PRESET 2CLEAR PRESET JK 3J K 1 4J K Q Q JK 5J K 0 Q Q Q 1 2 10 D Q D 342
110 CP IC 2TTL CMOS TTL CMOS IC IC 3 JK NOR 2 IC 4 8 13 5 8 13 6NOR LOW CLEAR PRESET JK 7 LOW CLEAR PRESET JK 8 LOW CLEAR PRESET Q 9 HIGH CLEAR PRESET 8 10 J 0 K 0 JK 343
Q 11 12 8 10 13 8 10 JK CP even duty 14 8 4 Q Q HIGH 15 8 7 PRESET JK LOW 8 7 CP 1674LS75 D 1774LS74 IC 18TTL 5 IC 19 8 7 PRESET LOW 8 7 20 JK Q 21 8 1 8 1 22 8 7 CLEAR 344
23 Q J K 24 8 7 NOR 25 8 19 U7A J K 26 D NAND 27 8 11 28 8 11 JK U1A 29 8 10 1'2'5' 30 J K 1 5V JK 31VHDL LOW HIGH 32VHDL LOW HIGH preset clear preset clear LOW 33VHDL clk cp1 cp2 34 33 cp1 HIGH cp2 LOW LOW preset cp1 LOW cp2 HIGH LOW clear 35 VHDL 4 Library ieee; USE ieee.std_logic_1164.all; ENTITY FF IS PORT (J,K,clk:IN STD_LOGIC; Q1,Q2:OUT STD_LOGIC); END FF; ARCHITECTURE OF FF IS BEGIN PROCESS (J,K,clk,Q1,Q2) BEGIN IF (clk EVENT AND clk = '0') THEN IF J<='1' AND K<='1' THEN Q1<=Q1; ELSIF J<='1' AND K<='0' THEN Q1<='1'; ELSIF J<='0' AND K<='1' THEN Q1<='0'; ELSIF J<='0' AND K<='0' THEN 345
END IF; Q2 <= NOT Q1; END PROCESS; END a; Q1<=Q2; 36 VHDL 4 Library ieee; USE ieee.std_logic_1164.all; ENTITY _ff_pre_clr IS PORT (J,K,clk,pre,clr:IN STD_LOGIC; Q1,Q2:BUFFER STD_LOGIC); END _ff_pre_clr; ARCHITECTURE able OF _ff_pre_clr IS BEGIN PROCESS (J,K,clk,Q1,Q2,pre,clr); BEGIN IF pre <='0' THEN -- Q1<='1'; Q2<='0'; ELSIF clr <='0' THEN -- Q1<='0'; Q2<='1'; ELSIF (PRE<='1' AND clr<='1' ) THEN IF (clk EVENT AND clk = '1') THEN -- (+) IF (J='0' AND K='0') THEN -- Q1<=Q1; ELSIF (J='1' AND K='0') THEN -- Q1<='1'; ELSIF (J='0' AND K='1') THEN -- Q1<='0'; ELSIF (J='1' AND K='1') THEN -- Q1<=Q2; END IF; END IF; END IF; END PROCESS; END able; >>> JK JK 346
>>> 7476 JK IC 2 7408 4 AND IC 1 10 kw1 4 W 1 7404 6 IC 1 7432 4 OR IC 1 7410 3 3 NAND IC 1 7427 3 3 NOR IC 1 >>> 1. JK AND CP CP 2. Q Q CPCP 3. Q Q CPCP 4. 1 5. CPCP' A A B B C C 347
6. CPCP' A A B B C C 7. 8. 9. 8 10. 1. IC 2. 3. a JKCLEARPRESET5V JK 1 b JK NAND c Q 4. apreset CLEAR b c CP 348
>>> Multisim NAND JK Multisim >>> 1. Multisim JK NAND 2. 8B 1 ms9 3 3 3. 8B 1 ms9 349