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Preliminary -D8M -D8MF512 -D16M -D16MF512 Ver 1.6.7 August 12, 216 Advanced Digital Chips, Inc.

Ver 1.6.7 History Ver. Jul. 21, 211 Ver.1 Aug. 2, 211 Ver.2 Aug. 5, 211 Ver.2.1 Aug. 16, 211 Ver.2.2 Aug. 17, 211 Ver.2.3 Aug. 22, 211 Ver.2.4 Aug. 29, 211 1st version released 2nd version released 3rd version released Figure 28-1 Package Dimension changed. Figure 2-3 added. Figure 2-2 modified Pin layout Pin name fixed. Pin definition Pullup/Pulldown description modified Features: Analog IPs modified. MCPWM/QEI added. Operating Temp. fixed. Block diagram SPM -> SRAM Timer Wave Output Generation bit added. Ver.2.5 Sep. 15, 211 Pin diagram fixed. (pin 12) Pin description fixed. (pin 33, 111, 128) Ver.2.6 Sep. 22, 211 Ver.2.7 Oct. 2, 211 Ver.2.8 Oct. 4, 211 Ver.2.9 Oct. 21, 211 Ver.3. Oct. 25, 211 general description updated. Pinmux Description updated (ex. PA[] -> P.) Watch dog Register Address fixed. Timer description fixed (8ch->4ch) CRTC Register fixed ADC Register s address fixed. Flash Mapping Address fixed. SPI Register address fixed. DMA Register address fixed. UART Irda Register added Pinmux -> Port Alternative Functions (PAF) 1-2 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 Ver.3.2 Nov. 2, 211 Ver.3.3 Nov. 8, 211 Ver.3.5 Nov. 14, 211 Ver.3.6 Nov. 15, 211 Ver.3.7 Nov. 16, 211 Ver.3.8 Nov. 18, 211 Ver.3.9 Nov. 21, 211 Ver.4. Nov. 29, 211 Ver.4.1 Nov. 3, 211 Ver.4.2 Dec. 9, 211 Ver.4.3 Dec. 21, 211 Ver.4.4 Dec. 27, 211 Ver.4.5 Jan. 3, 212 Ver.4.6 Feb. 7, 212 Ver.4.7 Feb. 13, 212 ADC Sampling clock description Wrong description fixed (Alternate function pins, USB PHY control register) Wrong description fixed (Features, Dedicated PWM pin description, etc.) Output Compare function removed Miss typing corrected (Dedicated PWM) Serial DBG description removed. PLL Parameter Fin. added. I2S Clock control description added CRT Controller Resolution fixed. External SRAM Register description fixed ADC Conversion cycle description added Dedicated PWM function removed GPIO Block diagram updated. GPIO Schmitt input enable register added Some CRTC registers added. Short name of some INTC registers changed PWM function added Block diagram modified CRT -> LCD TWI Master Receive mode flow chart fixed. Cache write-back removed Internal SRAM description updated. LDO deleted. Area information of analog IPs removed. Office information updated. Advanced Digital Chips, Inc. CONFIDENTIAL 1-3

Ver 1.6.7 Ver.4.8 Feb. 24, 212 Ver.4.9 Feb. 27, 212 Ver.5. Mar. 2, 212 Ver.5.1 Mar. 15, 212 Ver.5.2 Mar. 18, 212 Ver.5.3 May. 3, 212 Ver.5.4 Jul. 17, 212 Ver.5.5 Sep. 21, 212 Ver.5.6 Nov. 16, 212 Ver.5.7 Dec. 17, 212 Ver.5.8 Feb. 7, 213 USB Host: TBD. LDO added. Block diagram updated. USB Host: TBD -> *TBD, description added Electrical Characteristic information of Analog IPs not needed removed PMU Write Enable Register fixed. (Clock Control Off by Halt) PMU Clock Control Register fixed. (WIRQ mode/enable deleted) Flash Register added. (FLSTS2, FLCKDLY) Power consumption added. 22.5.5 Mixer Out Register description fixed TWI Flowchart miss typing fixed PWM Override Control Register Description fixed. Power On Start Time added. Delete Special Event Register of PWM. Added the flip function at the LCD module Ver.5.9 Jun. 5, 213 Update Figure 12-2, 12-4 Ver.6. Nov. 6, 213 USB PHY D+/D- Pull-down enable bit added. Ver.6.1 Corrected the flip command register address of the LCD module Dec. 26, 213 Ver 1.6.1 Feb. 12, 214 Ver 1.6.2 Sept. 4, 214 Ver 1.6.4 Nov. 11, 215 Ver 1.6.6 july. 7, 216 USB host function is available Added ADC s characteristics GP6.X SHMIT enable bit configuration is corrected gpio register, twi baud rate register setting modify. 1-4 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 Ver 1.6.7 Aug. 12, 216 Remove trigger option in the ADC operation. Data Book 213 Advanced Digital Chips, Inc. All right reserved. No part of this document may be reproduced in any form without written permission from Advanced Digital Chips, Inc. Advanced Digital Chips, Inc. reserves the right to change in its products or product specification to improve function or design at any time, without notice. Office 22F, KeumkangPenterium IT Tower A dong, 81, Gwangyang-dong, Dong-gu, Anyang-si, Gyeonggi-do, 431-6, Korea Tel : +82-31-463-75 Fax : +82-31-463-7588 URL : http://www.adc.co.kr Advanced Digital Chips, Inc. CONFIDENTIAL 1-5

Ver 1.6.7 CONTENTS 1 Descriptions and Features... 17 1.1 General Description... 17 1.2 Features... 18 2 Block Diagram & Pin Descriptions... 2 2.1 Block Diagram... 2 2.2 Pin Layout... 21 2.3 Pin Definition... 23 2.4 Pin Description... 29 3 Memory Architecture and Booting mode... 32 3.1 Memory Map... 32 3.2 Embedded Memories... 33 3.2.1 Internal SRAM for Instruction... 33 3.2.2 Internal SRAM for Data... 33 3.2.3 Internal SRAM Registers... 33 3.2.4 Internal SRAM Register Setting... 35 3.3 Memory Mapped I/O... 35 3.4 Boot Mode... 37 3.4.1 Debugger Boot Mode... 37 3.4.2 Normal Boot Mode... 37 3.4.3 Flash Boot Mode... 37 3.4.4 NOR Flash Boot Mode... 37 3.4.5 NAND Flash Auto Boot Mode... 37 4 System Reset and Clock... 38 4.1 Reset... 38 4.1.1 System Reset... 38 4.1.2 Power On Start Time... 38 4.2 Clocks... 4 4.3 Power Management Unit Registers... 41 4.3.1 PMU Write Enable Register (PMUWREN)... 41 4.3.2 Clock Control Register (CLKCON)... 42 4.3.3 PLL Control Register (PLLCON)... 43 4.3.4 Sound Control Register (SNDCLKCON)... 44 4.3.5 AHB Clock Control Register (HCLKCON)... 44 4.3.6 APB Clock Control Register (PCLKCON)... 45 4.3.7 USB PHY Control Register (USBPHYCON)... 45 5 Coprocessor... 46 5.1 Features... 46 5.2 Coprocessor Description... 47 5.3 Coprocessor Control Registers... 48 5.3.1 System Coprocessor Status Register (SCPR15)... 48 5.3.2 Master Command Register (SCPR15)... 48 5.3.3 Supervisor Stack Point Register (SCPR14)... 49 5.3.4 User Stack Point Register (SCPR13)... 49 5.3.5 Vector Base Register (SCPR12)... 49 5.3.6 Invalidate Cache Line and Lock Register (SCPR11)... 49 5.3.7 Memory Bank Configuration Register (SCPR9)... 5 5.3.8 Sub-Bank Configuration Register (SCPR8)... 51 5.3.9 Sub-Bank Address Register (SCPR5)... 51 6 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 5.3.1 General Access Point Data Register (SCPR4)... 52 5.3.11 General Access Point Index Register (SCPR3)... 52 6 Watchdog Timer... 54 6.1 Register Description... 54 6.1.1 Watchdog Timer Control Register (WDTCTRL)... 54 6.1.2 Watchdog Timer Counter Value Register (WDTCNT)... 54 7 GPIO (General Purpose I/O)... 55 7.1 Features... 55 7.2 Block Diagram... 55 7.3 Function Description... 56 7.3.1 Port Control... 56 7.3.2 Port Edge Detect... 56 7.3.3 Port Alternate Functions... 56 7.4 Register Description... 59 7.4.1 Port Direction Registers ( GPxDIR )... 59 7.4.2 Port Direction Output Mode Setting Registers ( GPxODIR )... 59 7.4.3 Port Direction Input Mode Setting Registers ( GPxIDIR )... 59 7.4.4 Port Output Data Level Registers ( GPxOLEV )... 6 7.4.5 Port Output Data Registers ( GPxDOUT )... 6 7.4.6 Port Output Data High Level Setting Registers ( GPxOHIGH )... 6 7.4.7 Port Output Data Low Level Setting Registers ( GPxOLOW )... 6 7.4.8 Port Input Data Level Registers ( GPxILEV )... 61 7.4.9 Port Pull-up Status Registers ( GPxPUS )... 61 7.4.1 Port Pull-up Enable Registers ( GPxPUEN )... 61 7.4.11 Port Pull-up Disable Registers ( GPxPUDIS )... 62 7.4.12 Port Rising Edge Detect Registers ( GPxRED )... 63 7.4.13 Port Falling Edge Detect Registers ( GPxFED )... 63 7.4.14 Port Edge Detect Status Registers ( GPxEDS )... 64 7.4.15 Port Open Drain Mode Control Registers ( GPxODM )... 64 7.4.16 Port Schmitt Input Enable Registers ( GPxSHMT )... 64 7.4.17 Port Pull-down Status Registers ( GPxPDS )... 65 7.4.18 Port Pull-down Enable Registers ( GPxPDEN )... 65 7.4.19 Port Pull-down Disable Registers ( GPxPDDIS )... 65 8 Interrupt Controller... 66 8.1 Features... 66 8.2 Function Description... 66 8.2.1 Interrupt Vector and Priority... 67 8.2.2 External Interrupt (EIRQx)... 69 8.2.3 Internal Interrupt Mode... 69 8.2.4 Interrupt Pending and Interrupt Pending Clear... 7 8.2.5 Interrupt Enable... 7 8.2.6 Interrupt Mask Set/Clear Register... 7 8.3 Register Description... 71 8.3.1 Interrupt Pending Clear Register (INTPENDCLR)... 71 8.3.2 External Interrupt Mode and External PIN Level Register (EINTMOD).. 71 8.3.3 Internal Interrupt Mode Register (IINTMODn)... 72 8.3.4 Interrupt Pending Register (INTPENDn)... 73 8.3.5 Interrupt Enable Register (INTENn)... 74 8.3.6 Interrupt Mask Status Register (INTMASKn)... 75 8.3.7 Interrupt Mask Set Register (INTMASKSETn)... 75 8.3.8 Interrupt Mask Clear Register (INTMASKCLRn)... 76 8.3.9 Programmable Interrupt Priority Enable Register (PIPENR)... 77 Advanced Digital Chips, Inc. CONFIDENTIAL 7

Ver 1.6.7 8.3.1 Interrupt Priority Vector n Register (IPVRn)... 77 9 DMA... 78 9.1 Features... 78 9.2 Block Description... 79 9.3 Function Description... 8 9.3.1 DMA Operation... 8 9.3.2 Linked List Operation... 81 9.3.3 Auto Reload Operation... 84 9.3.4 Peripheral Interface... 86 9.4 Register Description... 89 9.4.1 DMA Interrupt Status ( DMAIntStatus )... 89 9.4.2 DMA Terminal Count Interrupt Status ( DMATCIntStatus )... 89 9.4.3 DMA Terminal Count Interrupt Clear ( DMATCIntClr )... 89 9.4.4 DMA Error Interrupt Status ( DMAErrorIntStatus )... 89 9.4.5 DMA Error Interrupt Clear ( DMAErrorIntClr )... 9 9.4.6 DMA Block Interrupt Status ( DMABlockIntStatus )... 9 9.4.7 DMA Block Interrupt Clear ( DMABlockIntClr )... 9 9.4.8 DMA Raw Terminal Count Interrupt Status ( DMARawTCIntStatus )... 9 9.4.9 DMA Raw Error Interrupt Status ( DMARawErrorIntStatus )... 9 9.4.1 DMA Enabled Channel Status ( DMAEnbldChn )... 91 9.4.11 DMA Software Burst Request ( DMASoftBReq )... 91 9.4.12 DMA Software Single Request ( DMASoftSReq )... 91 9.4.13 DMA Software Last Burst Request ( DMASoftLBReq )... 91 9.4.14 DMA Software Last Single Request ( DMASoftLSReq )... 92 9.4.15 Channel Source Address Register ( ChnSrcAddr )... 92 9.4.16 Channel Destination Address Register ( ChnDstAddr )... 92 9.4.17 Channel Linked List Item Register ( ChnLLI )... 93 9.4.18 Channel Control Register ( ChnCntl )... 93 9.4.19 Channel Configuration Register ( ChnCfg )... 95 9.4.2 Channel Source Gather Address Register ( ChnSrcGaAddr )... 96 9.4.21 Channel Destination Scatter Address Register ( ChnDstScaAddr )... 97 9.4.22 Channel Auto Reload Count Register ( ChnAutoReloadCnt )... 97 9.5 Program Guide... 98 9.5.1 Sumary of Register... 98 9.5.2 Programming Sequence... 98 9.5.3 Program Consideration... 99 1 Flash Memory Controller... 1 1.1 Feature... 1 1.2 Function Description... 1 1.2.1 Flash Mode Register (FLMOD)... 1 1.2.2 Flash Baudrate Register (FLBRT)... 1 1.2.3 Flash Chip Select High Pulse Width Register (FLCSH)... 1 1.2.4 Flash Command Register (FLCMD)... 11 1.2.5 Flash Status Register (FLSTS)... 11 1.2.6 Flash 2nd Status Register (FLSTS2)... 11 1.2.7 Flash Sector/Block Erase Address Register (FLSEA/FLBEA)... 11 1.2.8 Flash WIP Check Period Register (FLWCP)... 11 1.2.9 Flash Clock Delay Register (FLCKDLY)... 11 1.3 Register Description... 12 1.3.1 Flash Mode Register (FLMOD)... 12 1.3.2 Flash Baudrate Register (FLBRT)... 13 1.3.3 Flash Chip Select High Pulse Width Register (FLCSH)... 13 8 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 1.3.4 Flash Performance Enhance Mode Register (FLPEM)... 13 1.3.5 Flash Command Register (FLCMD)... 13 1.3.6 Flash Status Register (FLSTS)... 13 1.3.7 Flash Sector Erase Address Register (FLSEA)... 13 1.3.8 Flash Block Erase Address Register (FLBEA)... 14 1.3.9 Flash Data Register (FLDAT)... 14 1.3.1 Flash WIP Check Period Register (FLWCP)... 14 1.3.11 Flash Clock Delay Register (FLCKDLY)... 14 1.3.12 Flash 2 nd Status Register (FLSTS2)... 14 11 Local Memory Controller... 15 11.1 Register Description... 15 11.1.1 SDRAM Control Register (MEMCON)... 15 11.1.2 SDRAM Clock Delay Register (MEMCLKCON)... 15 11.1.3 SDRAM Refresh Control Register (MEMREFCON)... 16 12 External SRAM Controller... 17 12.1 Function Description... 17 12.2 Register Description... 19 12.2.1 External SRAM_nCS Area Control Register (CSCTRL)... 19 12.2.2 External SRAM_nCS[3:1] Area Control Register (CSxCTRL)... 11 13 NAND Flash Controller... 111 13.1 Features... 111 13.2 Function Description... 112 13.3 ECC Operation... 112 13.4 Register Description... 114 13.4.1 NAND Flash Memory Control Register (NFCTRL)... 114 13.4.2 NAND Flash Memory Command Set Register (NFCMD)... 115 13.4.3 NAND Flash Memory Address Register (NFADR)... 115 13.4.4 NAND Flash Memory Data Register (NFDATA)... 115 13.4.5 NAND Flash Memory Operation Status Register (NFSTAT)... 115 13.4.6 NAND Flash Memory ECC(Error Correction Code) Register (NFECC). 116 13.4.7 NAND Flash Memory Configuration Register (NFCFG)... 117 13.4.8 NAND Flash Memory ECC Code for LSN data (NFECCL)... 118 13.4.9 NAND Flash Memory Error Corrected Data Register (NFECD)... 118 13.4.1 NAND Flash Memory Spare Address Register (NFSPADR)... 118 13.4.11 NAND Flash Memory MLC ECCn Register (NFECCn)... 118 13.4.12 NAND Flash Memory Error Location n Register (NFERRLOCn)... 119 13.4.13 NAND Flash Memory Error Pattern n Register (NFERRPTNn)... 119 13.4.14 NAND Flash Memory ID Register (NFMID)... 119 14 SD Host controller... 12 14.1 Features... 12 14.2 Block Diagram... 12 14.3 SD Card Protocol... 12 14.4 Register Description... 121 14.4.1 SDHC Control Register (SDHCCON)... 121 14.4.2 SDHC Status Register (SDHCSTAT)... 121 14.4.3 SDHC Clock Divide Register (SDHCCD)... 123 14.4.4 SDHC Response Time Out Register (SDHCRTO)... 124 14.4.5 SDHC Read Data Time Out Register (SDHCRDTO)... 124 14.4.6 SDHC Block Length Register (SDHCBL)... 124 14.4.7 SDHC Number of Block Register (SDHCNOB)... 124 14.4.8 SDHC Interrupt Enable Register (SDHCIE)... 125 14.4.9 SDHC Command Control Register (SDHCCMDCON)... 126 Advanced Digital Chips, Inc. CONFIDENTIAL 9

Ver 1.6.7 14.4.1 SDHC Command Argument Register (SDHCCMDA)... 126 14.4.11 SDHC Response FIFO Access Register (SDHCRFA)... 127 14.4.12 SDHC Data FIFO Access Register (SDHCDFA)... 127 15 USB Device... 128 15.1 Features... 128 15.2 Register Summary... 128 15.2.1 USB Function Address Register... 129 15.2.2 USB Power Management Register... 129 15.2.3 USB Interrupt Registers... 129 15.2.4 USB Interrupt Enable Registers... 129 15.2.5 Frame Number Registers... 129 15.2.6 Index Register... 129 15.2.7 MAXP Register... 129 15.2.8 EP Control Register... 129 15.2.9 IN Control Registers... 129 15.2.1 Out Control Registers... 129 15.2.11 Out Write Count Registers... 129 15.2.12 Endpoint FIFO Access Registers... 129 15.3 Register Description... 13 15.3.1 USB Function Address Register (USBFA)... 13 15.3.2 USB Power Management Register (USBPM)... 13 15.3.3 USB Endpoint Interrupt Register (USBEPI)... 131 15.3.4 USB Interrupt Register (USBINT)... 132 15.3.5 Endpoint Interrupt Enable Register (USBEPIEN)... 132 15.3.6 USB Interrupt Enable Register (USBINTEN)... 132 15.3.7 USB Low Byte Frame Number Register (USBLBFN)... 132 15.3.8 USB High Byte Frame Number Register (USBHBFN)... 133 15.3.9 USB Index Register (USBIND)... 133 15.3.1 USB MAXP Register (USBMP)... 133 15.3.11 USB EP Control Register (USBEPC)... 134 15.3.12 USB IN Control 1 Register (USBIC1)... 135 15.3.13 USB IN Control 2 Register (USBIC2)... 136 15.3.14 USB Out Control Register 1 (USBOC1)... 137 15.3.15 USB OUT Control Register 2 (USBOC2)... 138 15.3.16 USB Low Byte Out Write Count Register (USBLOWC)... 138 15.3.17 USB High Byte Out Write Count Register (USBHBOWC)... 138 15.3.18 EP FIFO Data Register (USBEP)... 139 15.3.19 EP1 FIFO Data Register (USBEP1)... 139 15.3.2 EP2 FIFO Data Register (USBEP2)... 139 15.3.21 EP3 FIFO Data Register (USBEP3)... 139 15.3.22 EP4 FIFO Data Register (USBEP4)... 139 16 LCD Controller... 14 16.1 Features... 14 16.2 Register Description... 14 16.2.1 LCD Base Address Register(LCDBA)... 141 16.2.2 LCD Horizontal Total Register(LCDHT)... 141 16.2.3 LCD Horizontal Sync. Start / End Register(LCDHS)... 141 16.2.4 LCD Horizontal Active Start / End Register(LCDHA)... 141 16.2.5 LCD Vertical Total Register(LCDVT)... 142 16.2.6 LCD Vertical Sync. Start / End Register(LCDVS)... 142 16.2.7 LCD Vertical Active Start / End Register(LCDVA)... 142 16.2.8 LCD Display Current X / Y Position Register(LCDXY)... 143 1 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 16.2.9 LCD Status Register(LCDSTAT)... 143 16.2.1 LCD Control Register(LCDCON)... 143 16.2.11 LCD Overlay & DAC Control Register(LCDOEDAC)... 144 16.2.12 LCD VESA Power Management Control Register(LCDPM)... 145 16.2.13 LCD Base Address n Register (LCDBARn)... 145 16.2.14 LCD Frame Sync. Count Register (LCDFRAMECNT)... 145 16.2.15 LCD Horizontal Width Register (LCDHWIDTH)... 145 16.2.16 LCD Flip Control Register (LCDFCTL)... 145 17 Timers... 152 17.1 Features... 152 17.2 Function Description... 152 17.2.1 15-bit Pre-scaler with clock source selection... 152 17.2.2 Timer/Counter... 153 17.2.3 Pulse Width Modulation (PWM)... 154 17.2.4 Capture... 156 17.3 Register Description... 158 17.3.1 Timer Pre-scale Control Registers ( TPxCTRL )... 158 17.3.2 Timer Control Registers ( TMxCTRL)... 159 17.3.3 Timer Counter / PWM Period Registers ( TMxCNT )... 16 17.3.4 Capture Counter Registers / PWM Duty Registers ( TMxDUT )... 16 17.3.5 PWM Pulse Count Registers ( TMxPUL )... 16 18 SPI (Serial Peripheral Interface)... 161 18.1 Features... 161 18.2 Block Diagram... 161 18.3 Function Description... 162 18.3.1 SPI Pins... 162 18.3.2 SPI Operating Modes... 163 18.3.3 SCK Phase and Polarity Control... 164 18.3.4 Data Transfer Timing... 164 18.3.5 SPI Serial Clock Baud Rate... 166 18.3.6 Open-Drain Output for Wired-OR... 166 18.3.7 Transfer Size and Direction... 166 18.3.8 Write Collision... 166 18.3.9 MODE Fault... 166 18.3.1 Interrupt... 167 18.4 Register Description... 168 18.4.1 SPI Control Register (SPICTRL)... 168 18.4.2 SPI Baud Rate Register (SPIBR)... 168 18.4.3 SPI Status Register (SPISTAT)... 169 18.4.4 SPI Data Register (SPIDATA)... 169 18.4.5 SPI nss Control Register (nssctrl)... 17 18.4.6 SPI Interrupt Mask Register (SPIINT)... 17 19 TWI (Two Wired Interface)... 171 19.1 Features... 171 19.2 Block Diagram... 171 19.3 Function Description... 172 19.3.1 DATA TRANSFER FORMAT... 172 19.3.2 START AND STOP CONDITION... 172 19.3.3 ACK SIGNAL TRANSMISSION... 173 19.3.4 READ-WRITE OPERATION... 173 19.3.5 BUS ARBITRATION PROCEDURES... 174 19.3.6 ABORT CONDITIONS... 175 Advanced Digital Chips, Inc. CONFIDENTIAL 11

Ver 1.6.7 19.3.7 Operational Flow Diagrams... 175 19.4 Register Description... 18 19.4.1 TWI Control Register (TWICTRL)... 18 19.4.2 TWI Status Register (TWISTAT)... 181 19.4.3 TWI Address Register(TWIADR)... 182 19.4.4 TWI Data Register (TWIDATA)... 182 19.4.5 TWI Baud-Rate Register (TWIBR)... 182 19.4.6 TWI Baud-Rate 1 Register (TWIBR1)... 183 2 UART... 184 2.1 Features... 184 2.2 Block Diagram... 184 2.3 Function Description... 185 2.3.1 Serial Data Format... 185 2.3.2 UART Baud Rate... 187 2.4 Register Summery... 188 2.5 Register Description... 189 2.5.1 UART Channel Receiver Buffer Registers ( UxRB )... 189 2.5.2 UART Channel Transmitter Holding Registers ( UxTH )... 189 2.5.3 UART Channel Interrupt Enable Registers ( UxIE )... 189 2.5.4 UART Channel Interrupt Identification Register ( UxII )... 189 2.5.5 UART Channel FIFO Control Register ( UxFC )... 19 2.5.6 UART Channel Line Control Register ( UxLC )... 191 2.5.7 UART Channel Line Status Register ( UxLS )... 191 2.5.8 UART Channel Divisor Latch LSB Register ( UxDLL )... 192 2.5.9 UART Channel Divisor Latch MSB Register ( UxDLM )... 192 2.5.1 UART IrDA Mode Register ( UxIRM )... 193 21 USB Host Controller... 194 21.1 Features... 194 21.2 Operational Registers... 194 22 Sound Mixer... 195 22.1 Features... 195 22.2 Block Diagram... 195 22.3 Low Pass Filter for Digital Modulator... 196 22.4 I2S Frequency Control... 196 22.5 Register Description... 197 22.5.1 Mixer Control Register (MIXER_ CON)... 197 22.5.2 Mixer Volume Register (MIXER_VOL)... 198 22.5.3 Mixer Buffer Status Register (MIXER_BST)... 198 22.5.4 Mixer Data Register (MIXER_DAT)... 198 22.5.5 Mixer Out Register (MIXER_OUT)... 199 22.5.6 Mixer Interrupt Status Register (MIX_IST)... 199 23 ADC Controller... 2 23.1 Features... 2 23.2 Register Description... 21 23.2.1 ADC Control Register (ADCCTRL)... 21 23.2.2 ADC Data Register (ADCDATA)... 21 23.2.3 ADC FIFO Register (ADCFIFO)... 21 23.2.4 ADC Status Register (ADCSTAT)... 22 24 PWM (Pulse Width Modulation)... 23 24.1 Features... 23 24.2 Function Description... 23 24.2.1 Edge Aligned PWM mode... 23 12 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 24.2.2 Single Event PWM mode... 24 24.2.3 Center Aligned PWM mode... 24 24.2.4 Center Aligned PWM with Double Update mode... 25 24.2.5 Dead Time Control... 25 24.3 Register Description... 26 24.3.1 PWM Mode Register (PWMMOD)... 26 24.3.2 PWM Counter Register (PWMCNT)... 26 24.3.3 PWM Period Register (PWMPRD)... 26 24.3.4 PWM Control Register (PWMCON)... 27 24.3.5 Dead Time Control Register (DTCON)... 27 24.3.6 Dead Time Control 1 Register (DTCON1)... 28 24.3.7 Fault A / B Control Register (FLTACON / FLTBCON)... 28 24.3.8 Override Control Register (OVDCON)... 29 24.3.9 PWM Duty Register (PWMDUT~3)... 21 24.3.1 PWM Interrupt Status Register (IRQSTAT)... 21 25 Electrical Characteristic... 211 25.1 DC Electrical Characteristic... 211 25.2 Operating Conditions... 211 25.3 LDO Electrical Specification... 212 25.4 POR Electrical Specification... 213 25.5 PLL Electrical Specification... 213 25.6 ADC Electrical Specification... 214 25.7 Power Consumption... 214 26 Package Dimension... 215 Advanced Digital Chips, Inc. CONFIDENTIAL 13

Ver 1.6.7 FIGURES FIGURE 2-1 ADSTAR BLOCK DIAGRAM... 2 FIGURE 2-2 ADSTAR D8/16MF512 PIN LAYOUT... 21 FIGURE 2-3 ADSTAR D8/16M PIN LAYOUT... 22 FIGURE 3-1 MEMORY MAP... 32 FIGURE 4-1 RESET... 38 FIGURE 4-2 POWER ON START TIME DIAGRAM... 39 FIGURE 7-1 GPIO BLOCK DIAGRAM... 55 FIGURE 8-1 EXTERNAL INTERRUPT MODE... 69 FIGURE 9-1 DMA BLOCK DIAGRAM... 79 FIGURE 9-2 DMA TRANSFER HIERARCHY... 8 FIGURE 9-3 LINKED LIST... 82 FIGURE 9-4 MULTI BLOCK TRANSFER... 82 FIGURE 9-5 GATHERING BY USING LLI... 83 FIGURE 9-6 AUTO RELOAD OPERATION TRANSFER HIERARCHY... 84 FIGURE 9-7 SCATTER WITH AUTO RELOAD OPERATION... 85 FIGURE 9-8 GATHER WITH AUTO RELOAD OPERATION... 86 FIGURE 9-9 DMA HANDSHAKE SIGNALS... 87 FIGURE 9-1 TIME DIAGRAM OF DMA REQUEST... 88 FIGURE 12-1 EXTERNAL 8-BIT SRAM MEMORY TIMING DIAGRAM... 17 FIGURE 12-2 CONNECTION 8-BIT SRAM MEMORY... 17 FIGURE 12-3 EXTERNAL 16-BIT SRAM MEMORY TIMING DIAGRAM... 18 FIGURE 12-4 CONNECTION 16-BIT SRAM MEMORY... 18 FIGURE 13-1 NAND FLASH CONTROLLER BLOCK DIAGRAM... 111 FIGURE 13-2 READ/WRITE TIMING DIAGRAM OF NAND FLASH MEMORY... 112 FIGURE 14-1 SDHC BLOCK DIAGRAM... 12 FIGURE 17-1 PRE-SCALER BLOCK DIAGRAM... 152 FIGURE 17-2 TIMER OPERATION... 153 FIGURE 17-3 PWM OPERATION... 155 FIGURE 17-4 CAPTURE MODE OPERATION... 156 FIGURE 18-1 SPI BLOCK DIAGRAM... 161 FIGURE 18-2 SCK PHASE AND POLARITY... 164 FIGURE 18-3 TRANSFER TIMING WHEN CPHA =... 165 FIGURE 18-4 TRANSFER TIMING WHEN CPHA = 1... 165 FIGURE 18-5 1-BYTE TRANSFER VS. STATUS AND INTERRUPT... 167 FIGURE 18-6 N-BYTES TRANSFER VS. STATUS AND INTERRUPT... 167 FIGURE 19-1 TWI BLOCK DIAGRAM... 171 FIGURE 19-2 TWI-BUS INTERFACE DATA FORMAT... 172 FIGURE 19-3 DATA TRANSFER ON THE TWI-BUS... 172 FIGURE 19-4 ACKNOWLEDGEMENT OF TWI... 173 FIGURE 19-5 BUS ARBITRATION 1 OF TWI... 174 FIGURE 19-6 BUS ARBITRATION 2... 174 FIGURE 19-7 TWI INITIALIZATION FLOW CHAR... 175 FIGURE 19-8 MASTER TRANSMIT FLOW CHAR... 176 FIGURE 19-9 MASTER RECEIVE FLOW CHAR... 177 FIGURE 19-1 SLAVE MODE FLOW CHART (POLLING)... 178 FIGURE 19-11 SLAVE MODE FLOW CHART (INTERRUPT)... 179 FIGURE 2-1 UART BLOCK DIAGRAM... 184 FIGURE 2-2 UART LCR REGISTER SETTING AND SERIAL DATA FORMAT... 186 FIGURE 22-1 MIXER BLOCK DIAGRAM... 195 FIGURE 22-2 LOW PASS FILTER FOR DIGITAL MODULATOR... 196 FIGURE 22-3 I2S PRE-SCALER... 196 FIGURE 24-1 EDGE ALIGNED PWM... 23 FIGURE 24-2 SINGLE EVENT PWM... 24 FIGURE 24-3 CENTER ALIGNED PWM... 24 14 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 FIGURE 24-4 CENTER ALIGNED PWM WITH DOUBLE UPDATE... 25 FIGURE 24-5 DEAD TIME INSERTION DIAGRAM... 25 FIGURE 26-1 PACKAGE DIMENSION... 215 Advanced Digital Chips, Inc. CONFIDENTIAL 15

Ver 1.6.7 TABLES TABLE 2-1 ADSTAR PIN DEFINITIONS 128-PIN... 23 TABLE 3-1 MEMORY MAPPED I/O REGISTER... 35 TABLE 5-1 REAL MEMORY MAP... 46 TABLE 5-2 COPROCESSOR REGISTER DESCRIPTION... 47 TABLE 7-1 INTERNAL PULL-UP RESISTANCE CHARACTERISTICS... 56 TABLE 8-1 INTERRUPT VECTOR & PRIORITY... 67 TABLE 15-1 ENDPOINT LIST... 128 TABLE 15-2 USB CORE REGISTER LIST... 128 TABLE 16-1 LCD CONTROLLER REGISTERS TABLE... 14 TABLE 16-2 NATIONAL TV SIGNAL STANDARD... 146 TABLE 16-3 32 BIT VIDEO DATA SERIALIZATION... 149 TABLE 16-4 REGISTERS PROGRAMMING RESOLUTION REFERENCE TABLE FOR LCDC... 151 TABLE 18-1 SPI PIN FUNCTIONS... 162 TABLE 2-1 UART BAUD RATE... 187 TABLE 2-2 UART REGISTER SUMMERY... 188 TABLE 2-3 UART INTERRUPT CONTROL FUNCTION... 19 TABLE 21-1 USB HOST REGISTERS LIST... 194 TABLE 22-1 I2S SAMPLING FREQUENCY(LRCK) AND MCLK CLOCK... 196 TABLE 22-2 I2S SAMPLING FREQUENCY AND SERIAL BIT CLOCK... 196 TABLE 25-1 I/O DC ELECTRICAL CHARACTERISTIC... 211 TABLE 25-2 I/O RECOMMENDED OPERATING CONDITIONS... 211 TABLE 25-3 LDO ELECTRICAL SPECIFICATIONS... 212 TABLE 25-5 POR SPECIFICATION (UNLESS OTHERWISE SPECIFIED, TOPR=25 C, VDD=1.8V)... 213 TABLE 25-6 PLL DC CHARACTERISTICS (UNLESS OTHERWISE SPECIFIED, TOPR=25 C, VDD=1.8V)... 213 TABLE 25-7 PLL INPUT FREQUENCY (UNLESS OTHERWISE SPECIFIED, TOPR=25 C, VDD=1.8V)... 213 TABLE 25-8 ADC RECOMMENDED OPERATING CONDITIONS... 214 TABLE 25-9 ADC DC CHARACTERISTICS (UNLESS OTHERWISE SPECIFIED, TOPR=25 C, VDD=1.8V)... 214 TABLE 25-1 ANALOG CHARACTERISITCS... 214 TABLE 25-11 POWER CONSUMPTION FROM DIFFERENT CONDITIONS... 214 16 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 1 DESCRIPTIONS AND FEATURES 1.1 General Description 는최대 18MHz 의빠른동작속도를가진 32 비트마이크로컨트롤러이며특히칩내부에내장되는메모리가기존의플래시메모리뿐만아니라 SDRAM 까지내장되어다양한어플리케이션에적용할수있다. PART NAME FLASH SDRAM -D8M - 8MB -D8MF512 512KB 8MB -D16M - 16MB -D16MF512 512KB 16MB 는칩외부에연결되거나내부에내장된 Quad Flash 로동작하게된다. Flash 는프로그램코드와데이터용도로같이사용가능하며, 설정에의해 Quad 데이터비트를사용하여매우빠른접근이가능하다. 또한 JTAG Programming 을통하여빠른프로그램다운로드가가능하다. CPU 는프로그램메모리와데이터메모리를액세스하기위한버스를독립적으로구현되어있으며 ( 하버드구조 ), 5 단파이프라인의 EISC 구조로매우빠른명령처리를수행한다. 별도의하드웨어로구성된 LCD Controller 는 RGB888 또는 RGB565 출력을지원하며동급 최대 8x6 의해상도를지원하고 Graphic Library 와 JPEG Decoding Library 를 제공함으로써 칩하나만으로도 LCD 를사용하는스마트어플리케이션에최적의 솔루션이된다. 이외에제공되는 MP3 Decoding Library 와 Sound Mixer 는음성, 효과음, 배경음등으로활용할수있으며 4 채널 1 비트 ADC(1MSPS) 는센서나외부데이터를활용할수있게한다. 특히 는보안적인측면도강화를하여사용자가 24 비트의 Key 를최초한번 Write 하여 Copy Protection 을구현한다. 또한외부에 SRAM, FLASH Memory, SD Card 를확장할수있고특히 NAND FLASH 의경우 SLC Type 뿐만아니라 24bit ECC 채용으로 MLC Type 을사용할수있으므로전체적인시스템단가를낮출수있다. 다양한통신수단으로는 USB 2. Full-Speed Device/Host 5 채널 UART, 2 채널 SPI, 2 채널 I2S, TWI 등을제공하며 8 채널 DMA 는보다빠른수행을할수있게한다. 는스마트가전등의스마트어플리케이션, LCD 를사용하여 G.U.I 환경의공장자동화시스템, 출입통제시스템, 스마트그리드, 사인패드, 각종프린터, POS, 바코드시스템, POP 모니터등에적용할수있다. 개발환경으로는 GCC 기반의컴파일러와소스편집및다운로드, 디버깅환경을제공하는 EISC STUDIO, 레퍼런스회로도, 각종 Library, 예제소스코드를에이디칩스홈페이지자료실에서아무런제약없이다운로드할수있으며, 개발보드와다운로드 / 디버깅툴인 E- con 은저렴한가격에판매를하고있다. 양산툴로는조립전의칩을 7 개의소켓이있는 Advanced Digital Chips, Inc. CONFIDENTIAL 17

Ver 1.6.7 갱라이터로 WRITE 하는방법과칩이조립된상태의타겟보드의전원을이용하여 stand alone 타입의 EISC HANDY 로하나씩다운로드하는방법을제공한다. 1.2 Features High-performance, Low-power 32-bit EISC Microprocessor 32-bit EISC Architecture AE32C-Lucida Harvard Architecture 5-Stage Pipelining 1 Cycle 32bit MAC Up to 18MIPS Throughput at 18MHz 8KB 2-way Instruction Cache 8KB 2-way Data Cache JTAG Debugger Core Debugger Bus Debugger Embedded Memory 2KBytes Internal SRAM for Instruction 3KBytes Internal SRAM for Data 8/16Mbytes SDRAM Optional 512KBytes Flash (More than 1, erase/program cycles) External Memory Interface 8 or 16-bit data, up to 18-bit addressing SRAM Interface 8-bit NAND Flash Interface supports SLC and MLC (4/24-bit ECC) type Boot Mode ROM Booting NAND Flash Booting Flash Booting JTAG Interface Boundary-scan capabilities Extensive On-chip Debug Support Programming of Fuses through the JTAG Interface LCD Controller RGB 888 or 565 output Supports up to 8 x 6 resolution display in RGB mode USB 2. Full-Speed Device/Host Compatible Supports Full-speed Data Rate 12Mbps Copy Protection 24-bit key-protected only-one programmable bits SD-Card Interface Supports single/quad Sound Mixer 2ch. I2S, 2ch Digital Modulator Other Peripherals 32-bit Watchdog Timer 18 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 8-ch DMA Interrupt Controller with 2 External IRQ 4 Channel 16-bit Timer/Counter with 15-bit Pre-scaler, Capture, PWM 5 Channel UART with 16Bytes FIFO, Functionally compatible with the 1655, with 1Channel IrDA 2 Channel Master/Slave SPI with 8Bytes FIFO Two Wire Interface Auto ECC NAND Flash Controller: 4-bit/24-bit ECC Support, Auto Booting with ECC Support 75-Port(-D8/16M) or 69-Port(-D8/16MF512) In/Out with open drain mode Analog IPs 1-bit 1MSPS SAR ADC with 4 analog input channels POR (Power On Reset) LDO PLL x 2 Operating frequency Up to 18MHz Power 3.V to 3.6V Operating Temperature -4 / +8 Package 128ETQFP (14 x 14) Advanced Digital Chips, Inc. CONFIDENTIAL 19

Ver 1.6.7 2 BLOCK DIAGRAM & PIN DESCRIPTIONS 2.1 Block Diagram INTC GPIO JTAG Bus Debugger Processor Debugger SRAM for Inst. 2KB AE32C I Cache 2-Way 8KB Fast I/O D Cache 2-Way 8KB SRAM for Data 3KB SRAM Ctrl (ALE) NAND Flash Ctrl SDHC S M S S M M M M M AHB M M M S S M S M M RGB LCD Ctrl SDRAM Ctrl Port Port1 DMA Ctrl AHB to APB Bridge USB Host Full Speed Flash Ctrl 4 bits * D8/16M only 16 bits SDRAM (8MB/16MB) Watchdog Timer USB PHY Flash (512KB) * D8/16MF512 only 12Mbps USB Dev Full Speed 1MHz~ 16MHz MOSC PLL (12M~18MHz) System clock Timer 4-ch. PLL (12M~18MHz) LCD clock SPI 2-ch. PMU APB TWI 1.8V 3.3V POR LDO 1mA BOD UART 5-ch. (1 ch. with IrDA) Sound Mixer PWM PAF ADC Ctrl 1-bit ADC Analog Mux 4 Figure 2-1 Block Diagram 2 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 2.2 Pin Layout 64 63 62 61 6 59 58 57 56 55 54 53 52 51 5 49 48 47 46 45 44 43 42 41 4 39 38 37 36 35 34 33 PIN_P3.4 PIN_P3.3 PIN_P3.2 IO VSS PIN_P3.1 PIN_P3. PIN_P2.7 PIN_P2.6 PIN_P2.5 PIN_P2.4 PIN_P2.3 PIN_P2.2 PIN_P2.1 PIN_P2. IO VSS PIN_P1.7 NC NC NC CORE VDD CORE VSS IO VDD PIN_P1.6 PIN_P1.5 PIN_P1.4 PIN_P1.3 IO VDD PIN_P1.2 PIN_P1. PIN_P1.1 PIN_nTEST PIN_P.7 PIN_ADC_VREF PIN_ADC_VIN[3] PIN_ADC_VIN[2] PIN_ADC_VIN[1] PIN_ADC_VIN[] AGND AVDD33 AVDD33 PIN_USB_DP PIN_USB_DM AGND AVDD18 PIN_PLL_VCTR AGND AVDD18 PIN_PLL1_VCTR AGND AVDD33 NC NC AGND CORE_VDD CORE VSS IO VDD IO VSS PIN_XOUT PIN_XIN PIN_P. PIN_P.1 PIN_P.2 PIN_P.3 IO VSS 1 2 3 4 5 6 7 8 9 1 11 12 13 14 15 16 17 18 19 2 21 22 23 24 25 26 27 28 29 3 31 32 96 95 94 93 92 91 9 89 88 87 86 85 84 83 82 81 8 79 78 77 76 75 74 73 72 71 7 69 68 67 66 65 PIN_P6.7 PIN_P6.6 PIN_P6.5 PIN_P6.4 PIN_P6.3 PIN_P6.2 PIN_P6.1 PIN_P6. PIN_P5.7 PIN_P5.6 PIN_P5.5 PIN_P5.4 PIN_P5.3 PIN_P5.2 PIN_P5.1 PIN_P5. PIN_P4.7 IO VSS IO VDD VPP OTP CORE VSS CORE VDD PIN_P4.6 PIN_P4.5 PIN_P4.4 PIN_P4.3 PIN_P4.2 PIN_P4.1 PIN_P4. PIN_P3.7 PIN_P3.6 PIN_P3.5 IO VSS PIN_P7. PIN_P7.1 PIN_P7.2 SDRAM VDDQ PIN_P7.3 PIN_P7.4 SDRAM VSSQ PIN_P7.5 PIN_P7.6 SDRAM VDDQ PIN_P7.7 PIN_P8. PIN_P8.1 SDRAM VSS CORE VSS CORE VDD NC NC NC SDRAM VDDQ PIN_P8.2 PIN_P8.3 SDRAM VSSQ PIN_P8.4 SDRAM VDDQ IO VSS PIN_P8.5 PIN_P8.6 PIN_P8.7 PIN_RESETn IO VDD 97 98 99 1 11 12 13 14 15 16 17 18 19 11 111 112 113 114 115 116 117 118 119 12 121 122 123 124 125 126 127 128 D16MF512 adchips inc. LOT No. WEEKCODE Figure 2-2 D8/16MF512 Pin Layout Advanced Digital Chips, Inc. CONFIDENTIAL 21

Ver 1.6.7 64 63 62 61 6 59 58 57 56 55 54 53 52 51 5 49 48 47 46 45 44 43 42 41 4 39 38 37 36 35 34 33 PIN_P3.4 PIN_P3.3 PIN_P3.2 IO VSS PIN_P3.1 PIN_P3. PIN_P2.7 PIN_P2.6 PIN_P2.5 PIN_P2.4 PIN_P2.3 PIN_P2.2 PIN_P2.1 PIN_P2. IO VSS PIN_P1.7 PIN_P.6 PIN_P.5 PIN_P.4 CORE VDD CORE VSS IO VDD PIN_P1.6 PIN_P1.5 PIN_P1.4 PIN_P1.3 IO VDD PIN_P1.2 PIN_P1. PIN_P1.1 PIN_nTEST PIN_P.7 PIN_ADC_VREF PIN_ADC_VIN[3] PIN_ADC_VIN[2] PIN_ADC_VIN[1] PIN_ADC_VIN[] AGND AVDD33 AVDD33 PIN_USB_DP PIN_USB_DM AGND AVDD18 PIN_PLL_VCTR AGND AVDD18 PIN_PLL1_VCTR AGND AVDD33 NC NC AGND CORE_VDD CORE VSS IO VDD IO VSS PIN_XOUT PIN_XIN PIN_P. PIN_P.1 PIN_P.2 PIN_P.3 IO VSS 1 2 3 4 5 6 7 8 9 1 11 12 13 14 15 16 17 18 19 2 21 22 23 24 25 26 27 28 29 3 31 32 96 95 94 93 92 91 9 89 88 87 86 85 84 83 82 81 8 79 78 77 76 75 74 73 72 71 7 69 68 67 66 65 PIN_P6.7 PIN_P6.6 PIN_P6.5 PIN_P6.4 PIN_P6.3 PIN_P6.2 PIN_P6.1 PIN_P6. PIN_P5.7 PIN_P5.6 PIN_P5.5 PIN_P5.4 PIN_P5.3 PIN_P5.2 PIN_P5.1 PIN_P5. PIN_P4.7 IO VSS IO VDD VPP OTP CORE VSS CORE VDD PIN_P4.6 PIN_P4.5 PIN_P4.4 PIN_P4.3 PIN_P4.2 PIN_P4.1 PIN_P4. PIN_P3.7 PIN_P3.6 PIN_P3.5 IO VSS PIN_P7. PIN_P7.1 PIN_P7.2 SDRAM VDDQ PIN_P7.3 PIN_P7.4 SDRAM VSSQ PIN_P7.5 PIN_P7.6 SDRAM VDDQ PIN_P7.7 PIN_P8. PIN_P8.1 SDRAM VSS CORE VSS CORE VDD PIN_P9. PIN_P9.1 PIN_P9.2 SDRAM VDDQ PIN_P8.2 PIN_P8.3 SDRAM VSSQ PIN_P8.4 SDRAM VDDQ IO VSS PIN_P8.5 PIN_P8.6 PIN_P8.7 PIN_RESETn IO VDD 97 98 99 1 11 12 13 14 15 16 17 18 19 11 111 112 113 114 115 116 117 118 119 12 121 122 123 124 125 126 127 128 D16M adchips inc. LOT No. WEEKCODE Figure 2-3 D8/16M Pin Layout 22 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 2.3 Pin Definition Table 2-1 Pin Definitions 128-Pin No. Port Name Description. Type 1 PIN_ADC_VREF ADC VREF - Reference Voltage Input Pin In 2 PIN_ADC_VIN[3] ADC VIN 3 - Analog Voltage Input Channel 3 In 3 PIN_ADC_VIN[2] ADC VIN 2 - Analog Voltage Input Channel 2 In 4 PIN_ADC_VIN[1] ADC VIN 1 - Analog Voltage Input Channel 1 In 5 PIN_ADC_VIN[] ADC VIN - Analog Voltage Input Channel In 6 AGND ADC GND - Ground In 7 AVDD33 ADC VDD - Positive Power Supply 3.3V In 8 AVDD33 USB PHY VDD - Power 3.3V In 9 PIN_USB_DP USB DP - Data+ pin I/O 1 PIN_USB_DM USB DM - Data- pin I/O 11 AGND USB GND - Ground In 12 AVDD18 PLL VDD - Analog Power Supply 1.8V In 13 PIN_PLL_VCTR PLL VCTR - VCO Control Voltage, corresponding LPF should be connected here In 14 AGND PLL GND - Ground In 15 AVDD18 PLL1 VDD - Analog Power Supply 1.8V In 16 PIN_PLL1_VCTR PLL1 VCTR - VCO Control Voltage, corresponding LPF should be connected here In 17 AGND PLL1 GND - Ground In 18 AVDD33 VDD - Power Supply 3.3V In 19 NC Not Connected 2 NC Not Connected 21 AGND GND - Ground In 22 CORE VDD Core VDD - Power Supply 1.8V In 23 CORE VSS Core GND - Ground In 24 IO VDD IO VDD - Power Supply 3.3V In 25 IO VSS IO GND - Ground In 26 PIN_XOUT OSC XOUT - Oscillator XOUT Out 27 PIN_XIN OSC XIN - Oscillator XIN In 28 PIN_P. GPIO - General Purpose I/O P. DM_PWML_P - Sound Channel 2 Digital Modulator PWM Left Channel Positive Output SPI_CSn - SPI Channel Chip Select TWI_SCL - TWI Serial Clock Output I/O [1] GPIO - General Purpose I/O P.1 DM_PWML_N - Sound Channel 2 Digital Modulator 29 PIN_P.1 PWM Left Channel Negative Output I/O [1] SPI_MISO - SPI Channel Master In Slave Out TWI_SDA - TWI Serial Data Input Output GPIO - General Purpose I/O.2 DM_PWMR_P - Sound Channel2 Digital Modulator 3 PIN_P.2 PWM Right Channel Positive Output I/O [1] SPI_MOSI - SPI Channel Master Out Slave In SRAM_CS1x - SRAM Bank 1 Chip Select GPIO - General Purpose I/O P.3 DM_PWMR_N - Sound CH2 Digital Modulator PWM 31 PIN_P.3 Right Channel Negative Output I/O [1] SPI_SCK - SPI Channel SCK Clock SRAM_CS2x - SRAM Bank 2 Chip Select 32 IO VSS IO GND - Ground In GPIO - General Purpose I/O P.7 DM1_PWMR_N - Sound CH3 Digital Modulator PWM 33 PIN_P.7 Right Channel Negative Output I/O [1] TAP_SEL - TAP Controller Select (BSC or DBG) UART_RX4 - UART Channel 4 RX (IrDA) Output Drive Current 8mA 8mA 8mA 8mA 8mA Pull-Up / Pull-Down Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) 34 PIN_nTEST ntest - Test Mode Enable Pin In Up GPIO - General Purpose I/O 1.1 35 PIN_P1.1 UART_RX - UART Channel RX I2S_SDI - Sound Channel I2S Data Input TWI_SDA - TWI Serial Data Input Output I/O [1] 8mA 36 PIN_P1. GPIO - General Purpose I/O 1. UART_TX - UART Channel TX I2S_MCLK - Sound I2S Master Clock TWI_SCL - TWI Serial Clock Output I/O [1] 8mA Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Advanced Digital Chips, Inc. CONFIDENTIAL 23

Ver 1.6.7 37 PIN_P1.2 GPIO - General Purpose I/O 1.2 NF_CSx - NAND Flash Chip Select SRAM_CS1x - SRAM Bank 1 Chip Select I/O [1] 38 IO VDD IO / SDRAM VDD - Power Supply 3.3V In GPIO - General Purpose I/O 1.3 39 PIN_P1.3 NF_ALE - NAND Flash Address Latch Enable SDHC_CMD - SDHC Command I/O [1] SRAM_CS3x - SRAM Bank 3 GPIO - General Purpose I/O 1.4 4 PIN_P1.4 NF_CLE - NAND Flash Command Latch Enable SDHC_CLK - SDHC Clock I/O [1] SRAM_BE1x - SRAM Byte Enable [1] GPIO - General Purpose I/O 1.5 41 PIN_P1.5 NF_WEx - NAND Flash Write Enable I2S_SCLK - Sound Channel I2S Bit Clock I/O [1] SRAM_A17 - SRAM Address [17] GPIO - General Purpose I/O 1.6 42 PIN_P1.6 NF_REx - NAND Flash Read Enable I2S_LRCLK - Sound Channel I2S Sample Clock I/O [1] SRAM_A18 - SRAM Address [18] 43 IO VDD IO VDD - Power Supply 3.3V In 44 CORE VSS Core GND - Ground In 45 CORE VDD Core VDD - Power Supply 1.8V In 46 47 48 NC (D16MF512 or D8MF512) PIN_P.4 (D16M or D8M) NC (D16MF512 or D8MF512) PIN_P.5 (D16M or D8M) NC (D16MF512 or D8MF512) PIN_P.6 (D16M or D8M) 49 PIN_P1.7 Not Connected. GPIO - General Purpose I/O.4 DM1_PWML_P - Sound Channel 3 Digital Modulator PWM Left Channel Positive Output Flash_CSx - Flash Chip Select CAP_IN1 - Capture Channel 1 Input Not Connected. GPIO - General Purpose I/O.5 DM1_PWML_N - Sound Channel 3 Digital Modulator PWM Left Channel Negative Output Flash_DQ1 - Flash Data[1] TM_OUT1 - PWM Channel 1 output Not Connected. GPIO - General Purpose I/O.6 DM1_PWMR_P - Sound Channel 3 Digital Modulator PWM Right Channel Positive Output Flash_DQ2 - Flash Data[2] UART_TX4 - UART Channel 4 TX (IrDA) GPIO - General Purpose I/O 1.7 NF_BUSYx - NAND Flash Busyx I2S_SDO - Sound Channel I2S Data Output SRAM_WAITx - SRAM Wait Signal Input 5 IO VSS IO GND In 51 PIN_P2. GPIO - General Purpose I/O 2. NF_D - NAND Flash Data[] UART_TX3 - UART Channel 3 TX SRAM_A8/D8 - SRAM Address[8]/Data[8] 52 PIN_P2.1 53 PIN_P2.2 54 PIN_P2.3 55 PIN_P2.4 GPIO - General Purpose I/O 2.1 NF_D1 - NAND Flash Data[1] UART_RX3 - UART Channel 3 RX SRAM_A9/D9 - SRAM Address[9]/Data[9] GPIO - General Purpose I/O 2.2 NF_D2 - NAND Flash Data[2] UART_TX4 - UART Channel 4 TX (IrDA) SRAM_A1/D1 - SRAM Address[1]/Data[1] GPIO - General Purpose I/O 2.3 NF_D3 - NAND Flash Data[3] UART_RX4 - UART Channel 4 RX (IrDA) SRAM_A11/D11 - SRAM Address[11]/Data[11] GPIO - General Purpose I/O 2.4 NF_D4 - NAND Flash Data[4] SDHC_D - SDHC Data[] SRAM_A12/D12 - SRAM Address[12]/Data[12] I/O [1] I/O [1] I/O [1] I/O [1] I/O [1] I/O [1] I/O [1] I/O [1] I/O [1] 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) 24 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 56 PIN_P2.5 GPIO - General Purpose I/O 2.5 NF_D5 - NAND Flash Data[5] SDHC_D1 - SDHC Data[1] SRAM_A13/D13 - SRAM Address[13]/Data[13] I/O [1] GPIO - General Purpose I/O 2.6 57 PIN_P2.6 NF_D6 - NAND Flash Data[6] SDHC_D2 - SDHC Data[2] I/O [1] SRAM_A14/D14 - SRAM Address[14]/Data[14] GPIO - General Purpose I/O 2.7 58 PIN_P2.7 NF_D7 - NAND Flash Data[7] SDHC_D3 - SDHC Data[3] I/O [1] SRAM_A15/D15 - SRAM Address[15]/Data[15] GPIO - General Purpose I/O 3. 59 PIN_P3. SRAM_A/A8/D - SRAM Address[]/Address[8]/Data[] I/O [1] CAP_IN - Capture Channel Input GPIO - General Purpose I/O 3.1 6 PIN_P3.1 SRAM_A1/A9/D1 - SRAM Address[1]/Address[9]/Data[1] I/O [1] TM_OUT - PWM Channel Output 61 IO VSS IO / SDRAM GND - Ground In GPIO - General Purpose I/O 3.2 62 PIN_P3.2 SRAM_A2/A1/D2 - SRAM Address[2]/Address[1]/Data[2] I/O [1] UART_TX3 - UART Channel 3 TX GPIO - General Purpose I/O 3.3 63 PIN_P3.3 SRAM_A3/A11/D3 - SRAM Address[3]/Address[11]/Data[3] I/O [1] UART_RX3 - UART Channel 3 RX GPIO - General Purpose I/O 3.4 64 PIN_P3.4 SRAM_A4/A12/D4 - SRAM Address[4]/Address[12]/Data[4] I/O [1] CAP_IN2 - Capture Channel 2 Input GPIO - General Purpose I/O 3.5 65 PIN_P3.5 SRAM_A5/A13/D5 - SRAM Address[5]/Address[13]/Data[5] I/O [1] TM_OUT2 - PWM Channel 2 Output GPIO - General Purpose I/O 3.6 66 PIN_P3.6 SRAM_A6/A14/D6 - SRAM Address[6]/Address[14]/Data[6] I/O [1] OHCI_OVC - USB Host Over Current GPIO - General Purpose I/O 3.7 67 PIN_P3.7 SRAM_A7/A15/D7 - SRAM Address[7]/Address[15]/Data[7] I/O [1] OHCI_PPW - USB Host Port Power GPIO - General Purpose I/O 4. 68 PIN_P4. SRAM_A16 - SRAM Address[16] I/O [1] EIRQ - External Interrupt Request GPIO - General Purpose I/O 4.1 69 PIN_P4.1 SRAM_ALE - SRAM Address Latch Enable I/O [1] EIRQ1 - External Interrupt Request 1 GPIO - General Purpose I/O 4.2 7 PIN_P4.2 SRAM_ALE1 - SRAM Address Latch Enable I/O [1] UART_TX1 - UART Channel 1 TX GPIO - General Purpose I/O 4.3 71 PIN_P4.3 SRAM_REx - SRAM Read Enable I/O [1] UART_RX1 - UART Channel 1 RX GPIO - General Purpose I/O 4.4 72 PIN_P4.4 SRAM_WEx - SRAM Write Enable TWI_SCL - TWI Serial Clock I/O [1] UART_TX2 - UART Channel 2 TX GPIO - General Purpose I/O 4.5 73 PIN_P4.5 SRAM_CSx - SRAM Bank Chip Select TWI_SDA - TWI Serial Data I/O [1] UART_RX2 - UART Channel 2 RX GPIO - General Purpose I/O 4.6 74 PIN_P4.6 I2S_MCLK - Sound I2S Master Clock SPI_SCK1 - SPI Channel 1 SCK I/O [1] CAP_IN3 - Capture Channel 3 Input 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) 75 CORE VDD Core VDD - Power Supply 1.8V In 76 CORE VSS Core GND - Ground In 77 VPP OTP OTP VPP - Supply Voltage for Program 6.7V In 78 IO VDD IO VDD - Power Supply 3.3V In 79 IO VSS IO GND - Ground In 8 PIN_P4.7 GPIO - General Purpose I/O 4.7 I/O [1] 8mA Controllable Advanced Digital Chips, Inc. CONFIDENTIAL 25

Ver 1.6.7 I2S_SDI - Sound Channel I2S Data Input SPI_CS1x - SPI Channel 1 Chip Select TM_OUT3 - PWM Channel 3 Output GPIO - General Purpose I/O 5. 81 PIN_P5. I2S_SCLK - Sound Channel I2S Bit Clock SPI_MISO1 - SPI Channel 1 Master In Slave Out SRAM_A - SRAM Address[] GPIO - General Purpose I/O 5.1 82 PIN_P5.1 I2S_LRCLK - Sound Channel Sample Clock SPI_MOSI1 - SPI Channel 1 Master Out Slave In SRAM_A1 - SRAM Address[1] GPIO - General Purpose I/O 5.2 83 PIN_P5.2 I2S_SDO - Sound Channel I2S Data Output UART_TX - UART Channel TX SRAM_A2 - SRAM Address[2] GPIO - General Purpose I/O 5.3 84 PIN_P5.3 CRTC_CLK_IN - CRTC Clock Input UART_RX - UART Channel RX SRAM_A3 - SRAM Address[3] GPIO - General Purpose I/O 5.4 85 PIN_P5.4 VSYNC - CRTC Vertical Sync. EIRQ - External Interrupt Request SRAM_A4 - SRAM Address[3] GPIO - General Purpose I/O 5.5 86 PIN_P5.5 HSYNC - CRTC Horizontal Sync. EIRQ1 - External Interrupt Request 1 SRAM_A5 - SRAM Address[5] GPIO - General Purpose I/O 5.6 87 PIN_P5.6 DISP_EN - CRTC Display Enable UART_TX1 - UART Channel 1 TX SRAM_A6 - SRAM Address[6] GPIO - General Purpose I/O 5.7 88 PIN_P5.7 CRTC_CLK_OUT - CRTC Clock Output UART_RX1 - UART Channel 1 RX SRAM_A7 - SRAM Address[7] GPIO - General Purpose I/O 6. 89 PIN_P6. R - CRTC Red Output ntrst - JTAG ntrst GPIO - General Purpose I/O 6.1 9 PIN_P6.1 R1 - CRTC Red 1 Output TCK - JTAG TCK GPIO - General Purpose I/O 6.2 91 PIN_P6.2 R2 - CRTC Red 2 Output TDI - JTAG TDI GPIO - General Purpose I/O 6.3 92 PIN_P6.3 R3 - CRTC Red 3 Output SDHC_CMD - SDHC Command I2S1_SCLK - Sound Channel 1 I2S Bit Clock GPIO - General Purpose I/O 6.4 93 PIN_P6.4 R4 - CRTC Red 4 Output SDHC_D - SDHC Data[] I2S1_LRCLK - Sound Channel 1 I2S Sample Clock GPIO - General Purpose I/O 6.5 94 PIN_P6.5 R5 - CRTC Red 5 Output SDHC_D1 - SDHC Data[1] I2S1_SDO - Sound Channel 1 I2S Data Output GPIO - General Purpose I/O 6.6 95 PIN_P6.6 R6 - CRTC Red 6 Output SDHC_D2 - SDHC Data[2] UART_TX2 - UART Channel 2 TX GPIO - General Purpose I/O 6.7 96 PIN_P6.7 R7 - CRTC Red 7 Output SDHC_D3 - SDHC Data[3] UART_RX2 - UART Channel 2 RX 97 IO VSS IO / SDRAM VSS - Ground I/O GPIO - General Purpose I/O 7. 98 PIN_P7. G - CRTC Green Output TMS - JTAG TMS SRAM_CS1x - SRAM Bank 1 Chip Select GPIO - General Purpose I/O 7.1 99 PIN_P7.1 G1 - CRTC Green 1 Output TDO - JTAG TDO SRAM_CS2x - SRAM Bank 2 Chip Select I/O [1] I/O [1] I/O [1] I/O [1] I/O [1] I/O [1] I/O [1] I/O [1] I/O [1] I/O [1] I/O [1] I/O [1] I/O [1] I/O [1] I/O [1] I/O [1] I/O [1] I/O [1] 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) 26 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 1 PIN_P7.2 GPIO - General Purpose I/O 7.2 G2 - CRTC Green 2 Output SDHC_CLK - SDHC Clock SRAM_A1 - SRAM Address[1] I/O [1] 11 SDRAM VDDQ SDRAM VDD - Power Supply 3.3V In GPIO - General Purpose I/O 7.3 12 PIN_P7.3 G3 - CRTC Green 3 Output CFG[] - Power Configuration[] I/O [1] SRAM_A11 - SRAM Address[11] GPIO - General Purpose I/O 7.4 13 PIN_P7.4 G4 - CRTC Green 4 Output CFG[1] - Power Configuration[1] I/O [1] SRAM_A12 - SRAM Address[12] 14 SDRAM VSSQ SDRAM VSS - Ground In GPIO - General Purpose I/O 7.5 15 PIN_P7.5 G5 - CRTC Green 5 Output CFG[2] - Power Configuration[2] I/O [1] SRAM_A13 - SRAM Address[13] GPIO - General Purpose I/O 7.6 16 PIN_P7.6 G6 - CRTC Green 6 Output CFG[3] - Power Configuration[3] I/O [1] SRAM_A14 - SRAM Address[14] 17 SDRAM VDDQ SDRAM VDD - Power Supply 3.3.V In GPIO - General Purpose I/O 7.7 18 PIN_P7.7 G7 - CRTC Green 7 Output CFG[4] - Power Configuration[4] (Not used, Pull-up Only) I/O [1] SRAM_A15 - SRAM Address[15] GPIO - General Purpose I/O 8. B - CRTC Blue Output 19 PIN_P8. DM_PWML_P - Sound Channel 2 Digital Modulator I/O [1] PWM Left Channel Positive Output SRAM_A8 - SRAM Address[8] GPIO - General Purpose I/O 8.1 B1 - CRTC Blue 1 Output 11 PIN_P8.1 DM_PWML_N - Sound Channel 2 Digital Modulator I/O [1] PWM Left Channel Negative Output SRAM_A9 - SRAM Address[9] 111 SDRAM VSS SDRAM VSS - Ground In 112 CORE VSS Core GND - Ground In 113 CORE VDD Core VDD - Power Supply 1.8V In NC (D16MF512 or Not Connected. D8MF512) 114 115 116 PIN_P9. (D16M or D8M) NC (D16MF512 or D8MF512) PIN_P9.1 (D16M or D8M) NC (D16MF512 or D8MF512) PIN_P9.2 (D16M or D8M) GPIO - General Purpose I/O 9. I2S1_SCLK - Sound Channel 1 I2S Bit Clock Flash_DQ - Flash Data[] CAP_IN - Capture Channel Input Not Connected. GPIO - General Purpose I/O 9.1 I2S1_LRCLK - Sound Channel 1 I2S Sample Clock Flash_CLK - Flash Clock TM_OUT - PWM Channel Output Not Connected. GPIO - General Purpose I/O 9.2 I2S1_SDO - Sound Channel 1 I2S Data Output Flash_DQ3 - Flash Data[3] SRAM_CS3x - SRAM Bank 3 Chips Select 117 SDRAM VDDQ SDRAM VDD - Power Supply 3.3V In 118 PIN_P8.2 GPIO - General Purpose I/O 8.2 B2 - CRTC Blue 2 Output DM_PWMR_P - Sound Channel 2 Digital Modulator PWM Right Channel Positive Output CAP_IN1 - Capture Channel 1 Input 119 PIN_P8.3 GPIO - General Purpose I/O 8.3 B3 - CRTC Blue 3 Output DM_PWMR_N - Sound Channel 2 Digital Modulator PWM Right Channel Negative Output TM_OUT1 - PWM Channel 1 Output I/O [1] I/O [1] I/O [1] I/O [1] I/O [1] 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA 8mA Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Advanced Digital Chips, Inc. CONFIDENTIAL 27

Ver 1.6.7 12 SDRAM VSSQ SDRAM VSS - Ground In 121 PIN_P8.4 GPIO - General Purpose I/O 8.4 B4 - CRTC Blue 4 Output DM1_PWML_P - Sound Channel 3 Digital Modulator PWM Left Channel Positive Output CAP_IN2 - Capture Channel 2 Input I/O [1] 8mA 122 SDRAM VDDQ SDRAM VDD - Power Supply 3.3V In 123 IO VSS IO / SDRAM VSS - Ground In GPIO - General Purpose I/O 8.5 B5 - CRTC Blue 5 Output 124 PIN_P8.5 DM1_PWML_N - Sound Channel 3 Digital Modulator I/O [1] 8mA PWM Left Channel Negative Output TM_OUT2 - PWM Channel 2 Output GPIO - General Purpose I/O 8.6 B6 - CRTC Blue 6 Output 125 PIN_P8.6 DM1_PWMR_P - Sound Channel 3 Digital Modulator I/O [1] 8mA PWM Right Channel Positive Output CAP_IN3 - Capture Channel 3 Input GPIO - General Purpose I/O 8.7 B7 - CRTC Blue 7 Output 126 PIN_P8.7 DM1_PWMR_N - Sound Channel 3 Digital Modulator I/O [1] 8mA PWM Right Channel Negative Output TM_OUT3 - PWM Channel 3 Output 127 PIN_nRESET Reset - Reset pin In Up 128 IO VDD IO / SDRAM VDD - Power Supply 3.3V In Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) Controllable (Up, Down or Disable) [1] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors. 28 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 2.4 Pin Description AVDD33, IO VDD, SDRAM VDD, SDRAM VDDQ : 3.3V Supply voltage AVDD18, Core VDD : 1.8V Supply voltage AGND, IO VSS, Core VSS, SDRAM VSSQ : Ground VPP OTP : 6.5V Supply voltage for OTP Program PIN_nTEST : Chip Test pin (Low active) Chip test 를위한핀이다. 이핀이 이면 PinMux 설정과관계없이 PIN_P6.~2 와 PIN_P7.~1 은 JTAG Interface 핀으로, PIN_P.7 은 TAP_SEL 핀으로고정된다. TAP_SEL : TAP Controller Select 칩내부에들어있는 JTAG Debugger TAP Controller 나 Boundary Scan TAP Controller 를선택한다. 이핀이 1 이면, JTAG Debugger TAP Controller 를, 이면 Boundary Scan TAP Controller 를선택하게된다. CFG[4:] : Booting Mode Select (3.4 Boot Mode 참고 ) Flash Booting, NOR Flash/ROM Booting, NAND Flash Booting 등을선택할수있다. PIN_ADC_VREF : VIN 과비교할 reference voltage input pin PIN_ADC_VIN[3:] : 디지털값으로변환할아날로그전압레벨입력채널 USB Pins: USB Device 와 Host 가공유. (4.3.7 USB PHY Control Register 참고 ) PIN_USB_DP : USB Data+ I/O PIN_USB_DM : USB Data- I/O GPIO : General Purpose I/O (7 GPIO 참고 ) EIRQ, EIRQ1 : External Interrupt Request Input Pins (8 Interrupt Controller 참고 ) 외부에서인터럽트를요청해야할경우사용. Flash (1 Flash Memory Controller 참고 ) Flash_CSx : Flash Chip Select Flash_CLK : Flash Clock Flash_D[3:] : Flash Data I/O. Flash 에 Command, Address 를 write 하는데사용되며, Data 를 Write/Read 하는용도로사용. External SRAM : 4 개의 Bank 지원. (12 External SRAM Controller 참고 ) Bank 는부팅용이며, 8-bit data width only. SRAM_CSx : 부팅용으로사용가능한 ROM 이나 NOR Flash 의 Chip Select SRAM_CS1x, SRAM_CS2x, SRAM_CS3x : SRAM Chips Select SRAM_A[7:]/A[15:8]/D[7:] : SRAM Controller 의설정이 8-bit bus width 이고, ALE Enable 인경우, SRAM_ALE[1] 이 1 일때 address[15:8], SRAM_ALE[] 이 1 일때 address[7:] 이출력되며, 그외구간에서 data[7:] 를출력한다. (Figure 12-1 참고 ) 동일한설정에서 bus width 만 16-bit 인경우, address[15:8] 은출력구간은없어진다. (Figure 12-3 참고 ) SRAM_A[15:8]/D[15:8] : SRAM Controller 의설정이 16-bit bus width 이고, ALE Enable 인경우, SRAM_ALE[1] 이 1 일때 address[15:8], 그외구간에서 data[15:8] 를출력한다. (Figure Advanced Digital Chips, Inc. CONFIDENTIAL 29

Ver 1.6.7 12-3 참고 ) SRAM_A[18:16] : SRAM Address[18:16] 을출력 SRAM_ALE[1:] : SRAM Address Latch Enable. ALE Enable 인경우, SRAM Data pin 으로 address 를출력하게된다. ALE[1] 이 1 일때 Address[15:8] 이, ALE[] 이 1 일때 Address[7:] 이출력된다. SRAM_BE1x : SRAM Byte Enable[1]. 16-bit width 일경우, 상위 8-bit 데이터를접근하기위한 Enable 신호. SRAM_WEx : SRAM Write Enable. SRAM_REx : SRAM Read Enable. SRAM_WAITx : SRAM Wait 신호. Default disable. SRAM 에서지원할경우사용. NAND Flash (13 NAND Flash Controller 참고 ) NF_CSx : NAND Flash Chips Select. NAND Flash 를활성화할때사용 NF_ALE : NAND Flash Address Latch Enable. NAND Flash 에 address 를전송할때사용 NF_CLE : NAND Flash Command Latch Enable. NAND Flash 에 command 를전송할때사용 NF_WEx : NAND Flash Write Enable. NAND Flash 에 data 를저장할때사용 NF_REx : NAND Flash Read Enable. NAND Flash 에서 data 를읽을때사용 NF_BUSYx : NAND Flash Busy signal input pin. NAND Flash 가 Busy 상태일때. NF_D[7:] : NAND Flash 8-bit Data I/O. SDHC (14 SD Host Controller 참고 ) SDHC_CLK : SDHC Clock SDHC_CMD : SDHC Command SDHC_D[3:] : SDHC Data I/O CRTC : RGB 888 출력. 124x768 지원 (16 CRTC Controller 참고 ) CRTC_CLK_IN : CRTC 에서사용할 Clock Input VSYNC : 수직동기신호 HSYNC : 수평동기신호 DISP_EN : Display Enable CRTC_CLK_OUT : CRTC Clock Output R[7:] : Red Output 8-bit G[7:] : Green Output 8-bit B[7:] : Blue Output 8-bit PWM/Capture : 4 channels. (17 Timer 참고 ) TM_OUT, TM_OUT1, TM_OUT2, TM_OUT3 : PWM Output. CAP_IN, CAP_IN1, CAP_IN2, CAP_IN3 : Capture Input. 외부신호의주기나펄스폭을측정하기위한입력핀 SPI : 2 channels. (18 SPI 참고 ) SPI_CSn, SPI1_CSn : SPI Chip select signal SPI_SCK, SPI1_SCK : SPI Clock pin SPI_MISO, SPI1_MISO : SPI 가 Master 일때 Data input, Slave 일때 Data output 으로사용 SPI_MOSI, SPI1_MOSI : SPI 가 Master 일때 Data output, Slave 일때 Data input 으로사용 TWI (19 TWI 참고 ) TWI_SCL : TWI Serial Clock TWI_SDA : TWI Serial Data UART : 5 channels. (2 UART 참고 ) Channel ~3 은 UART only. Channel 4 는 UART 에 IrDA 를지원. 3 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 UART_RX, UART_RX1, UART_RX2, UART_RX3 : UART RX UART_TX, UART_TX1, UART_TX2, UART_TX3 : UART TX UART_RX4 : UART RX with IrDA supported UART_TX4 : UART TX with IrDA supported Sound Mixer : I2S 2 channels, Digital Modulator 2 channels. (22 Sound Mixer 참고 ) I2S_MCLK : I2S Master Clock I2S_SDI : I2S Data input pin. 외부로부터데이터를입력받을때사용. Channel only. I2S_SCLK, I2S1_SCLK : I2S Bit Clock I2S_LRCLK, I2S1_LRCLK : I2S Sample Clock. Left data 와 Right data 를구분하는용도. I2S_SDO, I2S1_SDO : I2S Data output pin DM_PWML_P, DM_PWML_N, DM_PWMR_P, DM_PWMR_N, DM1_PWML_P, DM1_PWML_N, DM1_PWMR_P, DM1_PWMR_N : Sound Mixer Digital Modulator PWM 출력. Sound Mixer 의 Channel 2, 3 에할당. 각채널마다 Left 와 Right 출력이하나씩존재하며, 각각 Positive, Negative 출력으로다시나뉘어져한채널에총 4 개의신호로출력된다. Advanced Digital Chips, Inc. CONFIDENTIAL 31

Ver 1.6.7 3 MEMORY ARCHITECTURE AND BOOTING MODE 3.1 Memory Map 메모리영역은아래의표와같이할당되어있다. xbfff:ffff Figure 3-1 Memory Map 2nd Bus xa: x9fff:ffff 1st Bus x8: Reserved x51f:ffff External SRAM CS1~3 x58: x5: External SRAM CS Reserved X3FFF:FFFF Flash X3: x2fff:ffff SDRAM 8MB/16MB x2: x18:77ff x18: x1:7ff x1: xfff:ffff x: Reserved Internal SRAM 3KB for Data Reserved Internal SRAM 2KB for Instruction Boot Area (NAND Boot: Internal SRAM 2KB Flash Boot: Flash NOR Boot: E.SRAM CS) 32 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 3.2 Embedded Memories 2KB Internal SRAM for Instruction 3KB Internal SRAM for Data 3.2.1 Internal SRAM for Instruction 는 Instruction 을위한 2KB SRAM 메모리가내장되어있다. 명령어또는데이터를저장하는용도로사용할수있으며주로명령어를저장하게된다. 명령어를읽는경우 1cycle 접근이가능하며데이터를읽는경우는 3 cycle 이소요된다. 3.2.2 Internal SRAM for Data 는 Data 를위한 3KB SRAM 메모리가내장되어있다. 주로데이터를저장하는데사용되며, 데이터를읽는경우 1cycle 접근이가능하다. 3.2.3 Internal SRAM Registers Internal SRAM 전체를관장하는 1 개의 Global Control Register 를갖는다. 또한 Internal SRAM 은내부에여러개의 Bank 로구성될수있으므로 Global Register 의 Configuration 에의해결정되는 Bank 개수만큼 Local Register Set 을갖는다. Local Register Set 는다음과같은 3 개의 32bit Register 로구성된다. - Local Internal SRAM Control Register - Local Internal SRAM Start Address - Local Internal SRAM End Address Internal SRAM Global Control Register Address : x7 - Global Control Register Bit R/W Description Default 31 : 28 R Exception Status 4 b1 : DATA Access Violation h 4 b1 : Instruction Access Violation 27 : 24 R Reserved h 23 : 2 R ibank Size: isram에서각 bank의 physical Memory 크기 4 h : 1 KB 4 h1 : 2 KB 4 h2 : 4 KB 4 h3 : 8 KB 4 h4 : 16 KB 4 h5 : 32 KB 4 h6 : 64 KB 4 h7 : 128 KB Advanced Digital Chips, Inc. CONFIDENTIAL 33

Ver 1.6.7 19 : 16 R/W isram Configuration 4 h : 사용자에게 1개의메모리덩어리로보임 4 h1 : Reserved 4 h2 : 사용자에게 4개의메모리덩어리로보임 (4개를넘는경우는현재구현되어있지않음 ) 15 : 12 R isram Enable 4 b1 : SRAM Enable 4 b : SRAM Disable 11 : 8 R dbank Size: dsram에서각 bank의 physical Memory 크기 4 h : 1 KB 4 h1 : 2 KB 4 h2 : 4 KB 4 h3 : 8 KB 4 h4 : 16 KB 4 h5 : 32 KB 4 h6 : 64 KB 4 h7 : 128 KB 7 : 4 R/W dsram Configuration 4 h : 사용자에게 1개의메모리덩어리로보임 4 h1 : Reserved 4 h2 : 사용자에게 4개의메모리덩어리로보임 (4개를넘는경우는현재구현되어있지않음 ) 3 : R dsram Enable 4 b1 : SRAM Enable 4 b : SRAM Disable h h h h Internal SRAM Local Control Register Address : x71, x711, x721, x731 - Local isram Control Register Address : x74, x714, x724, x734 - Local dsram Control Register Bit R/W Description Default 31 : 12 R Reserved h 11 : 8 R External Access: BUS 접근권한 4 h : External Access Not Support 4 h1 : External Access Support 7 : 4 R/W Priviedge Mode: 사용자권한 4 h : Supervisor only Access h 4 h1 : Supervisor/User Access 34 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 3 : R Enable 4 b1 : Local SRAM Enable h 4 b : Local SRAM Disable Internal SRAM Local Start Address Register Address : x72, x712, x722, x732 - Local isram Start Register Address : x75, x715, x725, x735 - Local dsram Start Register Bit R/W Description Default 31 : R/W SRAM Start Address h Internal SRAM Local End Address Register ADDRESS : x73, x713, x723, x733 - Local isram End Register ADDRESS : x76, x716, x726, x736 - Local dsram End Register Bit R/W Description Default 31 : R/W SRAM End Address h 3.2.4 Internal SRAM Register Setting Internal SRAM 레지스터의설정은 GAP 를이용하기때문에 co-processor 레지스터접근명령어인 MVTC 와 MVFC 를사용하게된다. 예제. //#################################################### //## Internal SRAM Global Register Setting //#################################################### asm( ldi x7, %r ); asm( mvtc x, %r3 ); asm( ldi x2121, %r ); //#ON //#Num of Memory Bank: 4 asm( mvtc x, %r4 ); 3.3 Memory Mapped I/O Register 영역은 8_h 부터존재하며각기능 Block 당 1Kbyte 씩할당되어있다. Memory mapped I/O 의형태로자세한내용은아래와같다. Table 3-1 Memory Mapped I/O Register Offset Address Block BUS Remark x8_ Flash Controller x8_4 SDRAM Controller x8_8 External SRAM Controller 1 st x8_c Reserved AHB x8_1 Reserved x8_14 DMA Controller x82_ Watchdog Timer x82_4 Timer 4 Channels x82_8 UART (5th ch. IrDA) 1 st 5 Channels x82_c APB Reserved ~x82_17ff x82_18 TWI Advanced Digital Chips, Inc. CONFIDENTIAL 35

Ver 1.6.7 x82_1c ~x82_23ff Reserved x82_24 CRTC x82_28 ~x82_33ff Reserved x82_34 Port Alternate Functions x82_38 OTP Controller x82_3c PMU x83_ ~x83_ffff Reserved Offset Address Block BUS Remark xa_ USB Host xa_4 Reserved ~xa_bff 2 st xa_c NAND Flash Controller AHB xa_1 SDHC xa_14 Reserved xa_18 USB Device xa2_1 SPI xa2_14 SPI 1 xa2_18 Reserved xa2_1c Sound Mixer xa2_2 2 st Reserved ~xa2_37ff APB xa2_38 ADC Controller 1-bit ADC xa2_3c Reserved xa3_ ~xa3_ffff Reserved 36 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 3.4 Boot Mode 3.4.1 Debugger Boot Mode CFG[]= 인경우에 Debugger mode 로부팅된다. 이모드에서는 CPU 는정지상태에놓여있으며사용자가 JTAG Debugger 를통하여 CPU 의프로그램수행동작을제어하게된다. 3.4.2 Normal Boot Mode CFG[]=1 인경우에 Normal mode 로부팅된다. 이모드에서 CPU 는일반적인프로그램수행동작을진행한다. 3.4.3 Flash Boot Mode CFG[3:1]=1 인경우에 Flash 로부팅된다. 이모드에서는 CPU 가 Flash 에저장된프로그램을수행하게된다. 3.4.4 NOR Flash Boot Mode CFG[3:1]= 인경우에 8-bit NOR Flash 로부팅된다. 이모드에서는 CPU 가 NOR Flash 에저장된프로그램을수행하게된다. 3.4.5 NAND Flash Auto Boot Mode CFG[3:1] 이 이나 1 이아닌경우에 NAND Flash 로부팅된다. 이모드에서는최초 NAND Flash 의부트코드가내부 2KB 크기의 Internal SRAM 에복사가되며, 복사가끝나면 CPU 가복사된프로그램을수행하게된다. CFG[3:1] NAND Boot Mode NAND Flash Type 1 Small type 3-Cycle NAND Flash Small type Address 3 cycles 11 Small type 4-Cycle NAND Flash Small type Address 4 cycles 11 Large type 4-Cycle NAND Flash Large type Address 4 cycles 111 Large type 5-Cycle NAND Flash Large type Address 5 cycles 1 MLC 4-Bit ECC NAND Flash MLC type 4-bit ECC 11 MLC 24-Bit ECC NAND Flash MLC type 24-bit ECC Advanced Digital Chips, Inc. CONFIDENTIAL 37

Ver 1.6.7 4 SYSTEM RESET AND CLOCK 4.1 Reset Reset controller 는 External Reset, JTAG Reset 그리고 Watchdog Reset 으로구성되어있다. 아래그림에전체 Reset 들이표시되어있다. config_done int_resetx ext_clk ext_resetx por_resetx wdt_resetx dbg_resetx all_resetx reset counter poc_resetx boot_resetx config_done sys_resetx Figure 4-1 Reset 4.1.1 System Reset System Reset은다음과같은사항에서발생한다. 1. External Reset 2. JTAG Reset 3. Watchdog Reset 4. POR Reset 4.1.2 Power On Start Time VDD33 에 3.3V 전원이인가되고, 내부 LDO 출력을통해 VDD18 에 1.8V 가안정적으로인가되면, POR Reset 이 release 된다. 이때, External Reset 이 release 되면, External Clock 으로동작하는 Startup 회로가동작하게된다. 이 Startup 회로는 Xin 이안정화되기전의오동작을방지하며, 내부 logic 에동시에 system reset 을 release 시켜준다. System reset 은 POR Reset 과 External Reset 이 release 되고 Xin clock 기준 124-cycle 이지난후 release 된다. 38 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 3.3V VDDIO (VDD33) CoreVDD (VDD18).9V 1.62V 1.8V 75ms 3ms POR Resetn External Resetn External Clock (Xin) Internal System Resetx Figure 4-2 Power On Start Time Diagram Startup counter 124 cycles of Xin (9us at 12Mhz Xin) Advanced Digital Chips, Inc. CONFIDENTIAL 39

Ver 1.6.7 4.2 Clocks XIN 으로공급되는 External Clock 은 1~16Mhz 을사용한다. sysclk_sel ext_clk PLL 1/1~ 1/16 HCLK 1/2 PCLK dclk PLL1 dclk_sel 1/1~ 1/16 DCLK 1/1~ 1/16 ADCCLK usb_clk_src usb_clk_sel mclk_sel 1/2 1'b USB48M 1'b apb_clk cap_in 1/1~ 1/16 MCLK 1/4 USB12M dmclk_sel 1'b pll_clk cap_in 1/1~ 1/8 DMCLK 은 7 개의클럭소스를입력으로받는다. 1. HCLK 2. PCLK 3. DCLK (CRTC) 4. USBCLK 5. TCK (JTAG) 6. MCLK (I2S) 7. DMCLK (Digital Modulator) Figure 4-3 Clocks HCLK 과 PCLK 은각각 AHB 영역과 APB 영역에클럭을공급한다. 두클럭은동일한위상이며 2:1 의주파수비의관계를갖고있다. HCLK 의최대주파수는 18Mhz 이며 PCLK 의최대주파수는 54Mhz 이다. 4 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 DCLK 는 CRTC 에사용되는클럭을공급한다. USBCLK 는 USB Host/Device 에사용되는클럭을공급한다. TCK 는 JTAG 모듈에공급되며 HCLK 또는 PCLK 와는비동기된클럭이다. 그러나주파수는 HCLK 주파수의 1/4 이하로동작해야 JTAG 모듈이정상적으로동작한다. MCLK 는 I2S 에공급되며, DMCLK 는 Digital Modulator 에공급되어, sound 를출력하는데사용된다. 4.3 Power Management Unit Registers 4.3.1 PMU Write Enable Register (PMUWREN) Address : x82_3c 31:14 R Reserved - 14 R Reserved 13 R/W USB PHY Control Register Write Enable 12 R/W PCLK Control Register Write Enable 11 R/W HCLK Control Register Write Enable 1 R/W Sound Clock Control Register Write Enable 9 R/W PLL Control Register Write Enable 8 R/W Clock Control Register Write Enable 7:3 R Reserved - 2 R/W Core Clock Off by Halt 3 Enable 1: R Reserved - * Core Clock 을 Halt 3 명령으로 off 하기위해서는 bit[2] 를 1 로 set 해야한다. * Halt 명령으로 sleep mode 가된 core 를깨우려면, 인터럽트를발생시켜야한다. Advanced Digital Chips, Inc. CONFIDENTIAL 41

Ver 1.6.7 4.3.2 Clock Control Register (CLKCON) Address : x82_3c2 31:16 R Reserved - 19:16 R/W AHB Clock Select : System Clock 1: System Clock / 2 1: System Clock / 3 11: System Clock / 4 111: System Clock / 15 1111: System Clock / 16 15:12 R/W CRTC Clock Select : DotSrcClk 1: DotSrcClk / 2 1: DotSrcClk / 3 11: DotSrcClk / 4 111: DotSrcClk / 15 1111: DotSrcClk / 16 11:1 R Reserved - 9 R/W CRTC Source Clock Select (DotSrcClk) : External CRTC Clock 1: PLL1 Clock 8 R/W CRTC Clock Enable bit : CRTC Clock Disable 1: CRTC Clock Enable 1 7:4 R Reserved - 3 R/W USB Clock Enable bit : USB Clock Disable 1: USB Clock Enable 2 R/W USB Clock Select : USB Source Clock / 2 1: USB Source Clock 1 R/W USB Source Clock Select : AHB Clock 1: CRTC Clock R/W System Clock Select bit : External Clock 1: PLL Clock 42 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 4.3.3 PLL Control Register (PLLCON) Address : x82_3c24 31:15 R Reserved - 14:12 R/W PLL1 OS 11 R Reserved - 1:8 R/W PLL1 IS 7 R Reserved - 6:4 R/W PLL OS 3 R Reserved - 2: R/W PLL IS * FOUT = (XIN*M)/(N*O) [XIN/N 는 1M~3M 사이, XIN*M/N 은 48M~18M 사이의값을만족 ] Advanced Digital Chips, Inc. CONFIDENTIAL 43

Ver 1.6.7 4.3.4 Sound Control Register (SNDCLKCON) Address : x82_3c28 31:14 R Reserved - 13:12 R/W Digital Modulator Source Clock (DMCLKSRC) 1 : Clock disable 1: External Clock 1: PLL Clock 11: Capture Input[] 11:1 R Reserved - 9:8 R/W Digital Modulator Clock Divide Select : DMCLKSRC 1: DMCLKSRC / 2 1: DMCLKSRC / 4 11: DMCLKSRC / 8 7:6 R Reserved - 5:4 R/W I2S Source Clock Select : Clock disable 1: External Clock 1: APB Clock 11: Capture Input[] 1 3: R/W I2S Clock Divide Value : I2S Source Clock 1: I2S Source Clock / 2 1: I2S Source Clock / 3 111: I2S Source Clock / 15 1111: I2S Source Clock / 16 4.3.5 AHB Clock Control Register (HCLKCON) Address : x82_3c2c 31:13 R Reserved - 12 R/W USB Host AHB Clock Enable 1 11 R/W USB Device AHB Clock Enable 1 1 R/W CRTC AHB Master Clock Enable 1 9 R/W SDHC Clock Enable 1 8 R/W NAND Flash Controller Clock Enable 1 7 R/W External SRAM Controller Clock Enable 1 6 R/W Flash Controller Clock Enable 1 5 R/W DMA Clock Enable 1 4 R/W GPIO Clock Enable 1 3 R/W Interrupt Controller Clock Enable 1 2 R/W SDRAM Clock Enable 1 1 R/W SDRAM Controller Clock Enable 1 R/W AHB Bus Clock Enable 1 44 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 4.3.6 APB Clock Control Register (PCLKCON) Address : x82_3c3 31:13 R Reserved - 12 R/W Pin MUX Clock Enable 1 11 R/W ADC APB Clock Enable 1 1 R/W QEI Clock Enable 1 9 R/W Dedicated PWM Clock Enable 1 8 R/W Sound Mixer APB Clock Enable 1 7 R/W TWI Clock Enable 1 6 R/W SPI1 Clock Enable 1 5 R/W SPI Clock Enable 1 4 R/W UART Clock Enable 1 3 R/W Timer Clock Enable 1 2 R/W Watch Dog Timer Clock Enable8 1 1 R/W CRTC APB Slave Clock Enable 1 R/W APB Bus Clock Enable 1 4.3.7 USB PHY Control Register (USBPHYCON) Address : x82_3c34 31:9 R Reserved - 8 R/W USB Function Select bit : USB Device 1: USB Host 7 R Reserved - 6 R/W D- Pull-down Enable bit : Pull-down Disable 1: Pull-down Enable 5 R/W D+ Pull-down Enable bit : Pull-down Disable 1: Pull-down Enable 4 R/W Receive Enable bit : USB PHY가외부신호를받아들이지않는다. 1: USB PHY가외부신호를받아들인다. 1 3 R/W D- Weak Pull-up Enable bit : Pull-up Disable 1: Pull-up Enable 2 R/W D- Pull-up Enable bit : Pull-up Disable 1: Pull-up Enable 1 R/W D+ Weak Pull-up Enable bit : Pull-up Disable 1: Pull-up Enable R/W D+ Pull-up Enable bit : Pull-up Disable 1: Pull-up Enable Advanced Digital Chips, Inc. CONFIDENTIAL 45

Ver 1.6.7 5 COPROCESSOR 의 Coprocessor 는메모리관리를위한 Memory Management Unit(MMU) 과 I- Cache, D-Cache 기능블록을포함하며, 이들기능블록들과기타부가기능블록에대한제어를담당한다. 5.1 Features - Memory Management Unit - Real Memory mode - 2 Way Set Associative Harvard Cache - 8KBytes I-Cache - 8KBytes D-Cache - Write Through - 16 Bytes / Line - LRU Replacement - Cache Invalidation by Software - 4 Words Deep Write Buffer (FIFO) Real Memory mode 는 CPU 가 4GB 크기의선형메모리영역을위해예약된일부메모리영역만접근할수있으며, CPU 의주소는실제메모리주소와일치한다. Table 5-1 Real Memory map Address Range Sector Number Size x_ xf_ffff Flash 512KBytes (Memory Bank) x1_ x1_7ff Internal SRAM for 2KBytes (Memory Bank) Instruction x18_ x18_77ff Internal SRAM for Data 3KBytes (Memory Bank1) x2_ ~ x2fff_ffff SDRAM 8 or 16Mbytes x5_ ~ x5fff_ffff External SRAM - 46 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 5.2 Coprocessor Description Table 5-2 Coprocessor Register Description Register R/W Description SCPR15 R System Coprocessor Status Register W Master Command Register SCPR14 R/W Supervisor Stack Point Register SCPR13 R/W User Stack Pointer SCPR12 R/W Vector Base Register SCPR11 W Invalidate Cache Line and Lock Register SCPR1 - Reserved SCPR9 R/W Memory Bank Configuration Register SCPR8 R/W Sub-Bank Configuration Register SCPR7 R/W Reserved SCPR6 R/W Reserved SCPR5 R/W Sub-Bank Address Register SCPR4 R/W General Access Point Data Register SCPR3 R/W General Access Point Index Register SCPR2 R/W Reserved SCPR1 R/W Reserved SCPR R/W Reserved Advanced Digital Chips, Inc. CONFIDENTIAL 47

Ver 1.6.7 5.3 Coprocessor Control Registers 5.3.1 System Coprocessor Status Register (SCPR15) 31 R System Co-Processor Access Right (Privileged) 1 Coprocessor이접근권한을나타낸다. : Supervisor/User Accessible 1 : Supervisor Access only 3 : 28 R Coprocessor Type 1 27 : 25 R Coprocessor Subtype 24 : 19 R Reserved - 18 R L1 Cache Presented : Presented 1 : Not Presented 17 R L1 Cache Snooping Capability 1 : Support Snooping 1 : Not support Snooping 16 : 7 R Reserved - 6 R Misalign Correction Support for Data Access : Not support Misalign Correction 1 : Support Misalign Correction 5 : 2 R SCP Rending Exception Number 1111 : Inst. Fetch - Access Violation 1 : Privilege Violation Exception 11 : Data Access - Address Misalignment 1 : Data Access Access Violation 1 : Inst. Fetch - Address Misalignment 1111 : N/A 1 R SCP Pending Exception status : No Pending Exception 1 : Pending Exception Exist R Reserved - 5.3.2 Master Command Register (SCPR15) 31 : 6 W Reserved - 5 : 2 W End of Exception 1111 : Inst. Fetch - Access Violation 1 : Privilege Violation Exception 11 : Data Access - Address Misalignment 1 : Data Access Access Violation 1 : Inst. Fetch - Address Misalignment 1111 : Privilege Violation Exception 1 : W Reserved - 48 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 5.3.3 Supervisor Stack Point Register (SCPR14) 31 : 2 R/W Supervisor Stack Pointer x_ 1 : R/W Always 5.3.4 User Stack Point Register (SCPR13) 31 : 2 R/W User Stack Pointer x_ 1 : R/W Always 5.3.5 Vector Base Register (SCPR12) 31 : 2 R/W Vector Base for Exception x_ 1 : R/W Always 5.3.6 Invalidate Cache Line and Lock Register (SCPR11) 31 : 7 W Invalidation Target Address/Way - 6 : 4 W Invalidation Target Address/Way - 3 W Invalidation Mode : Address Based Invalidation 1 : Way Based Invalidation 2 W Copy-back Selection in Invalidation : Invalidation without Copy-back 1 : Invalidation with Copy-back if need 1 W Cache Line Locking in Invalidation : Invalidation without Locking 1 : Invalidation with Locking W Cache Type in Invalidation : I-Cache 1 : D-Cache - - - - Advanced Digital Chips, Inc. CONFIDENTIAL 49

Ver 1.6.7 5.3.7 Memory Bank Configuration Register (SCPR9) 31 : 16 R Reserved 15 R/W Always 14 R/W Memory Bank 3 Access Right : Supervisor only Accessible 1 : Supervisor/User Accessible 13 : 12 R/W Memory Bank 3 Cache Configuration : Disable Cache 1 : Reserved 1 : Enable Cache with Write-through 11 : N/A 11 R/W Always 1 R/W Memory Bank 2 Access Right : Supervisor only Accessible 1 : Supervisor/User Accessible 9 : 8 R/W Memory Bank 2 Cache Configuration : Disable Cache 1 : Reserved 1 : Enable Cache with Write-through 11 : N/A 7 R/W Always 6 R/W Memory Bank 1 Access Right : Supervisor only Accessible 1 : Supervisor/User Accessible 5 : 4 R/W Memory Bank 1 Cache Configuration : Disable Cache 1 : Reserved 1 : Enable Cache with Write-through 11 : N/A 3 R/W Always 2 R/W Memory Bank Access Right : Supervisor only Accessible 1 : Supervisor/User Accessible 1 : R/W Memory Bank Cache Configuration : Disable Cache 1 : Reserved 1 : Enable Cache with Write-through 11 : N/A 5 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 5.3.8 Sub-Bank Configuration Register (SCPR8) 31 : 7 R Reserved - 6 : 4 R/W Sub-Bank Index 3 R/W Sub-Bank Valid Control bit : Invalid 1 : Valid 2 R/W Sub-Bank Access Right : Supervisor only Accessible 1 : Supervisor/User Accessible 1 : R/W Sub-Bank Cache Property Control bit : Disable Cache 1 : N/A 1 : Enable Cache with Write-through 11 : N/A *** SCPR5와함께설정되어 Sub-Bank를지정한다. *** Sub-Bank가설정된영역에서는 Sub-Bank 설정정보가 SCPR9에서설정한 Memory Bank의설정보다우선순위를가진다. 5.3.9 Sub-Bank Address Register (SCPR5) 31 : 12 R/W Sub-Bank Base Address[31:12] x 11 : R/W Sub-Bank Size Enable x : 4KBytes x1 : 8KBytes x3 : 16KBytes x7 : 32KBytes xf : 64KBytes x1f : 128KBytes x3f : 256KBytes x7f : 512KBytes xff : 1MBytes x *** Sub-Bank 설정시 Nature Align 되도록설정되어야한다. Advanced Digital Chips, Inc. CONFIDENTIAL 51

Ver 1.6.7 5.3.1 General Access Point Data Register (SCPR4) 31 : R/W General Access Point Data SCPR3에서설정된레지스터의값 x_ 5.3.11 General Access Point Index Register (SCPR3) 31 : R/W General Access Point Index x_ - Core Debugging Information x_ : Backup IR x_1 : Backup ER x_2 : Backup PC x_1 : Backup EAD - System Coprocessor Debugging Information x_33 : Inst. Bus Error Address x_34 : Data Bus Error Address - Cache Lock Information x_5 : Inst. Lock Condition x_51 : Data Lock Condition - Memory Bank Management Information x_6 : Inst. MBMB Violation Address x_61 : Data MBMB Violation Address - Internal SRAM Configuration Information x_7 : Global Control Reg. Address Local Control Registers x_71 : Local I-Control Reg. Address x_711 : Local I-Control Reg.1 Address x_721 : Local I-Control Reg.2 Address x_731 : Local I-Control Reg.3 Address x_74 : Local D-Control Reg. Address x_714 : Local D-Control Reg.1 Address x_724 : Local D-Control Reg.2 Address x_734 : Local D-Control Reg.3 Address Local Start Address Registers x_72 : Local I-Start Reg. Address x_712 : Local I-Start Reg.1 Address x_722 : Local I-Start Reg.2 Address x_732 : Local I-Start Reg.3 Address x_75 : Local D-Start Reg. Address x_715 : Local D-Start Reg.1 Address x_725 : Local D-Start Reg.2 Address x_735 : Local D-Start Reg.3 Address Local End Address Registers x_73 : Local I-End Reg. Address x_713 : Local I-End Reg.1 Address 52 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 x_723 : Local I-End Reg.2 Address x_733 : Local I-End Reg.3 Address x_76 : Local D-End Reg. Address x_716 : Local D-End Reg.1 Address x_726 : Local D-End Reg.2 Address x_736 : Local D-End Reg.3 Address Advanced Digital Chips, Inc. CONFIDENTIAL 53

Ver 1.6.7 6 WATCHDOG TIMER Watchdog Timer 는시스템에러, 정상적으로응답하지않는장치또는 noise 와같은이유로 CPU 가정상적인동작을하지않을때, 정상상태로복귀시키는역할을한다. Watchdog Timer 가 Enable 되면 WDTCNT 에설정된값에서 1 씩감소하여 WDTCNT 값이 이되면 Watchdog Reset 이발생한다. Watchdog Reset 이발생하면 WDTST bit 에 Watchdog Reset 이발생한상태가저장된다. 일단 Watchdog Timer 가설정되면 Watchdog Reset 이걸리지않게하기위해서는 32 비트의 Watchdog Counter 값이 이되지않도록주기적으로 WDTCNT 을재설정하여 Watchdog Reset 이발생하지않도록해야한다. WDTMOD bit 를 Interrupt mode 로설정하면, Watchdog Reset 은발생하지않고 Interrupt 를발생시켜 WDTCNT 에설정된값이 이되었음을알려준다. 6.1 Register Description 6.1.1 Watchdog Timer Control Register (WDTCTRL) Address : x82_ 31 : 5 R Reserved - 4 R WDTST : Watchdog timer status bit When watchdog timer is reset mode, : No watchdog reset 1 : Watchdog reset When watchdog timer is interrupt mode, : No watchdog interrupt 1 : Watchdog interrupt Clear at read 3 : 2 R Reserved - 1 R/W WDTMOD : Watchdog timer mode select bit : Reset mode 1 : Interrupt mode R/W WDTEN : Watchdog timer enable bit : Disable 1 : Enable 6.1.2 Watchdog Timer Counter Value Register (WDTCNT) Address : x82_4 31 : R/W Watchdog timer counter 32-bit value. Down-counter xffff_ffff 54 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 7 GPIO (GENERAL PURPOSE I/O) GPIO Ports 는 8-bit 으로구성된 9 개블록과 3-bit 으로구성된 1 개의블록으로총 75 또는 69 개의 I/O Ports 를제공한다. 각 Ports 는레지스터설정으로쉽게구성될수있으며, 다양한입출력응용과시스템구성에사용된다. 7.1 Features GP.x has 8 I/O Ports(-8/16M) or 5 I/O Ports(-8/16MF512) GP1.x has 8 I/O Ports GP2.x has 8 I/O ports GP3.x has 8 I/O ports GP4.x has 8 I/O Ports GP5.x has 8 I/O Ports GP6.x has 8 I/O ports GP7.x has 8 I/O ports GP8.x has 8 I/O Ports GP9.x has 3 I/O Ports(-8/16M Only) 7.2 Block Diagram GPxPUS GPxAF Alternate Function (Direction) GPxODIR/GPxIDIR VDD33 Alternate Function (Output) GPxOHIGH/GPxOLOW Alternate Function (Input) 1 GND GPxCMOS GPxSCHMT GPxEDS GPxILEV Edge Detect SYNCHRONIZER Q D Q D F/F Latch G GPxRED GRxFED CLK GPxPDS Figure 7-1 GPIO Block Diagram Advanced Digital Chips, Inc. CONFIDENTIAL 55

Ver 1.6.7 7.3 Function Description 7.3.1 Port Control GPIO Ports 는 GPxODIR 레지스터를통해각 Port 별로 Output mode 로설정되고또한 GPxIDIR 레지스터에의해각 Port 별로 Input mode 로설정된다. 각 Port 의설정상태는 GPxDIR 레지스터를통해확인할수있다. GPxODIR 레지스터와 GPxIDIR 레지스터설정시 1 인비트만해당동작으로설정되고, 인비트는어떠한영향을미치지못한다. GPIO Ports 의출력레벨은 Output mode 로설정된상태에서 GPxOHIGH 레지스터를통해 High Level 로설정되고, GPxOLOW 레지스터를통해 Low Level 로설정된다. Output level 의설정상태는 GPxOLEV 레지스터를통해확인할수있다. GPIO Ports 의입력레벨은 GPxILEV 레지스터를통해확인할수있다. 각 Port 에연결된 Pull-up 저항은외부입력이존재하거나출력인경우에는 Pull-up 을제거하면, 신호레벨이 Low 일때누설전류를줄일수있다. Table 7-1 Internal Pull-up Resistance Characteristics Parameter Min Typ Max Unit Pull-Up Resistance 34 41 64 K Pull-Down Resistance 33 44 79 K 7.3.2 Port Edge Detect EIRQ 핀을통한외부인터럽트이외에 GPIO 의 Port Edge Detect 을통해각각의그룹별로외부인터럽트를수행할수있다. Port 들은 Rising Edge, Falling Edge 그리고 Any Edge 모드를지원한다. 7.3.3 Port Alternate Functions GPIO Ports 의초기값은 Input 상태이며, Alternate Function 의설정을통해외부 Interface 를갖는 Peripheral Function 들과 Ports 를공유할수있다. Default 로 GPIO 가선택이되어있지만, register setting 에의해다른 function 으로사용될수있다. 또한, booting mode 에따라일부 port 의 default 가변하게되며, 일부는 ntest pin 에의해특정용도로고정되기도한다. Register PAF x8234 bit 1st 2nd 3rd 4th 1 1 11 1: snd2_pwml_p spi_cs twi_scl P. 3:2 snd2_pwml_n spi_miso twi_sda P.1 5:4 snd2_pwmr_p spi_mosi sram_cs1# P.2 7:6 snd2_pwmr_n spi_sck sram_cs2# P.3 9:8 snd3_pwml_p flash_cs cap_in1 P.4 11:1 snd3_pwml_n flash_dq1 tm_out1 P.5 13:12 snd3_pwmr_p flash_dq2 uart_tx4 P.6 15:14 snd3_pwmr_n TAP_SEL uart_rx4 P.7 Default 11b Flash Boot: 1b Etc.: 11b * 8/16M Only ntest = : fixed 1b Etc. : 11b 56 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 PAF1 x82344 PAF2 x82348 PAF3 x8234c PAF4 x82341 PAF5 x823414 PAF6 x823418 1: uart_tx snd_mclk twi_scl P1. 3:2 uart_rx snd_sdi twi_sda P1.1 5:4 nf_cs# pwm_fault1 sram_cs1# P1.2 7:6 nf_ale sdhc_cmd sram_cs3# P1.3 9:8 nf_cle sdhc_clk sram_be1# P1.4 11:1 nf_we snd_sclk sram_a17 P1.5 13:12 nf_re snd_lrclk sram_a18 P1.6 15:14 nf_busyx snd_sdo sram_wait# P1.7 1: nf_d uart_tx3 sram_a8/d8 P2. 3:2 nf_d1 uart_rx3 sram_a9/d9 P2.1 5:4 nf_d2 uart_tx4 sram_a1/d1 P2.2 7:6 nf_d3 uart_rx4 sram_a11/d11 P2.3 9:8 nf_d4 sdhc_d sram_a12/d12 P2.4 11:1 nf_d5 sdhc_d1 sram_a13/d13 P2.5 13:12 nf_d6 sdhc_d2 sram_a14/d14 P2.6 15:14 nf_d7 sdhc_d3 sram_a15/d15 P2.7 1: sram_a/a8/d pwm_h cap_in P3. 3:2 sram_a1/a9/d1 pwm_l tm_out P3.1 5:4 sram_a2/a1/d2 pwm_h1 uart_tx3 P3.2 7:6 sram_a3/a11/d3 pwm_l1 uart_rx3 P3.3 9:8 sram_a4/a12/d4 pwm_h2 cap_in2 P3.4 11:1 sram_a5/a13/d5 pwm_l2 tm_out2 P3.5 13:12 sram_a6/a14/d6 pwm_h3 ohci_overcurrent P3.6 15:14 sram_a7/a15/d7 pwm_l3 ohci_portpower P3.7 1: sram_a16 pwm_fault eirq P4. 3:2 sram_ale eirq1 P4.1 5:4 sram_ale1 uart_tx1 P4.2 7:6 sram_re# uart_rx1 P4.3 9:8 sram_we# twi_scl uart_tx2 P4.4 11:1 sram_cs# twi_sda uart_rx2 P4.5 13:12 snd_mclk spi_sck1 cap_in3 P4.6 15:14 snd_sdi spi_cs1 tm_out3 P4.7 1: snd_sclk spi_miso1 sram_a P5. 3:2 snd_lrclk spi_mosi1 sram_a1 P5.1 5:4 snd_sdo uart_tx sram_a2 P5.2 7:6 crtc_clk_in uart_rx sram_a3 P5.3 9:8 vsync eirq sram_a4 P5.4 11:1 hsync eirq1 sram_a5 P5.5 13:12 disp_en uart_tx1 sram_a6 P5.6 15:14 crtc_clk_out uart_rx1 sram_a7 P5.7 1: r ntrst P6. 3:2 r1 TCK P6.1 5:4 r2 TDI P6.2 11b NAND Boot: b NOR Boot: 1b Etc.: 11b NAND Boot: b NOR Boot: 1b Etc.: 11b NOR Boot: b Etc.: 11b NOR Boot: b Etc.: 11b 11b NOR Boot: 1b Default: 1b 7:6 r3 sdhc_cmd snd1_sclk P6.3 11b Advanced Digital Chips, Inc. CONFIDENTIAL 57

Ver 1.6.7 PAF7 x82341c PAF8 x82342 PAF9 x823424 9:8 r4 sdhc_d snd1_lrclk P6.4 11:1 r5 sdhc_d1 snd1_sdo P6.5 13:12 r6 sdhc_d2 uart_tx2 P6.6 15:14 r7 sdhc_d3 uart_rx2 P6.7 1: g TMS sram_cs1# P7. 3:2 g1 TDO sram_cs2# P7.1 5:4 g2 sdhc_clk sram_a1 P7.2 7:6 g3 cfg sram_a11 P7.3 9:8 g4 cfg1 sram_a12 P7.4 11:1 g5 cfg2 sram_a13 P7.5 13:12 g6 cfg3 sram_a14 P7.6 15:14 g7 cfg4 sram_a15 P7.7 Default : 1b NOR Boot: 1b Etc.: 11b 1: b snd2_pwml_p sram_a8 P8. NOR Boot: 1b 3:2 b1 snd2_pwml_n sram_a9 P8.1 Etc.: 11b 5:4 b2 snd2_pwmr_p cap_in1 P8.2 7:6 b3 snd2_pwmr_n tm_out1 P8.3 9:8 b4 snd3_pwml_p cap_in2 P8.4 11:1 b5 snd3_pwml_n tm_out2 P8.5 13:12 b6 snd3_pwmr_p cap_in3 P8.6 15:14 b7 snd3_pwmr_n tm_out3 P8.7 1: snd1_sclk flash_dq cap_in P9. 3:2 snd1_lrclk flash_clk tm_out P9.1 5:4 snd1_sdo flash_dq3 sram_cs3# P9.2 11b Flash Boot: 1b Etc.: 11b * 8/16M Only 58 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 7.4 Register Description 7.4.1 Port Direction Registers ( GPxDIR ) Address: xffff_3 / xffff_34 / xffff_38 / xffff_3c / xffff_31 / xffff_314 / xffff_318 / xffff_31c / xffff_32 / xffff_324 31 : 9 R Reserved - 8 R GPx.OMD : GPx. Output Control Mode bit : Pin 단위 1 : Port 단위 7 : R GPx.yDIR : GPx.y Direction bit : Input 1 : Output x 7.4.2 Port Direction Output Mode Setting Registers ( GPxODIR ) Address: xffff_3 / xffff_34 / xffff_38 / xffff_3c / xffff_31 / xffff_314 / xffff_318 / xffff_31c / xffff_32 / xffff_324 31 : 9 R Reserved - 8 W GPx.OPRT : Output Control by Port Mode Setting bit - 7 W GPx.7ODIR : GPx.7 Direction Output Mode Setting bit - 6 W GPx.6ODIR : GPx.6 Direction Output Mode Setting bit - 5 W GPx.5ODIR : GPx.5 Direction Output Mode Setting bit - 4 W GPx.4ODIR : GPx.4 Direction Output Mode Setting bit - 3 W GPx.3ODIR : GPx.3 Direction Output Mode Setting bit - 2 W GPx.2ODIR : GPx.2 Direction Output Mode Setting bit - 1 W GPx.1ODIR : GPx.1 Direction Output Mode Setting bit - W GPx.ODIR : GPx. Direction Output Mode Setting bit - *** Port Direction Output Mode Setting bit : No effect 1 : Set to output mode the corresponding bit in the PxDIR registers 7.4.3 Port Direction Input Mode Setting Registers ( GPxIDIR ) Address: xffff_34 / xffff_344 / xffff_384 / xffff_3c4 / xffff_314 / xffff_3144 / xffff_3184 / xffff_31c4 / xffff_324 / xffff_3244 31 : 8 R Reserved - 8 W GPx.OPIN : Output Control by Pin Mode Setting bit - 7 W GPx.7IDIR : GPx.7 Direction Input Mode Setting bit - 6 W GPx.6IDIR : GPx.6 Direction Input Mode Setting bit - 5 W GPx.5IDIR : GPx.5 Direction Input Mode Setting bit - 4 W GPx.4IDIR : GPx.4 Direction Input Mode Setting bit - 3 W GPx.3IDIR : GPx.3 Direction Input Mode Setting bit - 2 W GPx.2IDIR : GPx.2 Direction Input Mode Setting bit - 1 W GPx.1IDIR : GPx.1 Direction Input Mode Setting bit - W GPx.IDIR : GPx. Direction Input Mode Setting bit - *** Port Direction Input Mode Setting bit : No effect 1 : Set to input mode the corresponding bit in the PxDIR registers Advanced Digital Chips, Inc. CONFIDENTIAL 59

Ver 1.6.7 7.4.4 Port Output Data Level Registers ( GPxOLEV ) Address: xffff_38 / xffff_348 / xffff_388 / xffff_3c8 / xffff_318 / xffff_3148 / xffff_3188 / xffff_31c8 / xffff_328 / xffff_3248 31 : 8 R Reserved - 7 : R GPx.yOLEV : GPx.y Output Level bit : Low Level 1 : High Level xff 7.4.5 Port Output Data Registers ( GPxDOUT ) Address: xffff_38 / xffff_348 / xffff_388 / xffff_3c8 / xffff_318 / xffff_3148 / xffff_3188 / xffff_31c8 / xffff_328 / xffff_3248 7 : R/W GPx.DO : GPx.Port Output Data xff *** GPxDIR 의 8 번 bit 가 1 인경우, 이 register 를이용해 GPIO Port output 을결정한다. 7.4.6 Port Output Data High Level Setting Registers ( GPxOHIGH ) Address: xffff_38 / xffff_348 / xffff_388 / xffff_3c8 / xffff_318 / xffff_3148 / xffff_3188 / xffff_31c8 / xffff_328 / xffff_3248 31 : 8 R Reserved - 7 W GPx.7OH : GPx.7 Output Data High Level Setting bit - 6 W GPx.6OH : GPx.6 Output Data High Level Setting bit - 5 W GPx.5OH : GPx.5 Output Data High Level Setting bit - 4 W GPx.4OH : GPx.4 Output Data High Level Setting bit - 3 W GPx.3OH : GPx.3 Output Data High Level Setting bit - 2 W GPx.2OH : GPx.2 Output Data High Level Setting bit - 1 W GPx.1OH : GPx.1 Output Data High Level Setting bit - W GPx.OH : GPx. Output Data High Level Setting bit - *** Port Output Data High Level Setting bit (GPxDIR의 8번 bit가 인경우유효하다.) : No effect 1 : Set to high level output data the corresponding bit in the PxOLEV registers 7.4.7 Port Output Data Low Level Setting Registers ( GPxOLOW ) Address: xffff_3c / xffff_34c / xffff_38c / xffff_3cc / xffff_31c / xffff_314c / xffff_318c / xffff_31cc / xffff_32c / xffff_324c 31 : 8 R Reserved - 7 W GPx.7OL : GPx.7 Output Data Low Level Setting bit - 6 W GPx.6OL : GPx.6 Output Data Low Level Setting bit - 5 W GPx.5OL : GPx.5 Output Data Low Level Setting bit - 4 W GPx.4OL : GPx.4 Output Data Low Level Setting bit - 3 W GPx.3OL : GPx.3 Output Data Low Level Setting bit - 2 W GPx.2OL : GPx.2 Output Data Low Level Setting bit - 1 W GPx.1OL : GPx.1 Output Data Low Level Setting bit - W GPx.OL : GPx. Output Data Low Level Setting bit - *** Port Output Data Low Level Setting bit (GPxDIR의 8번 bit가 인경우유효된다.) : No effect 1 : Set to low level output data the corresponding bit in the PxOLEV registers 6 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 7.4.8 Port Input Data Level Registers ( GPxILEV ) Address: xffff_31 / xffff_35 / xffff_39 / xffff_3d / xffff_311 / xffff_315 / xffff_319 / xffff_31d / xffff_321 / xffff_325 31 : 8 R Reserved - 7 R GPx.7ILEV : GPx.7 Input Level bit : Low Level 1 : High Level 6 R GPx.6ILEV : GPx.6 Input Level bit : Low Level 1 : High Level 5 R GPx.5ILEV : GPx.5 Input Level bit : Low Level 1 : High Level 4 R GPx.4ILEV : GPx.4 Input Level bit : Low Level 1 : High Level 3 R GPx.3ILEV : GPx.3 Input Level bit : Low Level 1 : High Level 2 R GPx.2ILEV : GPx.2 Input Level bit : Low Level 1 : High Level 1 R GPx.1ILEV : GPx.1 Input Level bit : Low Level 1 : High Level R GPx.ILEV : GPx. Input Level bit : Low Level 1 : High Level - - - - - - - - 7.4.9 Port Pull-up Status Registers ( GPxPUS ) Address: xffff_318 / xffff_358 / xffff_398 / xffff_3d8 / xffff_3118 / xffff_3158 / xffff_3198 / xffff_31d8 / xffff_3218 / xffff_3258 31 : 8 R Reserved - 7 : R GPx.yUP : GPx.y Pull-up Status bit x : Pull-up Disable 1 : Pull-up Enable 7.4.1 Port Pull-up Enable Registers ( GPxPUEN ) Address: xffff_318 / xffff_358 / xffff_398 / xffff_3d8 / xffff_3118 / xffff_3158 / xffff_3198 / xffff_31d8 / xffff_3218 / xffff_3258 31 : 8 R Reserved - 7 W GPx.7PUEN : GPx.7 Pull-up enable bit - 6 W GPx.6PUEN : GPx.6 Pull-up enable bit - 5 W GPx.5PUEN : GPx.5 Pull-up enable bit - 4 W GPx.4PUEN : GPx.4 Pull-up enable bit - 3 W GPx.3PUEN : GPx.3 Pull-up enable bit - 2 W GPx.2PUEN : GPx.2 Pull-up enable bit - 1 W GPx.1PUEN : GPx.1 Pull-up enable bit - W GPx.PUEN : GPx. Pull-up enable bit - *** Port Pull-up enable bit : No effect 1 : Set to pull-up the corresponding bit in the PxPUS registers Advanced Digital Chips, Inc. CONFIDENTIAL 61

Ver 1.6.7 7.4.11 Port Pull-up Disable Registers ( GPxPUDIS ) Address: xffff_31c / xffff_35c / xffff_39c / xffff_3dc / xffff_311c / xffff_315c / xffff_319c / xffff_31dc / xffff_321c / xffff_325c 31 : 8 R Reserved - 7 W GPx.7PUDIS : GPx.7 Pull-up disable bit - 6 W GPx.6PUDIS : GPx.6 Pull-up disable bit - 5 W GPx.5PUDIS : GPx.5 Pull-up disable bit - 4 W GPx.4PUDIS : GPx.4 Pull-up disable bit - 3 W GPx.3PUDIS : GPx.3 Pull-up disable bit - 2 W GPx.2PUDIS : GPx.2 Pull-up disable bit - 1 W GPx.1PUDIS : GPx.1 Pull-up disable bit - W GPx.PUDIS : GPx. Pull-up disable bit - *** Port Pull-up disable bit : No effect 1 : Set to pull-up the corresponding bit in the PxPUS registers 62 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 7.4.12 Port Rising Edge Detect Registers ( GPxRED ) Address: xffff_32 / xffff_36 / xffff_3a / xffff_3e / xffff_312 / xffff_316 / xffff_31a / xffff_31e / xffff_322 / xffff_326 31 : 8 R Reserved - 7 R/W GPx.7RED : GPx.7 Rising Edge Detect bit : Disable 1 : Enable 6 R/W GPx.6RED : GPx.6 Rising Edge Detect bit : Disable 1 : Enable 5 R/W GPx.5RED : GPx.5 Rising Edge Detect bit : Disable 1 : Enable 4 R/W GPx.4RED : GPx.4 Rising Edge Detect bit : Disable 1 : Enable 3 R/W GPx.3RED : GPx.3 Rising Edge Detect bit : Disable 1 : Enable 2 R/W GPx.2RED : GPx.2 Rising Edge Detect bit : Disable 1 : Enable 1 R/W GPx.1RED : GPx.1 Rising Edge Detect bit : Disable 1 : Enable R/W GPx.RED : GPx. Rising Edge Detect bit : Disable 1 : Enable *** Rising Edge 와 Falling Edge가동시에설정되었을때는 Any Edge mode 가된다. 7.4.13 Port Falling Edge Detect Registers ( GPxFED ) Address: xffff_324 / xffff_364 / xffff_3a4 / xffff_3e4 / xffff_3124 / xffff_3164 / xffff_31a4 / xffff_31e4 / xffff_3224 / xffff_3264 31 : 8 R Reserved - 7 R/W GPx.7FED : GPx.7 Falling Edge Detect bit : Disable 1 : Enable 6 R/W GPx.6FED : GPx.6 Falling Edge Detect bit : Disable 1 : Enable 5 R/W GPx.5FED : GPx.5 Falling Edge Detect bit : Disable 1 : Enable 4 R/W GPx.4FED : GPx.4 Falling Edge Detect bit : Disable 1 : Enable 3 R/W GPx.3FED : GPx.3 Falling Edge Detect bit : Disable 1 : Enable 2 R/W GPx.2FED : GPx.2 Falling Edge Detect bit : Disable 1 : Enable 1 R/W GPx.1FED : GPx.1 Falling Edge Detect bit : Disable 1 : Enable R/W GPx.FED : GPx. Falling Edge Detect bit : Disable 1 : Enable *** Rising Edge 와 Falling Edge가동시에설정되었을때는 Any Edge mode 가된다. Advanced Digital Chips, Inc. CONFIDENTIAL 63

Ver 1.6.7 7.4.14 Port Edge Detect Status Registers ( GPxEDS ) Address: xffff_328 / xffff_368 / xffff_3a8 / xffff_3e8 / xffff_3128 / xffff_3168 / xffff_31a8 / xffff_31e8 / xffff_3228 / xffff_3268 31 : 8 R Reserved - 7 R/W GPx.7EDS : GPx.7 Edge Detect Status bit 6 R/W GPx.6EDS : GPx.6 Edge Detect Status bit 5 R/W GPx.5EDS : GPx.5 Edge Detect Status bit 4 R/W GPx.4EDS : GPx.4 Edge Detect Status bit 3 R/W GPx.3EDS : GPx.3 Edge Detect Status bit 2 R/W GPx.2EDS : GPx.2 Edge Detect Status bit 1 R/W GPx.1EDS : GPx.1 Edge Detect Status bit R/W GPx.EDS : GPx. Edge Detect Status bit *** Port Edge Detect Status bit : No edge detect has occurred on pin 1 : Edge detect has occurred on pin *** Status bits are cleared by writing a one to them. *** Writing a zero to a status bit are no effect. 7.4.15 Port Open Drain Mode Control Registers ( GPxODM ) Address: xffff_32c / xffff_36c / xffff_3ac / xffff_3ec / xffff_312c / xffff_316c / xffff_31ac / xffff_31ec / xffff_322c / xffff_326c 31 : 8 R Reserved - 7 : R/W GPx.yOD : GPx.y Open Drain Mode Setting bit : Normal CMOS Output Mode 1 : Open Drain Mode 7.4.16 Port Schmitt Input Enable Registers ( GPxSHMT ) Address: xffff_334 / xffff_374 / xffff_3b4 / xffff_3f4 / xffff_3134 / xffff_3174 /xffff_3174(b4) * /xffff_31f4 / xffff_3234 / xffff_3274 31 : 8 R Reserved - 7 W GPx.7SHMT : GPx.7 Schmitt input enable bit 6 W GPx.6SHMT : GPx.6 Schmitt input enable bit 5 W GPx.5SHMT : GPx.5 Schmitt input enable bit 4 W GPx.4SHMT : GPx.4 Schmitt input enable bit 3 W GPx.3SHMT : GPx.3 Schmitt input enable bit 2 W GPx.2SHMT : GPx.2 Schmitt input enable bit 1 W GPx.1SHMT : GPx.1 Schmitt input enable bit W GPx.SHMT : GPx. Schmitt input enable bit *** Port Schmitt input enable bit : CMOS input mode 1 : Schmitt input mode * GP6.xSHMT bits are configured by GP5.xSHMT (xffff_3174) register. 64 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 7.4.17 Port Pull-down Status Registers ( GPxPDS ) Address: xffff_33 / xffff_37 / xffff_3b / xffff_3f / xffff_313 / xffff_317 / xffff_31b / xffff_31f / xffff_323 / xffff_327 31 : 8 R Reserved - 7 : R GPx.yDN : GPx.y Pull-down Status bit : Pull-down Disable 1 : Pull-down Enable x 7.4.18 Port Pull-down Enable Registers ( GPxPDEN ) Address: xffff_33 / xffff_37 / xffff_3b / xffff_3f / xffff_313 / xffff_317 / xffff_31b / xffff_31f / xffff_323 / xffff_327 31 : 8 R Reserved - 7 W GPx.7PDEN : GPx.7 Pull-down enable bit - 6 W GPx.6PDEN : GPx.6 Pull-down enable bit - 5 W GPx.5PDEN : GPx.5 Pull-down enable bit - 4 W GPx.4PDEN : GPx.4 Pull-down enable bit - 3 W GPx.3PDEN : GPx.3 Pull-down enable bit - 2 W GPx.2PDEN : GPx.2 Pull-down enable bit - 1 W GPx.1PDEN : GPx.1 Pull-down enable bit - W GPx.PDEN : GPx. Pull-down enable bit - *** Port Pull-down enable bit : No effect 1 : Set to pull-down the corresponding bit in the PxPDS registers 7.4.19 Port Pull-down Disable Registers ( GPxPDDIS ) Address: xffff_31c / xffff_35c / xffff_39c / xffff_3dc / xffff_311c / xffff_315c / xffff_319c / xffff_31dc / xffff_321c / xffff_325c 31 : 8 R Reserved - 7 W GPx.7PDDIS : GPx.7 Pull-down disable bit - 6 W GPx.6PDDIS : GPx.6 Pull-down disable bit - 5 W GPx.5PDDIS : GPx.5 Pull-down disable bit - 4 W GPx.4PDDIS : GPx.4 Pull-down disable bit - 3 W GPx.3PDDIS : GPx.3 Pull-down disable bit - 2 W GPx.2PDDIS : GPx.2 Pull-down disable bit - 1 W GPx.1PDDIS : GPx.1 Pull-down disable bit - W GPx.PDDIS : GPx. Pull-down disable bit - *** Port Pull-down disable bit : No effect 1 : Set to pull-down the corresponding bit in the PxPDS registers Advanced Digital Chips, Inc. CONFIDENTIAL 65

Ver 1.6.7 8 INTERRUPT CONTROLLER 는 46 개채널의인터럽트입력을가지며, 이입력들은 Timer, SPI, TWI, UART 등과같은내부장치에서발생하는 44 개의인터럽트와외부 2 개의인터럽트로구성된다. 8.1 Features - 46 채널의인터럽트 (2 채널의외부인터럽트와 44 채널의내부인터럽트 ) - 외부인터럽트에대한동작조건설정 (5 가지 ) - 내부인터럽트에대한동작조건설정 (2 가지 ) - 채널별인터럽트 Enable 기능 - 채널별인터럽트 Mask 기능 - 개별적으로프로그램가능한인터럽트우선순위 8.2 Function Description 인터럽트의순차처리는다음과같은과정을통하여이루어진다. 1. 각인터럽트소스들은인터럽트제어기에인터럽트를요청한다. 2. Interrupt Enable Register 에의해선별된후, Interrupt Pending Register 에저장한다. 3. 인터럽트우선순위를판단한후, CPU 에인터럽트를요청한다. 4. 인터럽트를요청받으면 CPU 의인터럽트가비활성화되며인터럽트벡터주소를읽어서해당 Interrupt Service Routine(ISR) 으로진입한다. 5. ISR 을수행한다. 6. ISR 수행이끝나면 Interrupt Pending Clear Register 에해당 Vector 값을씀으로써 Interrupt Pending Register 에저장된인터럽트값을지운다. 7. ISR 을빠져나오면서 CPU 의인터럽트가활성화된다. 인터럽트의중첩처리는다음과같은과정을통하여이루어진다. 1. 각인터럽트소스들은인터럽트제어기에인터럽트를요청한다. 2. Interrupt Enable Register 에의해선별된후, Interrupt Pending Register 에저장한다. 3. 인터럽트우선순위를판단한후, CPU 에인터럽트를요청한다. 4. 인터럽트를요청받으면 CPU 의인터럽트가비활성화되며인터럽트벡터주소를읽어서해당 Interrupt Service Routine(ISR) 으로진입한다. 5. 인터럽트의중첩을허용하기위해 Interrupt Pending Clear Register 에해당 Vector 값을씀으로써 Interrupt Pending Register 에저장된인터럽트값을지우고 asm( set 13 ) 을통해 CPU 의인터럽트를활성화시킨다. 6. ISR 을수행한다. 7. 만약, 현재 ISR 의수행도중다시인터럽트가발생하면중첩처리가허용되어해당 ISR 로진입한다. 8. 새롭게진입한 ISR 의수행이끝나면이전 ISR 로복귀하여나머지수행을진행한다. 9. ISR 수행이끝나면완전히빠져나온다. 66 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 8.2.1 Interrupt Vector and Priority 인터럽트우선순위는 EIRQ 가가장높다. 인터럽트벡터주소는 CPU 가 32bit Addressing 을하기때문에각각 4bytes 의크기를가진다. Table 8-1 Interrupt Vector & Priority Vector No. Description Vector Address x53 Reserved x14c x52 Dedicated PWM Interrupt x148 x51 QEI Interrupt x144 x5 Reserved x14 x4f Fault B Interrupt x13c x4e Fault A Interrupt x138 x4d Capture Overflow Interrupt x134 x4c SPI 1 Interrupt x13 x4b GPIO 9 Interrupt x12c x4a TWI Interrupt x128 x49 GPIO 8 Interrupt x124 x48 Reserved x12 x47 GPIO 7 Interrupt x11c x46 UART 4 (IrDA) Interrupt x118 x45 GPIO 6 Interrupt x114 x44 Watch dog Interrupt x11 x43 GPIO 5 Interrupt x1c x42 ADC Interrupt x18 x41 GPIO 4 Interrupt x14 x4 Reserved x1 x3f DMA CH7 Interrupt xfc x3e UART 3 Interrupt xf8 x3d GPIO 3 Interrupt xf4 x3c SDHC Interrupt xf x3b DMA CH6 Interrupt xec x3a NAND Flash Interrupt xe8 x39 Timer 3 Interrupt xe4 x38 Reserved xe x37 DMA CH5 Interrupt xdc x36 UART 2 Interrupt xd8 x35 GPIO 2 Interrupt xd4 x34 USB Host Interrupt xd x33 DMA CH4 Interrupt xcc x32 USB Device Interrupt xc8 x31 Timer 2 Interrupt xc4 x3 Reserved xc x2f DMA CH3 Interrupt xbc x2e UART 1 Interrupt xb8 x2d GPIO 1 Interrupt xb4 x2c SPI Interrupt xb x2b DMA CH2 Interrupt xac x2a PMU Interrupt xa8 Advanced Digital Chips, Inc. CONFIDENTIAL 67

Ver 1.6.7 x29 Timer 1 Interrupt xa4 x28 EIRQ1 Interrupt xa x27 DMA CH1 Interrupt x9c x26 UART Interrupt x98 x25 GPIO Interrupt x94 x24 Frame Sync. Interrupt x9 x23 DMA CH Interrupt x8c x22 Sound Mixer Interrupt x88 x21 Timer Interrupt x84 x2 EIRQ Interrupt (Highest Priority) x8 68 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 8.2.2 External Interrupt (EIRQx) External Interrupt 는 EINTMOD 레지스터의설정에의해 5 가지형태의외부인터럽트를받아들인다. - Low Level Mode 에서는 External Interrupt 신호가 Low 를유지하는동안에매 System Cycle 마다인터럽트발생시킨다. - High Level Mode 에서는 External Interrupt 신호가 High 를유지하는동안에매 System Cycle 마다인터럽트를발생시킨다. - Falling Edge Mode 에서는 External Interrupt 신호가 High->Low 로바뀔때인터럽트를발생시킨다. - Rising Edge Mode 에서는 External Interrupt 신호가 Low->High 로바뀔때인터럽트를발생시킨다. - Any Edge Mode 에서는 External Interrupt 신호가 High->Low 또는 Low-> High 로바뀔때인터럽트를발생시킨다. External Interrupt Low Level Interrupt Event High Level Interrupt Event Falling Edge Interrupt Event Rising Edge Interrupt Event Any Edge Interrupt Event Figure 8-1 External Interrupt Mode 8.2.3 Internal Interrupt Mode 내부인터럽트는모두 Rising Edge 로동작한다. 그러나사용자가 High Level 로인터럽트를처리를원할경우에 Internal Interrupt Mode Registers 를통해설정할수있다. Advanced Digital Chips, Inc. CONFIDENTIAL 69

Ver 1.6.7 8.2.4 Interrupt Pending and Interrupt Pending Clear 각인터럽트의발생상태는 Interrupt Pending Registers 를통해확인할수있다. 일단한번발생한인터럽트는 Interrupt Pending Clear Register 에의해 Clear 되기전까지는계속 Interrupt Pending Register 에저장된다. 또한현재발생한인터럽트보다높은우선순위의인터럽트가 Masking 되지않은상태로 Interrupt Pending Registers 에저장되어있을경우에는높은우선순위의인터럽트가모두 Clear 될때까지 Interrupt Pending Registers 에저장되어자신의우선순위가되기를기다린다. Interrupt Pending Registers 에저장된인터럽트들을 Clear 하기위해서는 Interrupt Pending Clear Register 를통해해당인터럽트벡터번호값을 Write 하면된다. 8.2.5 Interrupt Enable Interrupt Mask Registers 에의해 Mask 되어있는인터럽트는 Interrupt Pending Registers 에계속저장되는데비해, Interrupt Enable Registers(IENR) 에의해 Disable 된인터럽트는 Interrupt Pending Registers 에저장되지않는다. 따라서이레지스터는전혀받아들이고싶지않은인터럽트에대해 Disable 하는데사용한다. 8.2.6 Interrupt Mask Set/Clear Register Set 이면 Request 가 Enable 되고, Clear 이면 Request 가 Disable 된다. 각인터럽트는 Interrupt Mask Registers 에의해해당인터럽트에대한 Request 를수행할수있다. Interrupt Mask Set bit 가 1 일경우에는 Interrupt Pending Register 에저장된 Interrupt 를 CPU 로요청하고, Interrupt Mask Clear bit 가 1 일경우에는 Interrupt Pending Register 에저장되어있는 Interrupt 를 CPU 로요청하지못한다. 설정되지않은나머지 Interrupt 들은요청될수있다. Mask bit 가 으로설정된인터럽트라도 Interrupt Pending Registers(IPR) 에는저장되기때문에 Mask bit 을 1 로재설정하면 Interrupt Pending Registers 에저장되어있는인터럽트가우선순위에의해인터럽트를다시요청한다. 7 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 8.3 Register Description 8.3.1 Interrupt Pending Clear Register (INTPENDCLR) Address : xffff_ 31 : 8 R Reserved - 7 : W Interrupt Pending Register Clear Value (x2 ~ x52) xff *** Interrupt Pending Register를 Clear 하기위해서는 Interrupt Vector No. 값으로 clear 해 야한다. (Interrupt Vector No. 참고 ) 8.3.2 External Interrupt Mode and External PIN Level Register (EINTMOD) Address : xffff_4 31:8 R Reserved - 7 R EIRQ1ST : EIRQ1 PIN Level - 6 : 4 R/W EIRQ1MOD : EIRQ1 Active State 1 : Low Level 1 : High Level 1 : Falling Edge 11 : Rising Edge 1xx : Any Edge 3 R EIRQST : EIRQ PIN Level - 2 : R/W EIRQMOD : EIRQ Active State 1 : Low Level 1 : High Level 1 : Falling Edge 11 : Rising Edge 1xx : Any Edge Advanced Digital Chips, Inc. CONFIDENTIAL 71

Ver 1.6.7 8.3.3 Internal Interrupt Mode Register (IINTMODn) Address : xffff_8 / xffff_48 31 R/W Vector No. x3f / x5f Interrupt Mode bit 3 R/W Vector No. x3e / x5e Interrupt Mode bit 29 R/W Vector No. x3d / x5d Interrupt Mode bit 28 R/W Vector No. x3c / x5c Interrupt Mode bit - 27 R/W Vector No. x3b / x5b Interrupt Mode bit 26 R/W Vector No. x3a / x5a Interrupt Mode bit 25 R/W Vector No. x39 / x59 Interrupt Mode bit 24 - Reserved - 23 R/W Vector No. x37 / x57 Interrupt Mode bit 22 R/W Vector No. x36 / x56 Interrupt Mode bit 21 R/W Vector No. x35 / x55 Interrupt Mode bit 2 R/W Vector No. x36 / x54 Interrupt Mode bit - 19 R/W Vector No. x33 / x53 Interrupt Mode bit 18 R/W Vector No. x32 / x52 Interrupt Mode bit 17 R/W Vector No. x31 / x51 Interrupt Mode bit 16 - Reserved - 15 R/W Vector No. x2f / x4f Interrupt Mode bit 14 R/W Vector No. x2e / x4e Interrupt Mode bit 13 R/W Vector No. x2d / x4d Interrupt Mode bit 12 R/W Vector No. x2c / x4c Interrupt Mode bit - 11 R/W Vector No. x2b / x4b Interrupt Mode bit 1 R/W Vector No. x2a / x4a Interrupt Mode bit 9 R/W Vector No. x29 / x49 Interrupt Mode bit 8 - Reserved - 7 R/W Vector No. x27 / x47 Interrupt Mode bit 6 R/W Vector No. x26 / x46 Interrupt Mode bit 5 R/W Vector No. x25 / x45 Interrupt Mode bit 4 R/W Vector No. x24 / x44 Interrupt Mode bit - 3 R/W Vector No. x23 / x43 Interrupt Mode bit 2 R/W Vector No. x22 / x42 Interrupt Mode bit 1 R/W Vector No. x21 / x41 Interrupt Mode bit - Reserved - *** Internal Interrupt Mode bit : High Level Mode 1 : Rising Edge Mode 72 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 8.3.4 Interrupt Pending Register (INTPENDn) Address : xffff_c / xffff_4c 31 R Vector No. x3f / x5f Interrupt Pending bit - 3 R Vector No. x3e / x5e Interrupt Pending bit - 29 R Vector No. x3d / x5d Interrupt Pending bit - 28 R Vector No. x3c / x5c Interrupt Pending bit - 27 R Vector No. x3b / x5b Interrupt Pending bit - 26 R Vector No. x3a / x5a Interrupt Pending bit - 25 R Vector No. x39 / x59 Interrupt Pending bit - 24 R Vector No. x38 / x58 Interrupt Pending bit - 23 R Vector No. x37 / x57 Interrupt Pending bit - 22 R Vector No. x36 / x56 Interrupt Pending bit - 21 R Vector No. x35 / x55 Interrupt Pending bit - 2 R Vector No. x34 / x54 Interrupt Pending bit - 19 R Vector No. x33 / x53 Interrupt Pending bit - 18 R Vector No. x32 / x52 Interrupt Pending bit - 17 R Vector No. x31 / x51 Interrupt Pending bit - 16 R Vector No. x3 / x5 Interrupt Pending bit - 15 R Vector No. x2f / x4f Interrupt Pending bit - 14 R Vector No. x2e / x4e Interrupt Pending bit - 13 R Vector No. x2d / x4d Interrupt Pending bit - 12 R Vector No. x2c / x4c Interrupt Pending bit - 11 R Vector No. x2b / x4b Interrupt Pending bit - 1 R Vector No. x2a / x4a Interrupt Pending bit - 9 R Vector No. x29 / x49 Interrupt Pending bit - 8 R Vector No. x28 / x48 Interrupt Pending bit - 7 R Vector No. x27 / x47 Interrupt Pending bit - 6 R Vector No. x26 / x46 Interrupt Pending bit - 5 R Vector No. x25 / x45 Interrupt Pending bit - 4 R Vector No. x24 / x44 Interrupt Pending bit - 3 R Vector No. x23 / x43 Interrupt Pending bit - 2 R Vector No. x22 / x42 Interrupt Pending bit - 1 R Vector No. x21 / x41 Interrupt Pending bit - R Vector No. x2 / x4 Interrupt Pending bit - *** Interrupt Pending Register 의각비트의값은해당인터럽트가발생하였음을나타낸다. Interrupt Pending Register 의값은 Interrupt Pending Clear 레지스터에의해 Clear 된다. 일반적으로해당 Interrupt 가끝날때 Clear 한다. Advanced Digital Chips, Inc. CONFIDENTIAL 73

Ver 1.6.7 8.3.5 Interrupt Enable Register (INTENn) Address : xffff_1 / xffff_5 31 R/W Vector No. x3f / x5f Interrupt Enable bit 3 R/W Vector No. x3e / x5e Interrupt Enable bit 29 R/W Vector No. x3d / x5d Interrupt Enable bit 28 R/W Vector No. x3c / x5c Interrupt Enable bit 27 R/W Vector No. x3b / x5b Interrupt Enable bit 26 R/W Vector No. x3a / x5a Interrupt Enable bit 25 R/W Vector No. x39 / x59 Interrupt Enable bit 24 R/W Vector No. x38 / x58 Interrupt Enable bit 23 R/W Vector No. x37 / x57 Interrupt Enable bit 22 R/W Vector No. x36 / x56 Interrupt Enable bit 21 R/W Vector No. x35 / x55 Interrupt Enable bit 2 R/W Vector No. x34 / x54 Interrupt Enable bit 19 R/W Vector No. x33 / x53 Interrupt Enable bit 18 R/W Vector No. x32 / x52 Interrupt Enable bit 17 R/W Vector No. x31 / x51 Interrupt Enable bit 16 R/W Vector No. x3 / x5 Interrupt Enable bit 15 R/W Vector No. x2f / x4f Interrupt Enable bit 14 R/W Vector No. x2e / x4e Interrupt Enable bit 13 R/W Vector No. x2d / x4d Interrupt Enable bit 12 R/W Vector No. x2c / x4c Interrupt Enable bit 11 R/W Vector No. x2b / x4b Interrupt Enable bit 1 R/W Vector No. x2a / x4a Interrupt Enable bit 9 R/W Vector No. x29 / x49 Interrupt Enable bit 8 R/W Vector No. x28 / x48 Interrupt Enable bit 7 R/W Vector No. x27 / x47 Interrupt Enable bit 6 R/W Vector No. x26 / x46 Interrupt Enable bit 5 R/W Vector No. x25 / x45 Interrupt Enable bit 4 R/W Vector No. x24 / x44 Interrupt Enable bit 3 R/W Vector No. x23 / x43 Interrupt Enable bit 2 R/W Vector No. x22 / x42 Interrupt Enable bit 1 R/W Vector No. x21 / x41 Interrupt Enable bit R/W Vector No. x2 / x4 Interrupt Enable bit *** Interrupt Enable bit : Interrupt Disable and Pending Clear 1 : Interrupt Enable 74 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 8.3.6 Interrupt Mask Status Register (INTMASKn) Address : xffff_14 / xffff_54 31 : R Interrupt Mask Status Register x_ *** 모든 Mask bit 의상태를확인할수있다. 8.3.7 Interrupt Mask Set Register (INTMASKSETn) Address : xffff_14h / xffff_54 31 W Vector No. x3f / x5f Interrupt Request Set bit 3 W Vector No. x3e / x5e Interrupt Request Set bit 29 W Vector No. x3d / x5d Interrupt Request Set bit 28 W Vector No. x3c / x5c Interrupt Request Set bit 27 W Vector No. x3b / x5b Interrupt Request Set bit 26 W Vector No. x3a / x5a Interrupt Request Set bit 25 W Vector No. x39 / x59 Interrupt Request Set bit 24 W Vector No. x38 / x58 Interrupt Request Set bit 23 W Vector No. x37 / x58 Interrupt Request Set bit 22 W Vector No. x36 / x56 Interrupt Request Set bit 21 W Vector No. x35 / x55 Interrupt Request Set bit 2 W Vector No. x34 / x54 Interrupt Request Set bit 19 W Vector No. x33 / x53 Interrupt Request Set bit 18 W Vector No. x32 / x52 Interrupt Request Set bit 17 W Vector No. x31 / x51 Interrupt Request Set bit 16 W Vector No. x3 / x5 Interrupt Request Set bit 15 W Vector No. x2f / x4f Interrupt Request Set bit 14 W Vector No. x2e / x4e Interrupt Request Set bit 13 W Vector No. x2d / x4d Interrupt Request Set bit 12 W Vector No. x2c / x4c Interrupt Request Set bit 11 W Vector No. x2b / x4b Interrupt Request Set bit 1 W Vector No. x2a / x4a Interrupt Request Set bit 9 W Vector No. x29 / x49 Interrupt Request Set bit 8 W Vector No. x28 / x48 Interrupt Request Set bit 7 W Vector No. x27 / x47 Interrupt Request Set bit 6 W Vector No. x26 / x46 Interrupt Request Set bit 5 W Vector No. x25 / x45 Interrupt Request Set bit 4 W Vector No. x24 / x44 Interrupt Request Set bit 3 W Vector No. x23 / x43 Interrupt Request Set bit 2 W Vector No. x22 / x42 Interrupt Request Set bit 1 W Vector No. x21 / x41 Interrupt Request Set bit W Vector No. x2 / x4 Interrupt Request Set bit *** Interrupt Request Set bit : No Effect interrupt Mask. 1 : Pending interrupt is allowed to become active (interrupts sent to CPU). Advanced Digital Chips, Inc. CONFIDENTIAL 75

Ver 1.6.7 8.3.8 Interrupt Mask Clear Register (INTMASKCLRn) Address : xffff_18 / xffff_58 31 W Vector No. x3f / x5f Interrupt Req. Clear bit 3 W Vector No. x3e / x5e Interrupt Req. Clear bit 29 W Vector No. x3d / x5d Interrupt Req. Clear bit 28 W Vector No. x3c / x5c Interrupt Req. Clear bit 27 W Vector No. x3b / x5b Interrupt Req. Clear bit 26 W Vector No. x3a / x5a Interrupt Req. Clear bit 25 W Vector No. x39 / x59 Interrupt Req. Clear bit 24 W Vector No. x38 / x58 Interrupt Req. Clear bit 23 W Vector No. x37 / x57 Interrupt Req. Clear bit 22 W Vector No. x36 / x56 Interrupt Req. Clear bit 21 W Vector No. x35 / x55 Interrupt Req. Clear bit 2 W Vector No. x34 / x54 Interrupt Req. Clear bit 19 W Vector No. x33 / x53 Interrupt Req. Clear bit 18 W Vector No. x32 / x52 Interrupt Req. Clear bit 17 W Vector No. x31 / x51 Interrupt Req. Clear bit 16 W Vector No. x3 / x5 Interrupt Req. Clear bit 15 W Vector No. x2f / x4f Interrupt Req. Clear bit 14 W Vector No. x2e / x4e Interrupt Req. Clear bit 13 W Vector No. x2d / x4d Interrupt Req. Clear bit 12 W Vector No. x2c / x4c Interrupt Req. Clear bit 11 W Vector No. x2b / x4b Interrupt Req. Clear bit 1 W Vector No. x2a / x4a Interrupt Req. Clear bit 9 W Vector No. x29 / x49 Interrupt Req. Clear bit 8 W Vector No. x28 / x48 Interrupt Req. Clear bit 7 W Vector No. x27 / x47 Interrupt Req. Clear bit 6 W Vector No. x26 / x46 Interrupt Req. Clear bit 5 W Vector No. x25 / x45 Interrupt Req. Clear bit 4 W Vector No. x24 / x44 Interrupt Req. Clear bit 3 W Vector No. x23 / x43 Interrupt Req. Clear bit 2 W Vector No. x22 / x42 Interrupt Req. Clear bit 1 W Vector No. x21 / x41 Interrupt Req. Clear bit W Vector No. x2 / x4 Interrupt Req. Clear bit *** Interrupt Request Clear bit : No Effect Interrupt Mask. 1 : Pending interrupt is masked from becoming active (interrupts not sent to CPU). 76 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 8.3.9 Programmable Interrupt Priority Enable Register (PIPENR) Address : xffff_1c 31 : 1 R Reserved - R/W Programmable Priority Enable bit : Programmable Priority Disable 1 : Programmable Priority Enable 8.3.1 Interrupt Priority Vector n Register (IPVRn) Address : xffff_2 / xffff_24 / xffff_28 / xffff_2c / xffff_3 / xffff_34 / xffff_38 / xffff_3c 31 : 28 R/W 8 th Priority Interrupt Number x7 27 : 24 R/W 7 th Priority Interrupt Number x6 23 : 2 R/W 6 th Priority Interrupt Number x5 19 : 16 R/W 5 th Priority Interrupt Number x4 15 : 12 R/W 4 th Priority Interrupt Number x3 11 : 8 R/W 3 rd Priority Interrupt Number x2 7 : 4 R/W 2 nd Priority Interrupt Number x1 3 : RW 1 st Priority Interrupt Number x * 우선순위는 8 개의인터럽트를하나의그룹으로하여, 그룹내에서우선순위를변경하는것이가능하다. Advanced Digital Chips, Inc. CONFIDENTIAL 77

Ver 1.6.7 9 DMA 9.1 Features - AMBA AHB Specificaiton 과호환. - 8 채널지원. 각채널별로 DMA 전송이가능하다 - 16 포트 DMA Request 지원. DMAC 는 Peripheral 을위한 16 포트의 DMA Request 신호를제공하고있다. - Single Request 와 Burst Request 신호를제공. Peripheral 에게제공되는 DMA Request 신호는 Single Request 와 Burst Request 신호두종류를제공하며두가지모두사용할수있다. - 4 가지 DMA 전송지원. memory-to-memory, Memory-to-peripheral, peripheral-to-memory peripheral-toperipheral 전송을지원한다. - Auto Reload 기능을이용한 Scatter 와 Gather 기능을지원한다. - Linked list 를이용한 Scatter 와 Gather 기능을지원한다. - 채널별 Priority 는하드웨어로고정되어있다. 채널 가가장높은 Priority 를갖고채널 7 이가장낮은 Priority 를갖게된다. - 2 개의 AHB Master 를내장하여 Multi Layer AHB Bus 를지원하고있다. - Programmable Burst Size 를제공하고있다. 사용자는 DMA 전송의효율성을높이기위하여 Burst Size 를설정한다. Burst Size 는 Peripheral 안에있는 FIFO 크기의절반으로설정하는것이일반적이다. - 각채널별로 4 Word FIFO 를내장하고있다. - 각채널별로분리된 DMA Error Interrupt 와 DMA Terminal Count Interrupt( 전송종료인터럽트 ) 를가지고있다. - Interrupt Enable 비트지원. DMA Error Interrupt 와 DMA Terminal Count Interrupt( 전송종료인터럽트 ) 에대한 Enable 비트를가지고있다. 78 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 9.2 Block Description DMA Controller AHB Bus Signals AHB Slave Interface Channel N AHB Master Interface AHB Bus Signals DMA_INT Arbiter DMABREQ[15:] DMASREQ[15:] DMALBREQ[15:] DMALSREQ[15:] DMACLR[15:] DMATC[15:] Peripheral Interface 4 Word FIFO AHB Master Interface 1 AHB Bus 1 Signals Figure 9-1 DMA Block Diagram DMA 는 8 개의채널을가지고있다. 각채널은 Source Peripheral 에서 Destination Peripheral 로전송되는단방향의데이터흐름을제어하며내부에 4x4 byte FIFO 를내장하고있다. AHB Master Interface 는채널로부터들어오는데이터의전송요청을받아서 AHB Bus 에서데이터전송을수행하는역할을한다. 내부에 2 개의 AHB Master Interface 가내장되어있어서로다른버스에연결할수있다. 그래서 Source Peripheral 과 Destination Peripheral 이다른버스에연결되어있더라도둘사이의데이터전송이가능하다. Arbiter 는각채널에서발생하는데이터전송요청을우선순위에따라 AHB Master Interface 또는 AHB Master Interface1 에전달하며어느 AHB Master Interface 를사용할지는요청되는데이터의 Address 에의해결정된다. AHB Slave Interface 는채널마다할당되어있는레지스터등을설정하고인터럽트를요청하는역할을한다. Peripheral Interface 는 Peripheral 들이요청하는 DMA Request 신호를받아서각채널의 Peripheral Selection 비트에의해선택된신호를해당채널로전달하게된다. 최대 16 개의 DMA Request 신호를받을수있으며채널입장에서는 Source DMA Request 신호와 Destination DMA Request 신호로구분하여 2 개의 DMA Request 신호를받을수있다 Advanced Digital Chips, Inc. CONFIDENTIAL 79

Ver 1.6.7 9.3 Function Description 9.3.1 DMA Operation - Transfer Hierarchy DMA 전송은그림 2 와같은 3 단계의계층구조를갖는다. 최상위단계의전송을 DMA Transfer 라정의한다. DMA Transfer 전송은 DMA 가전송하는전체데이터의양을의미하며 Control 레지스터에있는 Transfer Size 로전송량을결정하게된다. 차상위단계전송을 Burst Transaction 으로정의한다. Burst Transaction 에서전송하는데이터의양은 Control 레지스터에있는 Burst Size 로설정하게되며보통 Peripheral 들의 FIFO 크기에맞추어설정한다. 일반적인 Peripheral 들은메모리처럼필요한모든데이터를한번에전송하지못하므로 Peripheral 내부의 FIFO 단위로쪼개서전송하게된다. 한가지주의할사항은여기서설정하는 Burst size 가 AMBA Burst transfer 의 burst size 가아니라는점이다. 최하위단계전송은 AMBA Burst Transfer 이다. Burst Transaction 은 AMBA Burst Transfer 단위로나뉘어진다. 이단계의전송에서사용자가설정하는부분은없으며하드웨어적으로관리된다. 사용자는 Burst Size 보다적은 Transfer Size 값을설정하는것이가능하다. 이러한경우 Burst Transaction 은설정된 Transfer size 양만전송되며 DMA 전송이종료된다. Transfer Size 로전송량조정 DMA Transfer Burst Size 로전송량조정 Burst Transaction Burst Transaction Burst Transaction Single Transaction AMBA Burst Transfer AMBA Burst Transfer AMBA Burst Transfer AMBA Single Transfer Figure 9-2 DMA Transfer hierarchy - Transfer type 사용자는 DMA 설정에서데이터전송의종류 (Transfer type) 를지정해야한다. Transfer Type 은아래의 4 가지중에하나가된다. 1. Memory to Memory 2. Memory to Peripheral 3. Peripheral to Memory 4. Source Peripheral to Destination Peripheral 8 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 Memory to Memory 의의미는 Source Address 가 Memory 이고 Destination Address 도 Memory 로지정한경우를말한다. Memory to Peripheral 의의미는 Source Address 는 Memory 이고 Destination Address 는 Peripheral 로지정한경우이다. 즉메모리에있는데이터를 Peripheral 의버퍼등으로옮기는것을뜻한다. 이렇게사용자가 Transfer Type 을지정하는이유는 handshake 과정이필요한지아닌지를 DMA 에게알려주기위함이다. DMA 는메모리가아닌 Peripheral 과의데이터전송을수행할때에는 Handshake 방식으로진행한다. 메모리가아닌 Peripheral 들은데이터전송을위한준비과정과시간이필요하며데이터전송량도한정되어있다. Handshake 방식은 Peripheral 이데이터가준비되었을때만 DMAC 가데이터를전송하도록유도하므로필요한방식이다. 하지만 Peripheral 이메모리인경우는언제든 Access 가가능하므로이러한 handshake 과정은필요하지않다. 따라서사용자는 Transfer type 을지정하여 Peripheral 과의데이터전송에서 handshake 방식이필요한지아닌지를알려주어야한다. - Flow Controller Flow controller 란 DMA 전송량을결정하는모듈을말한다. Flow Controller 는 DMAC 또는 Peripheral 중에하나로정해진다. 만약 DMAC 가 Flow controller 가되면 DMA 전송량은 Transfer Size 에설정된값으로결정된다. 또한 Peripheral 이 Flow Controller 역할을할수있다. 이러한경우 DMAC 는 Peripheral 의 Request 신호에맞추어데이터를전송하게하게되며 Transfer size 에설정된값들은무시된다. DMA 전송을종료하기위해서는마지막데이터를요구할때 Last Request 신호를보내면된다. DMAC 가 Last Request 신호를받게되면마지막요청에대한데이터전송을수행한후에 DMA 전송이종료된다. 9.3.2 Linked List Operation - LLI LLI(Linked List Item) 는 DMA 전송을위해필요한기본적인정보들을담고있는배열이다. LLI 가담고있는내용은 Source Address, Destination Address, Next LLI Address, Control 정보이렇게 4 가지이다. Linked List Operation 은 DMAC 가첫번째 LLI 를읽어서내부레지스터들을갱신한후 DMA 전송을수행하고종료되면 Next LLI 주소를통해다음번 LLI 를읽어들이는방식으로동작한다. 아래의그림은 LLI 의구조를설명하는그림이다. Advanced Digital Chips, Inc. CONFIDENTIAL 81

Ver 1.6.7 x1 x14 x18 x1c Source Address Destination Address Next LLI Address (x2) Control 1st LLI x2 x24 x28 x2c Source Address Destination Address Next LLI Address(x3) Control 2nd LLI x3 x34 x38 x3c Source Address Destination Address Next LLI Address (x) Control Figure 9-3 Linked list Last LLI 마지막 LLI 는항상 Next LLI Address 에 x 을쓰도록약속되어있다. DMAC 는 Next LLI Address 가 x 임을확인하면현재읽은 LLI 가마지막임을알게된다. 그러므로 LLI 가실제주소 x 에놓이면수행되지않으므로주의해야한다. - Multi Block Transfer LLI 로기술되어있는데이터를전송하는경우를 Multi Block Transfer 라고부르기도한다. 즉하나의 LLI 가전송하는데이터를 Block 이라고정의하며 LLI 의개수는 Block 의개수가된다. 또한 Block 사이즈는각각의 LLI 에포함된 Control 레지스터의 Transfer Size 로정의된다. 아래의그림은 Multi Block Transfer 에대한계층구조를보여주고있다. Transfer Size 로전송량조정 DMA Transfer Block Block Block Burst Size 로전송량조정 Burst Transaction Burst Transaction Burst Transaction Single Transaction AMBA Burst Transfer AMBA Burst Transfer AMBA Burst Transfer AMBA Burst Transfer AMBA Single Transfer Figure 9-4 Multi Block Transfer - Scatter & Gather with Liked list Scatter 는한덩어리로모여있는데이터를 DMA 전송을통하여분산시키는것을의미하며 82 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 Gather 는그반대의의미로써흩어져있는데이터를한군데로모으는것을말한다. LLI 를이용하면 Scatter 와 Gather 기능을수행할수있다. 아래의그림은 LLI 를사용하여 Gather 기능을수행하는예를보여준다. 예제의 LLI 의내용은그림처럼사각형형태로저장된데이터를 Peripheral 로옮기는 Gather 작업을수행하고있다. LLI 의위치는 x2 에서시작한다. Figure 9-5 Gathering by using LLI 첫번째 LLI 내용 Source Address: xa2 Destination Address: Peripheral Address Source and Destination transfer width: 8bit Source and Destination burst Size: 16 burst Transfer Size: 372 byte, xc Next LLI Address: x21 두번째 LLI 내용 Source Address: xb2 Destination Address : Peripheral Address Source and Destination transfer width: 8bit Source and Destination burst Size: 16 burst Transfer Size: 372 byte, xc Next LLI Address: x22... 마지막 LLI 내용 Source Address: x112 Destination Address: Peripheral Address Source and Destination transfer width: 8bit Source and Destination burst Size: 16 burst Transfer Size: 372 byte, xc Next LLI Address: x Advanced Digital Chips, Inc. CONFIDENTIAL 83

Ver 1.6.7 9.3.3 Auto Reload Operation Auto Reload Operation 의기본동작은 DMA 전송이완료되었을때 Control 레지스터를다시 Reload 하여 DMA 전송을반복하는것이다. 반복회수는 Auto Reload count 레지스터값으로정하게된다. Auto Reload 가 1 회발생할때 Auto Reload Count 값이 1 씩감소하며 이되면 Auto Reload 는발생하지않는다. Auto Reload Operation 은별도의모드설정이없으며 DMA 전송이완료되었을때 Auto Reload Count 레지스터가 이아니면 Auto Reload 를수행하는방식이다. - Transfer Hierarchy Auto Reload Operation 은 Linked List Operation 처럼 Multi Block Transfer 로분류된다. Block 의개수는 Auto Reload count + 1 이되고 Block 의데이터전송량은 Transfer size 로설정된다. Transfer Size 로전송량조정 DMA Transfer Block Block Block Burst Size 로전송량조정 Burst Transaction Burst Transaction Burst Transaction Single Transaction AMBA Burst Transfer AMBA Burst Transfer AMBA Burst Transfer AMBA Burst Transfer AMBA Single Transfer Figure 9-6 Auto Reload Operation Transfer Hierarchy - Scatter with Auto reload 아래의그림은 Auto Reload Operation 을통하여 Scatter 기능을보여주는예제이다. Destination Scatter Address 는 Block 전송이완료될때마다 Destination Block 의시작주소를일정간격으로띄우는역할을한다. 사용자는이레지스터를통하여 Destination Block 간의간격을둠으로써 Scatter 기능을구현하게된다. 84 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 xa Source Data xb Destination Data Block Block xa1 Block 1 xb12 Dest Scatter Addr = x2 xa2 Block 1 Block 2 xb24 Dest Scatter Addr = x2 Block 2 Figure 9-7 Scatter with Auto Reload Operation 레지스터설정 Source Address: xa Destination Address: xb Source and Destination transfer width: 32bit Source and Destination burst Size: 4 burst Transfer Size: x4 Auto Reload Count: 2 Destination scatter Address: x2 - Gather with Auto reload 아래의그림은 Auto Reload Operation 을사용한 Gather 기능을보여주는예제이다. Source Gather Address 는블록전송이완료될때마다 Source 블록의시작주소를일정간격으로띄우는역할을한다. 사용자는이레지스터를통하여 Source Block 간의간격을둠으로써 Gather 기능을구현하게된다. Advanced Digital Chips, Inc. CONFIDENTIAL 85

Ver 1.6.7 xa Source Data Destination Data xb Block Block Source Gather Addr = x5 xb1 xa15 Block 1 Block 1 xb2 xa3 Source Gather Addr = x5 Block 2 Block 2 Figure 9-8 Gather with Auto Reload Operation 레지스터설정 Source Address: xa Destination Address: xb Source and Destination transfer width: 32bit Source and Destination burst Size: 4 burst Transfer Size: x4 Auto Reload Count: 2 Source gather Address: x5 9.3.4 Peripheral Interface - Hand Shake Signals DMA Request 신호와 DMA Clear 신호는 DMA 가메모리가아닌 Peripheral 과의데이터전송에서 Handshake 방식으로데이터를전송하는데사용하는신호이다. DMA Request 신호는 Peripheral 이 DMAC 에게데이터전송을요청할때사용하는신호이며 4 가지가있다. ( 아래의그림참조 ) Peripheral 은이중하나를선택하여 Request 를하며동시에여러개를 Request 하는것은허용하지않는다. DMA Clear 신호는 DMA Request 신호에대한응답으로 DMAC 가 Peripheral 에보내는신호이다. 86 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 Figure 9-9 DMA Handshake Signals - DMABREQ Burst Request 신호. 이신호가 Active 되면 DMAC 에의해 Burst Transaction 이발생하며전송되는데이터의양은 Burst Size 에서정해진다. - DMASREQ Single Request 신호. 이신호는 Active 되면 DMAC 에의해 Single Transaction 이발생한다. - DMALBREQ Last Burst Request 신호. Peripheral 이 Flow Control을역할을하도록설정하였을때마지막 DMA Burst Request 신호임을알리는신호이다. DMALBREQ 신호가 Active 되면마지막 Burst Transaction이발생하고 DMA 전송이종료된다. - DMALSREQ Last Single Request 신호. Peripheral 이 Flow Control을역할을하도록설정하였을때마지막 DMA Single Request 신호임을알리는신호이다. DMALSREQ 신호가 Active 되면마지막 Single Transaction이발생하고 DMA 전송이종료된다. - DMACLR DMA Clear 신호. Peripheral 이요청하는 4 가지 Request 신호를 inactive 시키는신호이다. - Time diagram of DMA Request Peripheral 이 Request 를보내면 DMAC 는 Program 된 Burst Size 만큼데이터를전송한후에 DMA Clear 신호를보내게된다. 이때모든전송이종료된경우에는 DMATC(DMA Terminal Count: DMA 전송종료 ) 신호도동시에 Active 된다. 이신호를통하여 Peripheral 은 DMA 전송이종료되었는지체크할수있다. Peripheral 이 DMA Clear (DMACLR) 신호를받게되면 DMA Request 신호를 Inactive 상태로만들게된다. 만약 DMA Clear 신호가오기전에 Peripheral 스스로 DMA Request 신호를 Inactive 상태로만들면문제가발생하게된다. 또한 Next DMA Request 신호를보낼때에는현재 DMA Clear 신호가 Inactive 상태일때만가능하다. Advanced Digital Chips, Inc. CONFIDENTIAL 87

Ver 1.6.7 Figure 9-1 Time Diagram of DMA Request 88 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 9.4 Register Description 9.4.1 DMA Interrupt Status ( DMAIntStatus ) Address: 8_14 31 : 8 R Reserved 7 : R Interrupt Status of Channel 각채널에서발생할수있는 Interupt 의발생유무를알려준다. ex) 번비트가 set 인경우 번채널인터럽트발생 1 번비트가 set 인경우 1 번채널인터럽트발생 인터럽트는 2 종류가있으므로 DMATCIS 와 DMATCIC 를읽어서인터럽트의종류를확인해야한다. 9.4.2 DMA Terminal Count Interrupt Status ( DMATCIntStatus ) Address: 8_144 31 : 8 R Reserved 7 : R Terminal Count Interrupt Status of Channel 각채널의 Terminal Count 인터럽트발생유무를알려준다. 9.4.3 DMA Terminal Count Interrupt Clear ( DMATCIntClr ) Address: 8_148 31 : 8 R Reserved 7 : W Terminal Count Interrupt Clear 각비트는해당채널의 Terminal count 인터럽트를 Clear 하는역할을한다. Set 하게되면해당채널의인터럽트가 Clear 된다. 9.4.4 DMA Error Interrupt Status ( DMAErrorIntStatus ) Address: 8_14C 31 : 8 R Reserved 7 : R Error Interrupt Status of Channel 각채널의 DMA 전송에러인터럽트에대한발생유무를알려준다. Advanced Digital Chips, Inc. CONFIDENTIAL 89

Ver 1.6.7 9.4.5 DMA Error Interrupt Clear ( DMAErrorIntClr ) Address: 8_141 31 : 8 R Reserved 7 : W Error Interrupt Clear 각비트는해당채널의 DMA 전송에러인터럽트를 Clear 하는역할을한다. Set 하게되면해당채널의인터럽트가 Clear 된다. 9.4.6 DMA Block Interrupt Status ( DMABlockIntStatus ) Address: 8_1414 31 : 8 R Reserved 7 : R Block Interrupt Status of Channel 각채널의 DMA Block 인터럽트에대한발생유무를알려준다. 9.4.7 DMA Block Interrupt Clear ( DMABlockIntClr ) Address: 8_1418 31 : 8 R Reserved 7 : W Block Interrupt Clear 각비트는해당채널의 DMA Block 인터럽트를 Clear 하는역할을한다. Set 하게되면해당채널의인터럽트가 Clear 된다. 9.4.8 DMA Raw Terminal Count Interrupt Status ( DMARawTCIntStatus ) Address: 8_141C 31 : 8 R Reserved 7 : R Raw Terminal Count Interrupt Status of Channel Interrupt Enable 비트로 Disable 된각채널의 Terminal Count 인터럽트가발생되었는지를알려준다. 9.4.9 DMA Raw Error Interrupt Status ( DMARawErrorIntStatus ) Address: 8_142 31 : 8 R Reserved 7 : R Error Interrupt Status of Channel Interrupt Enable 비트로 Disable 된각채널의에러인터럽트에대한발생유무를알려준다. 9 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 9.4.1 DMA Enabled Channel Status ( DMAEnbldChn ) Address: 8_1424 31 : 8 R Reserved 7 : R Enabled Channel Status 각비트는해당채널의 DMA 가 Enable 되어있는지를알려준다. 9.4.11 DMA Software Burst Request ( DMASoftBReq ) Address: 8_1428 31 : 16 R Reserved 15 : RW Software Burst Request 소프트웨어적으로 DMA Burst Request 신호를생성하는레지스터이다. 해당비트에 1을쓰게되면 DMA Burst Request 신호가생성되면 Clear는자동으로이루어진다. 9.4.12 DMA Software Single Request ( DMASoftSReq ) Address: 8_142C 31 : 16 R Reserved 15 : RW Software Single Request 소프트웨어적으로 DMA Single Request 신호를생성하는레지스터이다. 해당비트에 1을쓰게되면 DMA Burst Request 신호가생성되면 Clear는자동으로이루어진다. 9.4.13 DMA Software Last Burst Request ( DMASoftLBReq ) Address: 8_143 31 : 16 R Reserved 15 : RW Software Last Burst Request 소프트웨어적으로 DMA Single Request 신호를생성하는레지스터이다. 해당비트에 1을쓰게되면 DMA Burst Request 신호가생성되면 Clear는자동으로이루어진다. Advanced Digital Chips, Inc. CONFIDENTIAL 91

Ver 1.6.7 9.4.14 DMA Software Last Single Request ( DMASoftLSReq ) Address: 8_1434 31 : 16 R Reserved 15 : RW Software Last Single Request 소프트웨어적으로 DMA Last Single Request 신호를생성하는레지스터이다. 해당비트에 1을쓰게되면 DMA Last Single Request 신호가생성되면 Clear는자동으로이루어진다. 9.4.15 Channel Source Address Register ( ChnSrcAddr ) Address: 8_15 / 8_152 / 8_154 / 8_156 8_158 / 8_15A / 8_15C / 8_15E 31 : RW Source Address 각채널의 Source Address를설정하는레지스터이다. 또한설정된값은 Source transfer Width에따라 Align이맞아야한다. Source Address는채널에서데이터전송이진행됨에따라자동으로증가한다. 그래서이레지스터는언제나앞으로전송해야할데이터의 Address를지시하고있게된다. 하지만해당채널이동작중인상태에서이값을읽는것은의미가없다. 왜냐하면프로그램이 Read 하는순간에도채널은계속진행하고있기때문이다. 다만해당채널이종료된후이레지스터를체크하면읽어야할데이터가모두읽었는지는확인해볼수있다. 9.4.16 Channel Destination Address Register ( ChnDstAddr ) Address: 8_154 / 8_1524 / 8_1544 / 8_1564 8_1584 / 8_15A4 / 8_15C4 / 8_15E4 31 : RW Destination Address 각 DMA 채널의 Destination Address를설정하는레지스터이다. 또한설정된값은 Destination transfer Width에따라 Align이맞아야한다. Destination Address는채널에서데이터전송이진행됨에따라자동으로증가한다. 그래서이레지스터는언제나앞으로전송되는데이터가저장되는주소를지시하고있게된다. 하지만채널이동작중인상태에서이값을읽는것은의미가없다. 왜냐하면프로그램이 Read 하는순간해당채널은계속진행되고있기때문이다. 다만채널이종료된후이레지스터를체크하면읽어야할데이터가모두읽었는지는확인해볼수있다. 92 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 9.4.17 Channel Linked List Item Register ( ChnLLI ) Address: 8_158 / 8_1528 / 8_1548 / 8_1568 8_1588 / 8_15A8 / 8_15C8 / 8_15E8 31 : 2 RW Linked List Item Address 각 DMA 채널의첫번째 Linked List Item 이위치한 곳의시작주소를지정하는레지스터이다. 이레지스 터가 x이아닌값으로설정되고채널이 Enable 되 면 DMAC는이주소에위치한첫번째 Linked List Item을 Load 하여 내부 레지스터들을 갱신하고 Linked List Operation을수행한다. Default Value는 Linked List Operation이수행하지않는다. 1 : R Reserved 9.4.18 Channel Control Register ( ChnCntl ) Address: 8_15C / 8_152C / 8_154C / 8_156C 8_158C / 8_15AC / 8_15CC / 8_15EC 31 : 3 R Reserved - 29 RW Destination Increment 설정되면 Destination 어드레스가데이터전송에따라자동으로증가한다 28 RW Source Increment 설정하게되면 Source 어드레스가데이터전송에따라자동으로증가한다. 26 : 24 RW Destination transfer width : 8bit 1 : Reserved 1 : 16bit 11 : Reserved 1 : 32bit 11 : Reserved 11 : Reserved 111 : Reserved Destination 측 data width를설정하는비트이다. Source transfer width와다르게설정하는것이가능하다. 만약 Destination transfer width < Source tranfer width 인경우 Transfer size 설정에주의한다. (Program Consideration 참조 ) 23 R Reserved 22 : 2 RW Source transfer width : 8bit 1 : Reserved 1 : 16bit 11 : Reserved 1 : 32bit 11 : Reserved 11 : Reserved 111 : Reserved Source 에서전송하는 data width 를설정하는비트이다. Advanced Digital Chips, Inc. CONFIDENTIAL 93

Ver 1.6.7 19 R Reserved 18 : 16 RW Destination burst size : 1 1 : 32 1 : 4 11 : 64 1 : 8 11 : 128 11 : 16 111 : 256 Destination 측 Peripheral 에서수행하는 Burst Transaction 의크기를지정한다. AHB Burst Size와유사하나그것을포함하는상위레벨의 Transaction이다. (Transfer Hierarchy 참조 ) Destination이 Memory인경우에도동일한 Burst size 로접근한다. 15 R Reserved 14 : 12 RW Source burst size : 1 1 : 32 1 : 4 11 : 64 1 : 8 11 : 128 11 : 16 111 : 256 Source측 Peripheral에서수행하는 Burst Transaction의크기를지정한다 AHB Burst Size와유사하나그것을포함하는상위레벨의 Transaction이다. (Transfer Hierarchy 참조 ) Source가 Memory인경우에도동일한 Burst Size로접근한다. 11 : RW Transfer Size DMAC 가 Flow Control 역할을할때 DMA 채널이전송하는데이터의전체양을의미한다. 전송단위는 Byte 가아니고 Source Transfer Width 가된다. 즉전체전송량을계산식은다음과같다 (Transfer size) x (source transfer width) 이값은사용자가설정한값에서데이터전송이수행될때마다 1 씩줄어들게되고 이되면 DMA 전송이종료된다. 따라서 DMA 전송중에이값을읽게되면앞으로전송종료까지남은데이터의양을확인할수있다. DMAC 가 Flow Controller 가아닌경우이값은무시되지만 Program 에서는이값을 으로설정해야한다. 94 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 9.4.19 Channel Configuration Register ( ChnCfg ) Address: 8_151 / 8_153 / 8_155 / 8_157 8_159 / 8_15B / 8_15D / 8_15F 31 : 22 R Reserved 21 RO FIFO Active - : 해당채널의 FIFO 내에데이터가비어있음 1 : 해당채널의 FIFO 내에데이터가남아있음 2 RW Halt : enable DMA request 1 : ignore DMA request. 사용자는이비트를사용하여 FIFO에아무런데이터도남기지않고깨끗하게 DMA 채널을 Disable 할수있다. 19 RW Lock 이비트를설정하면 Locked transfer를수행하게된다. 18 RW Block Interrupt Enable Multi Block Transfer 전송에서 Block 전송을끝냈을때발생하는인터럽트에대한 Enable 비트이다. Block Interrupt 가발생하면 DMA는 Block Interrupt가 Clear 될때까지 Next Block 전송을진행하지않는다. 17 RW Terminal count interrupt Enable DMA 전송종료인터럽트에대한 Enable 비트이다. 16 RW Interrupt error Enable DMA Error 인터럽트에대한 Enable 비트이다. 15 R Reserved 14 : 12 RW Flow Control Value Transfer type Flow controller Memory-to-Memory (Default) DMA 1 Memory-to-Peripheral DMA 1 Peripheral-to-Memory DMA 11 Source peripheral-to-destination peripheral DMA 1 Source peripheral-to-destination peripheral Dst. Peri. 11 Memory-to-Peripheral Peripheral 11 Peripheral-to-Memory Peripheral 111 Source peripheral-to-destination peripheral Src. Peri. 이값은 Transfer type과 Flow Controller를결정한다. 11 : 8 RW Destination Peripheral 16 개의 DMA Request 중하나를선택하는비트이다. : NAND Flash TX 1: SDHC 1: Reserved 11: Reserved 1: USB Device Bulk In 11: Mixer Play CH 11: Mixer Play CH1 111: Mixer Play CH2 1: Mixer Play CH3 11: Reserved 111: Reserved 1111: Reserved 7 : 4 RW Source Peripheral 16 개의 DMA Request 중하나를선택하는비트이다. Advanced Digital Chips, Inc. CONFIDENTIAL 95

Ver 1.6.7 : Reserved 1: SDHC 1: NAND Flash RX 11: USB Device Bulk Out 1: Reserved 11: Reserved 11: Reserved 111: Reserved 1: Reserved 11: Mixer Record 11: ADC 111: Reserved 1111: Reserved 3 : 1 R Reserved RW Channel Enable 채널을활성화시키는비트이다. 사용자가 DMA 전송을시작하기위해이비트를 Set 하게되면설정한대로데이터전송이시작되고모든전송이완료되면자동으로 Clear 된다. Auto Clear 조건은다음과같다. 1. 일반 DMA 전송의완료 2. Linked List Operation 완료 3. Auto Reload Operation 완료 4. Error 발생에의한종료 사용자는활성화되어있는채널을강제로종료할수도있다. 강제종료는 Enable 비트를 clear 하면된다. 하지만채널 FIFO 에남아있는데이터는사라지게된다. 9.4.2 Channel Source Gather Address Register ( ChnSrcGaAddr ) Address: 8_1514 / 8_1534 / 8_1554 / 8_1574 8_1594 / 8_15B4 / 8_15D4 / 8_15F4 31 : 16 R Reserved - 16 RW Auto Reload Source Address 이비트가설정되면 Auto Reload 발생시 Source Address 가초기설정했던 Source Address로 Reload 된다. 15 : RW Source Gather Address Auto Reload 가수행될때 Source Address 에 Source Gather Address 가더해진다. 96 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 9.4.21 Channel Destination Scatter Address Register ( ChnDstScaAddr ) Address: 8_1518 / 8_1538 / 8_1558 / 8_1578 8_1598 / 8_15B8 / 8_15D8 / 8_15F8 31 : 16 R Reserved - 16 RW Auto Reload Destination Address Auto Reload가수행될때 Destination Address 가 초기설정했던값으로 Reload 된다. 15 : RW Destination Scatter Address Auto Reload 가수행될때 Destination Address 에 Destination Scatter Address 가더해진다. 9.4.22 Channel Auto Reload Count Register ( ChnAutoReloadCnt ) Address: 8_151C / 8_153C / 8_155C / 8_157C 8_159C / 8_15BC / 8_15DC / 8_15FC 31 : 22 R Reserved - 21 RW Uncountable Auto Reload 설정하게되면 Auto Reload Count의값과상관없 이 Auto Reload가무제한이루어진다. 2 : RW Auto Reload Count 사용자는이곳에 Auto Reload 회수를설정하여 DMA 전송을반복한다. Auto Reload count 는설정된값에서 Block 전송이완료되었을때 (Transfer Size 가 이되었을때 ) 1 씩줄어들며 Auto reload count 가 이되면 Auto Reload Operation 이종료된다. Advanced Digital Chips, Inc. CONFIDENTIAL 97

Ver 1.6.7 9.5 Program Guide 9.5.1 Sumary of Register Name Address Type Description DMAIntStatus x R DMA Interrupt Status DMATCIntStatus x4 R DMA Terminal Count Interrupt Status DMATCIntClr x8 W DMA Terminal Count Interrupt Clear DMAErrorIntStatus xc R DMA Error Interrupt Status DMAErrorIntClr x1 W DMA Error Interrupt Clear DMABlockIntStatus x14 R DMA Block Interrupt Status DMABlockIntClr x18 W DMA Block Interrupt Clear DMARawTCIntStatus x1c R DMA Raw Terminal Count Interrupt Status DMARawErrorIntStatus x2 W DMA Raw Error Interrupt Status DMAEnbldChns x24 R DMA Enabled Channels DMASoftBReq x28 RW DMA Software Burst Request DMASoftSReq x2c RW DMA Software Single Request DMASoftLBReq x3 RW DMA Software Last Burst Request DMASoftLSReq x34 RW DMA Software Last Single Request ChnSrcAddr x1 RW Channel Source Address ChnDestAddr x14 RW Channel Destination Address ChnLLI x18 RW Channel Linked List Item ChnCntl x1c RW Channel Control ChnCfg x11 RW Channel Configuration ChnSrcGaAddr x114 RW Channel Source Gather Address ChnDestScatAddr x118 RW Channel Destination Scatter Address ChnAutoReloadCnt x11c RW Channel Auto Reload Count 9.5.2 Programming Sequence - DMA Operation (Memory to Memory) 1. 사용할채널을선택 2. 해당채널의 Source Address 설정 (ChnSrcAddr 레지스터 ) 3. 해당채널의 Destination Address 설정 (ChnDstAddr 레지스터 ) 4. 해당채널의 Source 와 Destination의 Transfer Width 설정 (ChnCntl 레지스터 ) 5. 해당채널의 Source 와 Destination의 Burst Size 설정 (ChnCntl 레지스터 ) 6. 해당채널의 Transfer size(dma 전송량 ) 를설정 (ChnCntl 레지스터 ) 7. 해당채널을 Enable 함 (ChnCfg 레지스터 ) 8. 전송완료를확인 (DMAEnbldChns 레지스터 ) 9. 종료 - DMA Operation (Memory to Peripheral) 1. 사용할채널을선택 2. 해당채널의 Source Address 설정 (ChnSrcAddr 레지스터 ) 3. 해당채널의 Destination Address 설정, Peri의주소 (ChnDstAddr 레지스터 ) 4. 해당채널의 Source 와 Destination의 Transfer Width 설정 (ChnCntl 레지스터 ) 5. 해당채널의 Source 와 Destination의 Burst Size 설정 (ChnCntl 레지스터 ) 6. 해당채널의 Transfer size(dma 전송량 ) 를설정 (ChnCntl 레지스터 ) 98 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 7. 해당채널의 Transfer Type 지정 (ChnCfg 레지스터 ) 8. 해당채널을 Enable 함 (ChnCfg 레지스터 ) 9. 전송완료를확인 (DMAEnbldChns 레지스터 ) 1. 종료 - Linked List Operation (Memory to Memory) Linked List Item 은미리준비되어있다고가정한다. 1. 사용할채널을선택 2. 첫번째 LLI 의주소를지정 (ChnLLI 레지스터 ) 3. 해당채널을 Enable 함 (ChnCfg 레지스터 ) 4. 전송완료를확인 (DMAEnbldChns 레지스터 ) 5. 종료 - Auto Reload Operation Program (Memory to Memory) 1. 사용할채널을선택 2. 해당채널의 Source Address 설정 (ChnSrcAddr 레지스터 ) 3. 해당채널의 Destination Address 설정 (ChnDstAddr 레지스터 ) 4. 해당채널의 Source 와 Destination의 Transfer Width 설정 (ChnCntl 레지스터 ) 5. 해당채널의 Source 와 Destination의 Burst Size 설정 (ChnCntl 레지스터 ) 6. 해당채널의 DMA 전송량을지정 (ChnCntl 레지스터 ) 7. 해당채널의 Auto Reload Count 설정 (ChnAutoReloadCnt 레지스터 ) 8. 해당채널을 Enable 함 (ChnCfg 레지스터 ) 9. 전송완료를확인 (DMAEnbldChns 레지스터 ) 1. 종료 9.5.3 Program Consideration 사용자프로그램은다음과같은고려사항을반영되어야한다. 1. 채널이 Enable 된후에는채널의레지스터들을변경하지말아야한다. 채널이 Enable 되면 DMA 전송이진행중이므로전송도중레지스터값변경은문제를발생시킬수있다. 따라서사용자가채널의레지스터들을변경하기위해서는채널이 Disable 상태인지확인한후에설정해야한다. 2. Source transfer width 가 Destination transfer width 보다작은경우 DMA 전송량은 Destination transfer width 의배수가되도록설정해야한다. 왜냐하면 DMA 전송량은 Source 측에서 Read 하는데이터의양 (Source width x Transfer size) 으로계산되는데 DMA 전송량이 Destination width x N 으로되지못하면 Destination 으로 Write 하는데이터양이부족하거나남을수있기때문이다. 3. Linked List Item 은 x 번지에위치할수없다. Advanced Digital Chips, Inc. CONFIDENTIAL 99

Ver 1.6.7 1 FLASH MEMORY CONTROLLER Flash 메모리는메모리의용량제한은 16MBytes 이며, 메모리의동작속도는최대 8Mhz 까지이지만 Flash Memory Controller 는 AHB clock 을분주하여사용하므로최대시스템클럭의 2 분주로동작하게된다. 1.1 Feature - Single, Double, Quad 비트데이터전송지원 - H/W, S/W 방식에의한 Flash Erase, Flash Program 지원 - XIP(eXecute In Place) 지원 1.2 Function Description 1.2.1 Flash Mode Register (FLMOD) Flash 의동작모드를결정한다. Single, dual 그리고 quad 방식으로접근할수있다. 1.2.2 Flash Baudrate Register (FLBRT) Flash 의동작속도를결정한다. 동작 Clock 의 high pulse 와 low pulse 의폭을설정할수있다. 1.2.3 Flash Chip Select High Pulse Width Register (FLCSH) Chip select 신호의 deselect time 을결정한다. Chip select 신호가 deselect 가되면일정시간이상태를유지해야한다. Read 동작후에 read 를할경우 1ns, Erase 나 Program 동작후에 Status register 에접근할경우 5ns 를지켜줘야한다. 외부에 Flash 를연결하여사용할경우, Flash type 마다 time 값이다를수있으므로확인후적용하여야한다. 1 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 1.2.4 Flash Command Register (FLCMD) Chip Erase(C7h/6h), Power-down(B9h), Release Power-down(ABh) 등의 command 를줄수있다. Chip Erase (C7h/6h) 이 register 에 C7h 혹은 6h 를 write 하면, flash 전체가 erase 된다. Power-down (B9h) 이 register 에 B9h 를 write 하면, Flash 는 3us(tDP) 후 power-down 상태가된다. *( 주의 ) Power-down 상태가되기전에프로그램은다른메모리영역에서수행되고있어야한다. Release Power-down (ABh) 이 register 에 ABh 를 write 하면 Flash 는 3us(tRES1) 후 power-down 상태에서 stand-by 상태가된다. 1.2.5 Flash Status Register (FLSTS) Flash 의 status register 의하위 1byte 에접근하는 register 이다. 주로 write 동작의완료여부를확인하는 bit(busy) 을 check 하는용도로사용된다. 1.2.6 Flash 2nd Status Register (FLSTS2) Serial Flash Controller Serial Flash Memory Serial Flash Controller Serial Flash Memory CMD:x5 CMD:x35 R_SFSTS R_SFSTS2 7 Stutus1 7 7 Stutus2 15 8 CMD:x1 R_SFSTS2 15 Stutus1 7 Stutus2 15 8 Read 시 Write 시 Flash 의 status register 의상위 1byte 에접근하는 register 이다. Quad mode 를지원하기위해 bit1(qe) 을 set 하는용도로사용된다. 1.2.7 Flash Sector/Block Erase Address Register (FLSEA/FLBEA) Flash 를 sector 단위혹은 block 단위로 erase 할수있다. 이 register 에 erase 할 sector 나 block 의 address 를 write 하면해당영역의 erase 를수행한다. 1.2.8 Flash WIP Check Period Register (FLWCP) Flash 를 program 하거나 erase 하는등의 write 동작을수행하였을때, flash busy 상태를하드웨어적으로 check 하는주기를결정한다. 이 register 에설정된주기마다 Flash 의 status register 를자동으로 read 하여 번 bit (BUSY) 를확인한다. 이 bit 가 1 에서 이되면 write 동작이완료가된다. 1.2.9 Flash Clock Delay Register (FLCKDLY) Flash 의 read timing 을보정하기위한 register 이다. Flash 의 read clock 을설정된값에따라 delay 할수있다. Advanced Digital Chips, Inc. CONFIDENTIAL 11

Ver 1.6.7 1.3 Register Description 1.3.1 Flash Mode Register (FLMOD) Address : x8_ 31:9 R Reserved - 8 R/W Chip select control 1b 1: Chip select 신호가 H/W에의해제어 : Chip select 신호를 Low level로고정 7 R/W Bus Error Enable 1b 1: Flash에 Write 접근이일어날시, Bus Error를발생 : Flash에 Write 허용 6 R Reserved - 5 R EQIO Mode Flag (Flash 지원여부확인 ) 1: EQIO Mode : Normal Mode Command Register에 EQIO(38h) 를 write하면 Flash는 EQIO모드로전환된다. 4 R Performance Enhance Mode (Flash 지원여부확인 ) 1: Performance Enhance Mode가적용. : Normal Mode. 적용되지않음. FLPEM Register에 1을 write하여 Performance Enhance Mode를 Enable하였을경우, Quad Read 이거나 EQIO 모드일때만적용된다. 3 R/W Bus Ready Control b : Write 동작의경우, bus ready를제어. S/W가 flash의 status를확인할필요없음. 1: Write 동작후, S/W에서 flash의 status를확인하도록설정. 2 R Reserved - 1: R/W Flash Read Mode : Single Read Mode 1: Dual Read Mode 1: Quad Read Mode 11: Reserved b 12 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 1.3.2 Flash Baudrate Register (FLBRT) Address : x8_4 31:8 R Reserved - 7:4 R/W SCK High Pulse Width 111b : 1clock 1: 2clocks 1: 3clocks 111: 15clocks 1111: 16clocks 3: R/W SCK Low Pulse Width 111b : 1clock 1: 2clocks 1: 3clocks 111: 15clocks 1111: 16clocks 1.3.3 Flash Chip Select High Pulse Width Register (FLCSH) Address : x8_8 31:4 R Reserved - 3: R/W Chip Select High Pulse Width (1ns 필요 ) Fh : 1clock 1: 2clocks 1: 3clocks 111: 15clocks 1111: 16clocks 1.3.4 Flash Performance Enhance Mode Register (FLPEM) Address : x8_c 31:1 R Reserved - R/W Performance Enhance Mode 1: Enable : Disable b 1.3.5 Flash Command Register (FLCMD) Address : x8_1 31:8 R Reserved - 7: R/W Flash Command b 1.3.6 Flash Status Register (FLSTS) Address : x8_14 31:8 R Reserved - 7: R Flash Status b 1.3.7 Flash Sector Erase Address Register (FLSEA) Address : x8_18 31:24 R Reserved - 23: R/W Flash Sector Address to Erase b Advanced Digital Chips, Inc. CONFIDENTIAL 13

Ver 1.6.7 1.3.8 Flash Block Erase Address Register (FLBEA) Address : x8_1c 31:24 R Reserved - 23: R/W Flash Block Address to Erase b 1.3.9 Flash Data Register (FLDAT) Address : x8_2 31: R/W Flash Data (8, 16, 32-bit supported) b 1.3.1 Flash WIP Check Period Register (FLWCP) Address : x8_24 31: R/W Flash WIP Status Check Period FFFh 1.3.11 Flash Clock Delay Register (FLCKDLY) Address : x8_28 3: R/W Serial Flash Feed-back Clock Delay Value h 1.3.12 Flash 2 nd Status Register (FLSTS2) Address : x8_2c 15:8 W Flash 2 nd Status (Winbond only) - 7: R/W READ 시 Flash 2 nd Status (Winbond only) WRITE 시 Flash 1 nd Status (Winbond only) - 14 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 11 LOCAL MEMORY CONTROLLER 11.1 Register Description 11.1.1 SDRAM Control Register (MEMCON) Address : x8_4 31 : 16 R Reserved - 15 : 8 R Reserved - 7 : 6 R/W Row Address Line Number 11b : 11 bit 1 : 12 bit 1 : 13 bit 11 : 14 bit 5 : 4 R/W Column Address Line Number 11b : 8 bit 1 : 9 bit 1 : 1 bit 11 : 11 bit 3 R/W Timing Constraint Select ( : 1MHz 초과, 1 : b 1 MHz 이하 ) : trcd = 3 Clock, trp = 3 Clock, tras = 7 Clock, trc = 1 Clock 1 : trcd = 2 Clock, trp = 2 Clock, tras = 5 Clock, trc = 7 Clock 2 R/W CAS Latency b : 2 Clock 1 : 3 Clock 1 : R/W This bit determine data bus width : 8 bit 1 : 16 bit 1 : 32 bit 11 : Reserved 1b < Register 설명 > (1) Bit [16] : Bank 2 에대하여사용하는 Memory 종류를선택한다. (2) Bit [7:6] : SDRAM 의 Row Address 수를선택한다. (3) Bit [5:4] : SDRAM 의 Column Address 수를선택한다. (4) Bit [3] : SDRAM 동작에필요한 Timing 조건을결정한다. 1MHz 를기준으로 1MHz 이상인경우에는 을선택하여 Timing 을맞춰준다. (5) Bit [2] : SDRAM 동작에서 CAS Latency Cycle 을선택한다. (6) Bit [1:] : 해당 Bank 의 SDRAM 의 Data Bus 폭을결정한다. 11.1.2 SDRAM Clock Delay Register (MEMCLKCON) Address : x8_44h 31 : 12 R Reserved - 11 : 8 R/W Local SDRAM Clock Generation (Clock delay) h : CLOCK 1 : Invert CLOCK 1 : CLOCK+1ns 11 : Invert CLOCK+1ns 1 : CLOCK+2ns 11 : Invert CLOCK+2ns 11 : CLOCK+3ns 111 : Invert CLOCK+3ns Advanced Digital Chips, Inc. CONFIDENTIAL 15

Ver 1.6.7 1 : CLOCK+4ns 11 : Invert CLOCK+4ns 11 : CLOCK+5ns 111 : Invert CLOCK+5ns 11 : CLOCK+6ns 111 : Invert CLOCK+6ns 111 : CLOCK+7ns 1111 : Invert CLOCK+7ns 7 : R/W 1Mhz Clock generation Divider Value FFh < Register 설명 > (1) Bit [11:8] : SDRAM 의 Data 읽기시에사용되는 SDRAM Feedback Clock 의지연정도를결정한다. (2) Bit [7:] : SDRAM Refresh 동작을위하여 1MHz 주파수를생성하는데필요한값을설정한다. 사용되는 Main Clock 에따라서 Main Clock / (n+1) 로생성되므로 divider 값에는 n-1 값을설정한다. 11.1.3 SDRAM Refresh Control Register (MEMREFCON) Address : x8_48h 31 : 1 R Reserved - 9 R/W Refresh Period < Refresh Source : 1Mhz > b : 15 usec 1 : 3 usec 8 R/W Number of Refresh Cycle / Period < Refresh Source : 1Mhz > b : 1 Cycle 1 : 2 Cycle 7 : 1 R Reserved - R/W : Auto Refresh 1: Self Refresh b < Register 설명 > (3) Bit [9] : 1MHz 를사용하는경우의 Refresh 주기에대한선택을한다. (4) Bit [8] : 한주기에의해서몇번의 Refresh 를할것인지선택한다. (5) Bit [] : Refresh Mode select. 16 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 12 EXTERNAL SRAM CONTROLLER 12.1 Function Description 외부에 8/16-bit 의 NOR Flash, PROM, SRAM 을지원한다. 최대 512KB 크기의메모리를 4 개까지사용할수있다. External Static Memory 와의 Interface 를위해 SRAM_ALE1, SRAM_ALE, SRAM_nCS[3:], SRAM_nRE, SRAM_nWE, AD[15:], A[18:16], nbe1 을지원한다. 외부에 8-bit SRAM Memory 와의 Interface 을할때, AD[7:] 에서 Address[15:] 와 Data[7:] 의신호가발생한다. SRAM_ALE1 에서 AD[7:] 를 Latch 하면 Address[15:8] 이되고 SRAM_ALE 에서 AD[7:] 를 Latch 하면 Address[7:] 이된다. 이후 AD[7:] 은 SRAM_nCS, SRAM_nRE, SRAM_nWE 의구간에서 Data[7:] 을쓰거나읽을수있다. HCLK A[18:16] Address[18:16] AD[7:] Address[15:8] Address[7:] Data[7:] SRAM_ALE1 SRAM_ALE SRAM_nCS SRAM_nRE / SRAM_nWE tcss toes tacc toeh tcsh Figure 12-1 External 8-bit SRAM Memory Timing Diagram Figure 12-2 Connection 8-bit SRAM Memory Advanced Digital Chips, Inc. CONFIDENTIAL 17

Ver 1.6.7 외부에 16-bit SRAM Memory 와의 Interface 을할때, AD[15:] 에서 Address[15:] 와 Data[15:] 의신호가발생한다. SRAM_ALE 에서 AD[15:] 를 Latch 하면 Address[15:] 이된다. 이후 AD[15:] 은 SRAM_nCS, SRAM_nRE, SRAM_nWE 의구간에서 Data[15:] 을쓰거나읽을수있다. HCLK A[18:16] AD[15:] SRAM_ALE SRAM_nCS Address[15:] Address[18:16] Data[15:] SRAM_nRE / SRAM_nWE tcss toes tacc toeh tcsh Figure 12-3 External 16-bit SRAM Memory Timing Diagram Figure 12-4 Connection 16-bit SRAM Memory 18 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 12.2 Register Description 12.2.1 External SRAM_nCS Area Control Register (CSCTRL) Address : x8_8 23 : 22 R/W tale1h : Address Latch Enable Hold 11 : Clock 1 : 1 Clock 1 : 2 Clock 11 : 4 Clock 21 : 2 R/W tale1s : Address Latch Enable Setup 11 : Clock 1 : 1 Clock 1 : 2 Clock 11 : 4 Clock 19 : 18 R/W taleh : Address Latch Enable Hold : Clock 1 : 1 Clock 1 : 2 Clock 11 : 4 Clock 17 : 16 R/W tales : Address Latch Enable Setup : Clock 1 : 1 Clock 1 : 2 Clock 11 : 4 Clock 15 : 14 R/W tcss : Address Set-up before SRAM_nCS : Clock 1 : 1 Clock 1 : 2 Clock 11 : 4 Clock 13 : 12 R/W toes : Chip Selection Set-up nre / nwe : Clock 1 : 1 Clock 1 : 2 Clock 11 : 4 Clock 11 : 8 R/W tacc : Access Cycle : 1 Clock 1 : 2 Clock 1 : 3 Clock 11 : 4 Clock 1 : 6 Clock 11 : 8 Clock 11 : 1 Clock 111 : 12 Clock 1 : 14 Clock 11 : 16 Clock 11 : 18 Clock 111 : 2 Clock 11 : 22 Clock 111 : 24 Clock 111 : 26 Clock 1111 : 3 Clock 7 : 6 R/W toeh : Chip Selection Hold on nre / nwe : Clock 1 : 1 Clock 1 : 2 Clock 11 : 4 Clock 5 : 4 R/W tcsh : Address Holding Time after SRAM_nCS : Clock 1 : 1 Clock 1 : 2 Clock 11 : 4 Clock 3 R/W This bit determines whether using nbe1 pin for 16bit Data bus : Not using nbe1 1 : Using nbe1 2 R/W This bit determines WAIT status : nwait Disable 1 : nwait Enable 1 R/W This bit determines data bus width : 8 bit 1 : 16 bit R/W Error Response Enable bit in Read only Memory : Error Response Disable 1 : Error Response Enable 11 11 11 11 1111 11 11 Advanced Digital Chips, Inc. CONFIDENTIAL 19

Ver 1.6.7 12.2.2 External SRAM_nCS[3:1] Area Control Register (CSxCTRL) Address : x8_84 / x8_88 / x8_8c 31 : 24 R Reserved - 23 : 22 R/W tale1h : Address Latch Enable Hold : Clock 1 : 1 Clock 1 : 2 Clock 11 : 4 Clock 21 : 2 R/W tale1s : Address Latch Enable Setup : Clock 1 : 1 Clock 1 : 2 Clock 11 : 4 Clock 19 : 18 R/W taleh : Address Latch Enable Hold : Clock 1 : 1 Clock 1 : 2 Clock 11 : 4 Clock 17 : 16 R/W tales : Address Latch Enable Setup : Clock 1 : 1 Clock 1 : 2 Clock 11 : 4 Clock 15 : 14 R/W tcss : Address Set-up before SRAM_nCSx : Clock 1 : 1 Clock 1 : 2 Clock 11 : 4 Clock 13 : 12 R/W toes : Chip Selection Set-up nre / nwe : Clock 1 : 1 Clock 1 : 2 Clock 11 : 4 Clock 11 : 8 R/W tacc : Access Cycle : 1 Clock 1 : 2 Clock 1 : 3 Clock 11 : 4 Clock 1 : 6 Clock 11 : 8 Clock 11 : 1 Clock 111 : 12 Clock 1 : 14 Clock 11 : 16 Clock 11 : 18 Clock 111 : 2 Clock 11 : 22 Clock 111 : 24 Clock 111 : 26 Clock 1111 : 3 Clock 7 : 6 R/W toeh : Chip Selection Hold on nre / nwe : Clock 1 : 1 Clock 1 : 2 Clock 11 : 4 Clock 5 : 4 R/W tcsh : Address Holding Time after SRAM_nCSx : Clock 1 : 1 Clock 1 : 2 Clock 11 : 4 Clock 3 R/W This bit determines whether using nbe1 pin for 16bit Data bus : Not using nbe1 1 : Using nbe1 2 R/W This bit determines WAIT status : nwait Disable 1 : nwait Enable 1 R/W This bit determines data bus width : 8 bit 1 : 16 bit R/W Error Response Enable bit in Read only Memory : Error Response Disable 1 : Error Response Enable 11 11 11 11 11 11 1111 11 11 11 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 13 NAND FLASH CONTROLLER NAND Flash 제어기는 8-bit I/O 타입의 NAND Flash memory 와의데이터전송을관리한다. 13.1 Features - 8bit I/O support - 3-cycle/4-cycle/5-cycle Address support - 1bit for SLC and 4bit/24bit ECC for MLC - Auto ECC Decoding support NFCTRL_IRQ (To Interrupt Controller) SYS_RESETX (To All Blocks) adr_siz (From external pin) NFCFG NF_nCS NF_CLE NFCTRL Controller / Auto Boot logic NF_nWE NF_nRE AHB BUS NFSTAT NFCMD NFADD 1bit ECC 4-bit ECC 24-bit ECC NF_nBUSY NFDATA NF_IO[7:] 1Kbytes Buffer Figure 13-1 NAND Flash Controller Block Diagram Advanced Digital Chips, Inc. CONFIDENTIAL 111

Ver 1.6.7 13.2 Function Description Data Read/Write 1. 데이터전송을위한타이밍을 NFCFG 레지스터에설정한다. 2. NAND Flash Memory Command 를 NFCMD 레지스터에설정한다. 3. 접근할 NAND Flash Memory 의주소를 NFADR 레지스터를통해설정한다. 이때 NAND Flash 에접근에필요한 Address cycle 만큼반복하여설정하여야한다. 4. NFCPUDATA 레지스터를통해 Read/Write 동작을수행한다. 데이터를읽기전또는데이터를쓰고난뒤에는반드시 NDFL_nBUSY 핀을확인하여야한다. HCLK NAND_ALE NAND_CLE NAND_nWE NAND_nRE T s Twp / Trp T h Figure 13-2 Read/Write Timing Diagram of NAND Flash Memory DMA Operation NAND Flash 제어기는 DMA 전송을지원한다. 먼저 DMA 제어기를설정한후, NAND Flash 제어기를설정을한다. NFCTRL 레지스터에서 DMA 동작을설정하게되면 NAND Flash Memory 와 DMA 전송을시작한다. NAND Flash Memory 가 Large type(2 세대 ) 일경우, 최대 2KBytes 까지전송단위의설정이가능하며, Small type(1 세대 ) 인경우는 512Bytes 까지만설정할수있다. 13.3 ECC Operation 는 SLC 타입의 NAND Flash 뿐만아니라 MLC 타입의 NAND Flash 도지원한다. MLC 타입의 NAND Flash 는 SLC 에비해에러발생률이높기때문에이에러를보정해주어야사용할수있다. 의 NAND Flash Controller 는 BCH 알고리즘을이용하여 Parity bit 를생성하며, 이를이용하여데이터에러를복구할수있는기능을제공한다. 512Bytes 의데이터에대하여 4bit 에러, 1Kbytes 의데이터에 24bit 에러까지검출및복원을지원한다. 112 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 ECC Encoding 1. NAND Flash 를사용하기위해 NFCFG 레지스터를설정한후, Command 와 Address 를전송한다. 2. NFECC1 레지스터를 read 하여 ECC 상태와 ECC 관련레지스터를 clear 한다. 3. NFCTRL 레지스터의 ECC GEN bit 를 1 로설정한다. (ECC Generation enable) 4. 512Bytes 혹은 124Bytes 의데이터를전송한다. 데이터를전송할때마다 52-bit 또는 336-bit 크기의 Parity bits 가생성되어 NFECCn 들에저장된다. 5. 512Bytes 혹은 124Bytes 의전송이완료되면, NFECC, NFECC1 레지스터순서로 read 하여메모리상에저장해둔다. 6. 다시 512Bytes 혹은 124Bytes 단위로전송하기위하여 2-5 과정을반복한다. 7. 한페이지크기의전송이완료되면, NFCTRL 레지스터의 ECC GEN bit 를 으로설정한다. (ECC Generation disable) 8. 메모리에저장해두었던각 512Bytes 혹은 124Bytes 에대한 Parity bits 를 NAND Flash 의 spare 영역에저장한다. ECC Decoding by S/W 1. NAND Flash 를사용하기위해 NFCFG 레지스터를설정한후, Command 와 Address 를전송한다. 2. NFECC1 레지스터를 read 하여 ECC 상태와 ECC 관련레지스터를 clear 한다. 3. NFCTRL 레지스터에서 4-bit 혹은 24-bit ECC Mode 를선택하고, ECC GEN bit 를 1 로설정한다. (ECC Decoding enable) 4. 512Bytes 혹은 124Bytes 의데이터를 read 한다. 5. 512Bytes 혹은 124Bytes read 가완료되면, spare 영역에접근하여해당하는 Parity bits 를 read 한다. 6. Parity bits 의 read 가완료되면, 자동적으로 decoding 작업을시작하며, 사용자는 NFSTAT 레지스터에서 decoding 완료여부와성공여부를확인할수있다. 7. Decoding 이완료되면, NFERRLOC~3 혹은 ~23 레지스터에에러가발생한위치와 NFERRPTN~3 혹은 ~23 레지스터에 8bit 에러패턴이저장된다. 8. NFERRLOCn 위치의 8bit 데이터와 NFERRPTNn 값을 Exclusive-OR 하여손상된데이터를복원한다. 9. 한페이지를 read 할때까지 2-8 과정을반복한다. ECC Decoding by H/W (Auto ECC Decoding) 1. NAND Flash 를사용하기위해 NFCFG 레지스터를설정한후, Command 와 Address 를전송한다. 2. NFECC1 레지스터를 read 하여 ECC 상태와 ECC 관련레지스터를 clear 한다. 3. NFCTRL 레지스터에서 4-bit 혹은 24-bit ECC Mode 를선택하고 Auto ECC Decoding bit 를 1 로설정하면, 자동으로 NAND Flash 에서데이터와 parity 를읽어들인다. 4. NFSTAT 에서 Auto ECC Done bit 가 1 이되는것을확인한다. 5. NFECD 레지스터를통해복구된데이터를읽는다. 6. 한페이지를 read 할때까지 2-5 과정을반복한다. Advanced Digital Chips, Inc. CONFIDENTIAL 113

Ver 1.6.7 13.4 Register Description 13.4.1 NAND Flash Memory Control Register (NFCTRL) Address: xa_c 16 R/W Auto ECC Enable bit : Auto ECC done 1: Auto ECC Start 이 bit를 set하면 Auto ECC를시작하며, 완료되면자동으로 clear된다. 15 R/W 4-bit ECC Mode Set bit 1 : 24-bit ECC Mode 1: 4-bit ECC Mode 14:13 R Reserved - 12 R/W ECC Generation Enable bit : Disable 1 : Enable 11 R/W Endian Select bit : Little Endian 1 : Big Endian 1 R/W Data Swap Size : 8bit 1 : 16bit 9 R/W DMA Write Request bit : DMA Write Request Clear 1 : DMA Write Request 이 bit를 set하면 DMA 전송을시작하게되며, 완료 되면자동으로 clear된다. 8 R/W DMA Read Request bit : DMA Read Request Clear 1 : DMA Read Request 이 bit를 set하면 DMA 전송을시작하게되며, 완료 되면자동으로 clear된다. 7 R/W Busy End Interrupt Enable bit : Interrupt Disable 1 : Interrupt Enable 6 R/W DMA Clear Interrupt Enable bit : Interrupt Disable 1 : Interrupt Enable 5 R/W BCH ECC Decoding Done Interrupt Enable bit : Interrupt Disable 1 : Interrupt Enable 4 R/W Auto ECC Done Interrupt Enable bit : Interrupt Disable 1 : Interrupt Enable 3: R/W Reserved 114 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 13.4.2 NAND Flash Memory Command Set Register (NFCMD) Address: xa_c4 7 : R/W NAND Flash Memory Command h 13.4.3 NAND Flash Memory Address Register (NFADR) Address: xa_c8 7 : R/W NAND Flash Memory Address h 13.4.4 NAND Flash Memory Data Register (NFDATA) Address: xa_cc 31 : R/W NAND Flash Memory Read/Program Data 32/16/8-bit accessible _h 13.4.5 NAND Flash Memory Operation Status Register (NFSTAT) Address: xa_c14 16:12 R Error bit count ECC가완료된후, 검출된 Error bit의개수 11 R Read data not FF Flag Erase 후, NAND Flash의 data가전부 FF인지확인하는용도로사용된다. 읽은 data가 FF가아닌경우 1로 set되며, 이레지스터를읽으면 clear된다. 1 R Reserved - 9 R DMA Write Done DMA Write가완료되면 set된다. 이 register를읽으면 clear된다. 8 R DMA Read Done DMA Read가완료되면 set된다. 이 register를읽으면 clear된다. 7 R BCH Decoding Done Status ECC의 Decoding이완료되면 set된다. 이 register 를읽으면 clear된다 6 : 4 R Reserved - 3 R BCH Decoding Result : Decoding Fail 1 : Decoding Success 2 R Auto ECC Done bit 이 bit가 1이면 Auto ECC가완료되었음을나타낸다. 이 register를읽으면 clear된다. 1 R NAND Flash Memory nbusy Level : Busy 1 : Ready R NAND Flash Memory Busyx Rising Edge Status Ready/Busyx 신호가 low에서 high로변하면 1로 설정된다. 이 register를읽으면 clear 가된다. nbusy Level Advanced Digital Chips, Inc. CONFIDENTIAL 115

Ver 1.6.7 13.4.6 NAND Flash Memory ECC(Error Correction Code) Register (NFECC) Address: xa_c18 23 : 16 R/Clea r 15 : 8 R/Clea r 7 : R/Clea r *** P1~P4 : Column Parity, P8~P248 : Row Parity *** ~ : Logically inverse operation ECC2 (~P4, ~P4, ~P2, ~P2, ~P1, ~P1, ~P248, ~P248 ) ECC1 (~P124, ~P124, ~P512, ~P512, ~P256, ~P256, ~P128, ~P128 ) ECC (~P64, ~P64, ~P32, ~P32, ~P16, ~P16, ~P8, ~P8 ) FFh FFh FFh 116 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 13.4.7 NAND Flash Memory Configuration Register (NFCFG) Address: xa_c1c 2 R/w Read data Latch timing Adjust bit. Configure as system clock. : Minimum ~ 6Mhz 1 : 4Mhz ~ Maximum 1 19 : 17 R Reserved - 16 R/W NDFL_nCS Control : Chip Enable 1 : Chip Disable 1 15 R Reserved - 14 : 12 R/W Ts : NDFL_ALE/NDFL_CLE Set-up Time 111 : 1 Clock 1 : 2 Clocks 1 : 3 Clocks 11 : 4 Clocks 1 : 5 Clocks 11 : 6 Clocks 11 : 7 Clocks 111 : 8 Clocks 11 R Reserved - 1 : 8 R/W Twp : NDFL_nWE Pulse Width 111 : 1 Clock 1 : 2 Clocks 1 : 3 Clocks 11 : 4 Clocks 1 : 5 Clocks 11 : 6 Clocks 11 : 7 Clocks 111 : 8 Clocks 7 R Reserved - 6 : 4 R/W Trp : NDFL_nRE Pulse Width 111 : 1 Clock 1 : 2 Clocks 1 : 3 Clocks 11 : 4 Clocks 1 : 5 Clocks 11 : 6 Clocks 11 : 7 Clocks 111 : 8 Clocks 3 R Reserved - 2 : R/W Th : NDFL_ALE/ NDFL_CLE/ NDFL_nCS Hold Time 111 : 1 Clock 1 : 2 Clocks 1 : 3 Clocks 11 : 4 Clocks 1 : 5 Clocks 11 : 6 Clocks 11 : 7 Clocks 111 : 8 Clocks Advanced Digital Chips, Inc. CONFIDENTIAL 117

Ver 1.6.7 13.4.8 NAND Flash Memory ECC Code for LSN data (NFECCL) Address: xa_c2 15 : 8 R S_ECC1 (1, 1, 1, 1, 1, 1, ~P4_s, ~P4 _s) FFh 7 : R S_ECC (~P2_s, ~P2 _s, ~P1_s, ~P1 _s, ~P16_s, ~P16 _s, ~P8_s, ~P8 _s) *** P1_s~P4_s : Column Parity, P8_s~P16_s : Row Parity *** ~ : Logically inverse operation FFh 13.4.9 NAND Flash Memory Error Corrected Data Register (NFECD) Address: xa_c24 31 : R Automatically Error Corrected Data - 13.4.1 NAND Flash Memory Spare Address Register (NFSPADR) Address: xa_c28 15 : R/W Spare address to access during Auto ECC h 13.4.11 NAND Flash Memory MLC ECCn Register (NFECCn) Address: xa_c2c / xa_c3 / xa_c34 / xa_c38 / xa_c3c / xa_c4 / xa_c44 / xa_c48 / xa_c4c / xa_c5 / xa_c54 31 : R 4-bit ECC Parity Value 52-bit parity[31:] / 52-bit parity[52:32] 24-bit ECC Parity Value _h 336-bit parity[31:], 336-bit parity[63:32], 336-bit parity[95:64], 336-bit parity[127:96], 336-bit parity[159:128], 336-bit parity[191:16], 336-bit parity[223:192], 336-bit parity[255:224], 336-bit parity[287:256], 336-bit parity[319:288], 336-bit parity[335:32] 118 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 13.4.12 NAND Flash Memory Error Location n Register (NFERRLOCn) Address: xa_c58 / xa_c5c / xa_c6 / xa_c64 / xa_c68 / xa_c6c / xa_c7 / xa_c74 / xa_c78 / xa_c7c / xa_c8 / xa_c84 / xa_c88 / xa_c8c / xa_c9 / xa_c94 / xa_c98 / xa_c9c / xa_ca / xa_ca4 / xa_ca8 / xa_cac / xa_cb / xa_cb4 1 : R Error byte location 1 st ~24 th h 13.4.13 NAND Flash Memory Error Pattern n Register (NFERRPTNn) Address: xa_cb8 ~ xa_d14 7 : R Error byte pattern 1 st ~24 th h 13.4.14 NAND Flash Memory ID Register (NFMID) Address: xa_d18 31 : R NAND Flash ID _h Advanced Digital Chips, Inc. CONFIDENTIAL 119

Ver 1.6.7 14 SD HOST CONTROLLER 14.1 Features - SD (ver 2.) / MMC (ver 3.31) 카드지원 - High Speed (5 MHz) 지원 - 1bit / 4bit data bus 지원 - DMA 전송지원 - 64 byte FIFO 내장 - 4 bit Command Register - 136 bit Response Register 14.2 Block Diagram AMBA Bus (AHB) AMBA Interface CMD register (4 bit) Response register (136 bit) CLK control CMD control shift_register crc7 Tx cmd Rx resp CMD Line SDCLK FIFO (64 Byte) DATA control shift_register crc16 Tx data[3:] Rx data[3:] DATA Line Figure 14-1 SDHC Block Diagram 14.3 SD Card Protocol SD card 와 SD Host 사이의통신은 start bit 으로시작해서 stop bit 으로끝나는 command 와 response, data 를기반으로한다. Command : Command 는 Host(Controller) 가 Command line 을통해 SD 카드로전송되는명령어이다. Command 는여러개의 SD 카드를향해동시에전송되는 broadcast command 와 Address 로선택된하나의 SD 카드에만전송되는 addressed command 로분류된다. Response : Host 가전송한 Command 에대한응답으로써선택된카드가 Command line 을통해전송한다. Data : Host 에서 SD 카드로또는 SD 카드에서 Host 로 Data line 을통하여블록단위로 12 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 전송되며일반적으로 1 block 의크기는 512byte 또는 124 byte 이다. SD Card protocol 에서는데이터전송의신뢰성을위해 Command 와 Response 그리고 Data 를 CRC7 과 CRC16 로체크하며 CRC 코드생성과오류검출은하드웨어내부에서스스로이루어진다. 14.4 Register Description 14.4.1 SDHC Control Register (SDHCCON) Address : xa_1h 31 : 6 R Reserved - 5 R/W MMC/SD HC Enable Host에대한 Enable 비트이다. 이비트가 Disable 상태가되면컨트롤러의상태는초기화되고내부버퍼들은모두 clear된다. b : Disable (Controller is initialized) 1 : Enable 4 : 3 R/W Memory access type 이 비트는 SD 메모리카드에 Data를 저장할 때 데이터정렬방식을정하게된다. : byte align 1 : short align 1 : word align 11 : not use 2 R/W DMA mode selection DMA를사용하여빠르게데이터를전송할수 있는 모드를제공한다. : Normal mode (data transfer by CPU) 1 : DMA mode (data transfer by DMA) 1 R/W Bus width Selection : 1bit data bus 1 : 4bit data bus R/W MMC/SD clock enable : Disable 1 : Enable b b b b 14.4.2 SDHC Status Register (SDHCSTAT) Address: xa_14h 31 : 16 R Reserved - 15 R Card_Insertion Data line[3] 을통하여 SD카드가슬롯에삽입되었는 b 지를알려주는비트이다. 이를사용하기위해서는 data line[3] 은 weak Pull down 저항을달아야한 다. : No card insertion detection 1 : card insert detected Advanced Digital Chips, Inc. CONFIDENTIAL 121

Ver 1.6.7 14 R Card_Removal Data line[3] 을통하여 SD카드가슬롯에서제거되었는지를알려주는비트이다. : No card removal detection 1 : card remove detected 13 R FIFO full 64바이트데이터 FIFO 가가득찼음을나타내는비 트이다. 12 R FIFO half full 64바이트데이터 FIFO 가절반이상찼음을나타내 는비트이다. 11 R FIFO empty 64바이트데이터 FIFO가비워졌음을나타내는비트 이다. 1 R/C Command & response transaction done Host가 Command를 보내었을 때 그에 대한 response를받았음을 알려주는비트이다. 만약 Response가도착하지않는비정상적인경우에도 Time out error를발생시키며이비트가 1이된다. : Command and response transaction is in progress 1 : Command and response transaction is done 9 R/C Data Write operation done Data write operation이완료되었음을알려주는비 트이다. Data CRC error가발생한경우에도 write operation이종료되면서이비트가 1이된다. : Write operation is in progress or incomplete 1 : Write operation complete 8 R/C Read operation done Data read operation이완료되었음을알려주는비트 이다. Read data CRC error가발생한경우에도 read operation이종료되면서이비트가 1이된다. : Read operation is in progress or incomplete 1 : Read operation complete 7 :6 R/C Write CRC error code Write operation 진행중에 SD카드로부터받은 CRC 검사결과를나타내는코드이다. SD카드는 Host가한블록씩데이터를보낼때마다각블록에 대한 CRC를검사하여그결과값을 Host에게전송 한다. : No CRC Error 1 : CRC Error ( 데이터블록에서 CRC 에러발 생 ) 1 : No CRC response ( 데이터블록이 SD 카드에 서무시되었음 ) 11 : Reserved 5 R/C Response CRC error Response 에 CRC 에러가발생했음을알려주는비 트이다. : No error 1 : Response CRC error occurred b b b 1b b b b b b 122 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 4 R/C Read data CRC error SD카드로부터 Read 한데이터에 CRC 에러가발생했음을알려주는비트이다. : No error 1 : Read data CRC error occurred 3 R/C Write data CRC error SD카드로전송한 데이터에 CRC 에러가발생했음 을알려주는비트이다. : No error 1 : Write data CRC error occurred 2 R/C Response time out error Response가설정된시간안에오직않았음을알려 주는비트이다. : No error 1 : Command response was not received in time Specified 1 R/C Read data time out error Read 데이터가지정된시간안에오지않았음을알 려주는비트이다. : No error 1 : The expected data from card was not received in time Specified R Memory busy state SD카드의 busy 상태를나타내는비트이다. : Memory is ready 1 : Memory is busy b b b b b R/C는 Read/Clear를의미한다. Status의특정비트를 Clear 하는방법은해당비트에 1을쓰면 clear 된다. Status[15:8] 는인터럽트를발생하는인터럽트소스이기도한다. 이중에한비트가 1 이되면인터럽트가발생하고해당비트가 clear 되기전까지계속인터럽트를요청하게된다. 14.4.3 SDHC Clock Divide Register (SDHCCD) Address : xa_18h 31 : 1 R Reserved. - 9 : R/W MMC/SD clock Divide Register 2h f SDCLK f AHB_ Clock 2 Divide [9 : ] Advanced Digital Chips, Inc. CONFIDENTIAL 123

Ver 1.6.7 14.4.4 SDHC Response Time Out Register (SDHCRTO) Address: xa_1ch 31 : 8 R Reserved - 7 : R/W Response time out. Command를보낸후 response를기다리는최대시간을설정한다. 지정된시간안에 response가도착하지않을경우 response time out error가발생된다. 시간단위는 SD카드에전송되는클럭을기준으로하며 Command의마지막비트가전송되면클럭카운트가시작된다. FFh 1h : 1 clock count 2h : 2 clock counts... FFh : 255 clock counts 14.4.5 SDHC Read Data Time Out Register (SDHCRDTO) Address: xa_11h 31 : 16 R Reserved - 15 : 8 R/W Data read time out. FFh Read command를보낸후 read 데이터를받기까지기다리는최대시간을설정한다. 사용자는상위 8비트만설정할수있고하위 8비트는 h로고정되어있다. 일반적으로 FFh로설정할것을권장한다. 7 : R Reserved. h 14.4.6 SDHC Block Length Register (SDHCBL) Address: xa_114h 31 : 12 R Reserved - 11 : R/W Block length. 데이터전송의최소단위인블록의 byte 크기를정하는레지스터임 2h 14.4.7 SDHC Number of Block Register (SDHCNOB) Address: xa_118h 31 : 16 R Reserved - 15 : R/W Multi-block command를사용하여다수의 data block 을전송하는경우블록의개수를지정하는레지스터이다. 한블록씩전송될때마다 1씩감소하며전송완료되면 이된다. h 124 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 14.4.8 SDHC Interrupt Enable Register (SDHCIE) Address : xa_11ch 31 : 8 Reserved - 7 R/W Card insert detection Interrupt enable b : disable 1 : enable 6 R/W Card remove detection Interrupt enable b : disable 1 : enable 5 R/W FIFO full Interrupt enable b : disable 1 : enable 4 R/W FIFO half full Interrupt enable b : disable 1 : enable 3 R/W FIFO empty Interrupt enable b : disable 1 : enable 2 R/W End command response Interrupt enable b : disable 1 : enable 1 R/W Write operation done Interrupt enable b : disable 1 : enable R/W Read operation done Interrupt enable : disable 1 : enable b SDHCSTAT[15:8] 이인터럽트소스이고 SDHCIE 레지스터는이에대한인터럽트 Enable 신호이다. 인터럽트가발생하면인터럽트서비스루틴에서필요한작업을수행하고 SDHCSTAT[15:8] 중에인터럽트를발생시킨비트를 으로만든다. 그러나 card insert detection 인터럽트와 card remove detection 인터럽트는 SDHCSTAT[15] 와 SDHCSTAT[14] 는해당비트가 clear 되지않기때문에인터럽트서비스루틴안에서인터럽트 Enable 비트를 으로만들어인터럽트신호를 Disable 시킨다. Advanced Digital Chips, Inc. CONFIDENTIAL 125

Ver 1.6.7 14.4.9 SDHC Command Control Register (SDHCCMDCON) SDHCCMDCON 레지스터는사용자가 command 를보내기위해구성하는레지스터이다. 사용자가 SDHCCMDCON 레지스터에 write 하게되면레지스터에쓰여진설정대로 command 가 SD 카드로전송된다. Address: xa_12h 31 : 11 R Reserved - 1 R/W Response 가필요한 command type인지아닌지를결정하는비트이다. b No response를 설정하는 경우 response가 response buffer에저장되지않는다. : no response 1 : wait response 9 : 8 R/W Response type을결정하는비트이다. Response b type은 command 에따라달라지므로 command에맞는 response type을잘선택해야한다. : short response (response size : 48bit ) 1 : short response with busy (response size : 48bit, ) 1 : long response (response size : 136bit) 7 R/W Data stream이사용되는 command 인지아닌지를 b 결정하는비트이다. Read command 또는 Write command인경우이비트를 1로해야한다 : without data 1 : with data 6 R/W 데이터 FIFO의입출력방향을결정하는비트이다. b Read command 인경우 로설정하고 write command인경우 1로설정한다. : read data 1 : write data 5 : R/W command number를지정하는비트이다. Command number의의미는 MMC 와 SD card가조금씩다르므로각각의 spec을참고하기바람. h = CMD 1h = CMD1... 3Fh = CMD63 h 14.4.1 SDHC Command Argument Register (SDHCCMDA) Address: xa_124h 31 : R/W Command argument. Command token을구성하는항목중에 argument를설정하는레지스터이다. h 126 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 14.4.11 SDHC Response FIFO Access Register (SDHCRFA) Address: xa_128h 31 : 16 R Reserved - 15 : R/W Response를저장하는 FIFO이다. 크기는 8x16 bit h 14.4.12 SDHC Data FIFO Access Register (SDHCDFA) Address: xa_12ch 31 : R/W 데이터를저장하는 FIFO 이다. 크기는 16x32 bit - Advanced Digital Chips, Inc. CONFIDENTIAL 127

Ver 1.6.7 15 USB DEVICE 에내장된 USB Device 는 2. Full-speed(12Mbps) 를지원하며, 5 개의 endpoint 으로구성되어있다. 하드웨어적으로 USB 프로토콜을지원하며, 자동적인 data retry, data toggle 그리고 power management 기능 (suspend 와 resume) 을지원한다. 내부에 PHY 가포함되어있다. 15.1 Features - USB 2. Full Speed(12Mbps) - 5 개의 Endpoint 지원 - 하드웨어적으로 USB 프로토콜지원 - Suspend 와 Resume signaling 지원 Table 15-1 Endpoint List Endpoint Max Size (bytes) Direction Transaction Type 16 IN/OUT Control 1 64 OUT Bulk 2 64 IN Bulk 3 16 OUT Interrupt 4 16 IN Interrupt 15.2 Register Summary Table 15-2 USB Core Register List Register Address R/W Description Default Value USBFA xa18 R/W Function address register x USBPM xa184 R/W Power management register x USBEPI xa188 R/W Endpoint interrupt register x USBINT xa181 R/W USB interrupt register x USBEPIEN xa1814 R/W Endpoint interrupt enable register x1f USBINTEN xa1818 R/W USB interrupt enable register x4 USBLBFN xa181c R Frame number1 register x USBHBFN xa182 R Frame number2 register x USBIND xa1824 R/W Index register x USBMP xa1828 R/W MAXP register x USBEPC xa182c R/W EP control register x USBIC1 xa182c R/W EP2, 4 IN Control register1 x USBIC2 xa183 R/W EP2, 4 IN Control register2 x USBOC1 xa1838 R/W EP1, 3 OUT Control register 1 x USBOC2 xa183c R/W EP1, 3 OUT Control register 2 x USBLBOWC xa184 R Low Byte OEP Write count register x USBHBOWC xa1844 R High Byte OEP write count register x USBEPD xa1848 R/W EP FIFO data register x USBEP1D xa184c R/W EP1 FIFO data register x_ USBEP2D xa185 R/W EP2 FIFO data register x_ USBEP3D xa1854 R/W EP3 FIFO data register x USBEP4D xa1858 R/W EP4 FIFO data register x 128 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 15.2.1 USB Function Address Register USBFAR 레지스터에는호스트에의해할당된 USB 디바이스주소가저장된다. MCU 는 SET_ADDRESS Descript 수행을통해받은값을이레지스터에저장한다. 이값은다음토큰에서사용된다. 15.2.2 USB Power Management Register Power Management 레지스터는 Suspend, Resume 그리고 reset 신호에의해사용된다. Suspend 와 Reset 상태는 USB_INTERRUPT Register 에저장된다. 15.2.3 USB Interrupt Registers USB Host 의요청상태와각 Endpoint 의상태와알려준다. 15.2.4 USB Interrupt Enable Registers 각 Endpoint 의인터럽트를 Enable 한다. 대부분의인터럽트는초기값이 Enable 상태이나, Suspend 인터럽트는 Disable 이다. 15.2.5 Frame Number Registers Frame Packet 의끝에서 frame 번호를저장한다. 15.2.6 Index Register 인덱스레지스터는각각의 endpoint 에해당하는컨트롤레지스터를선택할때사용한다. 15.2.7 MAXP Register 8byte 배수단위로사용할 FIFO 크기를조절할수있다. 그러나각 Endpoint 에서지원하는최대 FIFO 사이즈보다크게는설정할수없다. 15.2.8 EP Control Register Endpoint 의제어와상태를나타낸다. 15.2.9 IN Control Registers IN Endpoint 의제어와상태를나타낸다. 15.2.1 Out Control Registers Out Endpoint 의제어와상태를나타낸다. 15.2.11 Out Write Count Registers 두개의레지스터로이루어져 write count 값을가지다. OUT endpoint 에서 OPOPR 비트가 set 되면, 이레지스터에는 MCU 에의해가져간 packet 의수를가지고있다. 15.2.12 Endpoint FIFO Access Registers FIFO 에접근하는 register 이다. Advanced Digital Chips, Inc. CONFIDENTIAL 129

Ver 1.6.7 15.3 Register Description 15.3.1 USB Function Address Register (USBFA) Address : xa_18h Bit R/W MCU USB Description 31 : 8 Reserved 7 R/W R/ ADDUP : ADDR_UPDATE bit. Clear 이레지스터의 FUNADD field가업데이트되면 MCU는 이비트를 1 로설정한다. FUNADD field는, Endpoint CSR의 DATA_END 비트를 clear에의해발생되는제어 전송의 status phase 이후부터사용된다. 6 : R/W R FUNADD : FUNCTION_ADDR bits. MCU가주소를여기에 write 한다. Default Value 15.3.2 USB Power Management Register (USBPM) Address : xa_184h Bit R/W MCU USB Description 31 : 4 Reserved 3 R Set UBRST : USB_RESET bit. 호스토로부터 Reset 신호를받으면 USB가이비트를 설정한다. Reset 신호가버스상에서유지되는한, 이비트는 set 상태를유지한다. 2 W/R R UBRSUM : USB_RESUME bit. Resume 신호를초기화하기위해 MCU가 1ms ( 최대 15ms) 동안이비트를설정한다. Suspend 모드에서이 비트가설정되어있는동안 USB 가 Resume 신호를발생한다. 1 R R/W UBSPDMOD : SUSPEND_MODE bit. Suspend모드로들어가게되면 USB 가이비트를 설정한다. 다음조건에의해 clear 가된다. -Resume 신호를 끝내기 위해서 MCU가 MUC_RESUME 를 clear 하는경우 -USB_RESUME 인터럽트발생때 MCU가인터럽트 레지스터 3 을읽게되는경우. R/W R UBENSPD : ENABLE_SUSPEND bit = 1 Enable Suspend mode = Disable Suspend mode (Default) 이비트가 zero 이면, 디바이스는 suspend 모드상태로 들어가지않는다. Default Value 13 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 15.3.3 USB Endpoint Interrupt Register (USBEPI) Address : xa_188h R/W Bit Description MCU USB 31 : 5 Reserved Default Value 4 R/ Clear 3 R/ Clear 2 R/ Clear 1 R/ Clear R/ Clear Set Set Set Set Set EP4INT : EP4 Interrupt bit. (Interrupt in mode) 이비트는 endpoint4 인터럽트에해당된다. (USBIC1R, USBIC2R 의 bit 참고 ) - ICIPR(In Control 1 In Packet Ready bit) 비트가 clear 될때 - FIFO가 flush 되었을때 - ICSTSTAL(In Control 1 Sent Stall bit) 비트가 set 되었을경우에 EP3INT : EP3 Interrupt bit. (Interrupt out mode) 이비트는 endpoint3 인터럽트에해당된다. (USBOC1R, USBOC2R 의 bit 참고 ) - OCOPR(Out Control 1 Out Packet Ready bit) 비트를 set 할때 - OCSTSTAL(Out Control 1 Sent Stall bit ) 비트를 set 할때 EP2INT : EP2 Interrupt bit. (Bulk in mode) 이비트는 endpoint2 인터럽트에해당된다. (USBIC1R, USBIC2R 의 bit 참고 ) - ICIPR(In Control 1 In Packet Ready bit) 비트가 clear 될때 - FIFO가 flush 되었을때 - ICSTSTAL(In Control 1 Sent Stall bit) 비트가 set 되었을경우에 EP1INT : EP1 Interrupt bit. (Bulk out mode) 이비트는 endpoint1 인터럽트에해당된다. (USBOC1R, USBOC2R 의 bit 참고 ) - OCOPR(Out Control 1 Out Packet Ready bit) 비트를 set 할때 - OCSTSTAL(Out Control 1 Sent Stall bit ) 비트를 set 할때 EPINT : EP Interrupt bit. (Control mode) 이비트는 endpoint 인터럽트에해당된다. (USBEPCR 의 bit 참고 ) 1. EPOPR bit is set. 2. EPIPR bit is cleared 3. EPSTSTAL bit is set 4. EPSTED bit is set 5. EPDED bit is cleared(indicates End of control transfer) Advanced Digital Chips, Inc. CONFIDENTIAL 131

Ver 1.6.7 15.3.4 USB Interrupt Register (USBINT) Address : xa_181h Bit R/W MCU USB Description 31 : 3 Reserved 2 R/ Set RSTINT : USB Reset Interrupt bit. Clear Reset신호가입력되면 USB가이비트를 set 한다. 1 R/ Set RSUMINT : Resume Interrupt bit. Clear Suspend 모드상태에서 Resume신호를받으면 USB가이 비트을 set한다. USB Reset에의한 Resume 이면, Resume 인터럽트에의해 MCU에먼저인터럽트가걸린다. 일단 Clock이다시동작하고 SE 상태가 3ms 동안지속되면, USB Reset 인터럽트가발생한다.. R/ Clear Set SPDINT : Suspend Interrupt bit Suspend 신호를수신하면 USB는이비트를 set 한다. 버스상에서 3ms 동안아무런동작이이루어지지않으면이비트는 set 된다. 그래서 MCU가첫번째 suspend 인터럽트이후에 Clock을멈추지않으면, USB 버스상에서아무런동작이이루지않는한매 3ms 마다인터럽트가계속발생한다. 디폴트로이인터럽트는 disable 이다. Default Value 15.3.5 Endpoint Interrupt Enable Register (USBEPIEN) Address : xa_1814h 31 : 5 R Reserved 4 R/W EP4INTEN : Endpoint 4 Interrupt enable bit 1 3 R/W EP3INTEN : Endpoint 3 Interrupt enable bit 1 2 R/W EP2INTEN : Endpoint 2 Interrupt enable bit 1 1 R/W EP1INTEN : Endpoint 1 Interrupt enable bit 1 R/W EPINTEN : Endpoint Interrupt enable bit 1 15.3.6 USB Interrupt Enable Register (USBINTEN) Address : xa_1818h 31 : 3 R Reserved 2 R/W RSTINTEN : USB RESET Interrupt enable bit 1 1 R Reserved R/W SPDINTEN : SUSPEND Interrupt enable bit 15.3.7 USB Low Byte Frame Number Register (USBLBFN) Address : xa_181ch 31 : 8 R Reserved 7 : R/W Frame Number 1 register x 132 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 15.3.8 USB High Byte Frame Number Register (USBHBFN) Address : xa_182h 31 : 8 R Reserved 7 : R/W Frame Number 2 register x 15.3.9 USB Index Register (USBIND) Address : xa_1824h 31 : 3 R Reserved 2 : R/W Index register : Endpoint 1 : Endpoint 1 1 : Endpoint 2 11 : Endpoint 3 1 : Endpoint 4 11 : Reserved 11 : Reserved 111 : Reserved 15.3.1 USB MAXP Register (USBMP) Address : xa_1828h 31 : 8 R Reserved 7 : R/W Max FIFO Size x _1 MAXP=8 _1 MAXP=16 _1 MAXP=32 _1 MAXP=64 Advanced Digital Chips, Inc. CONFIDENTIAL 133

Ver 1.6.7 15.3.11 USB EP Control Register (USBEPC) Address : xa_182ch Bit R/W MCU USB Description 7 Clear EPSUEC : EP Set Up End Clear bit. MCU가 EPSTED 비트를 clear 하기위해 1 를 write 한다. 6 Clear EPOPRC : EP Out Packet Ready Clear bit. MCU는 EPOPR 비트를 clear하기위해이비트에 1 를 write한다. 5 Set Clear EPSDSTAL : EP Send Stall bit. MCU는잘못된 token이라고인식되면, EPOPR 비트를 clear와동시에이비트를 set 한다. USB는 STALL handshake를현재컨트롤전송에발생시킨다. MCU는 STALL 상황을끝내기위해 를 write 한다. 4 R Set EPSTED : EP Setup End bit. 이비트는읽기전용이 다. EPDED 비트가 set되기전에컨트롤전송이끝났을때 USB 가 이비트를 set한다. USB가이비트를 set 할 때 MCU에 인터럽트가 전달된다. 이러한 상황이 발생했을때 USB는 FIFO를 flush하고 MCU의 FIFO 접근을무효화한다. MCU의 FIFO 접근이무효화될때 이비트는 clear 된다. 3 Set/R Clear EPDED : EP Data End bit. MCU는다음과같은상황에서이비트 set한다 : - 마지막데이터패킷를가져온후 EPOPR 비트를 clear 할때 - Zero length data 구간에서 EPOPR 비트를 clear 하고 EPIPR 비트 를 set 할때 - MCU가 FIFO에대한패킷데이터를 load한후에 EPIPR 비트를 set함과동시에이비트 (EPDED) 를 set 한다. 2 Clear Set EPSTSTAL : Sent Stall bit. /R 프로토콜오류로컨트롤 transaction이끝나면 USB가이 비트 set 한다. 이 비트가 set 되면 인터럽트가 발생한다. 1 Set/R Clear EPIPR : EP In Packet Ready bit. MCU는 endpoint FIFO에데이터패킷을 write 한후에 이 비트을 set 한다. 데이터 패킷이 성공적으로 호스트에전달되면 USB가이비트을 clear 시킨다. USB가이비트를 clear시키면인터럽트가발생한다. 그래서 MCU는계속해서다음데이터를 load 할수 있게된다. Zero length data phase에서는 MCU는동시에 이비트 (EPIPR) 와 EPDED 비트를 set 한다. R Set EPOPR : EP Out Packet Ready bit. 이비트는읽기전용이다. 유효한 token이 FIFO에 쓰여지면 USB가이비트를 set 한다. USB가 set 하면 인터럽트가발생한다. MCU는 EPOPRC 비트에 1 를 write 함으로써이비트를 clear 시킨다. Default Value 134 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 15.3.12 USB IN Control 1 Register (USBIC1) Address : xa_182ch Bit R/W MCU USB Description 31 : 7 R Reserved 6 Set R/Clea ICCDT : In Control 1 Clear Data Toggle bit. r MCU가이비트에 1 을 write하면 data toggle 비트가 clear 된다. 이비트는쓰기전용이다. 5 R/ Clear Set ICSTSTAL : In Control 1 Sent Stall bit. MCU가 ICSDSTAL 비트를 set 했기때문에, IN token 에 STALL handshake를발생된다. 이때 USB 가이비트를 set 한다. USB 가 STALL handshake를발생시키면 ICIPR 비트는 clear된다. MCU 가 를 write함으로써이비트를 clear 시킨다. Default Value 4 R/W R ICSDSTAL : In Control 1 Send Stall bit. MCU가 USB에 STALL handshake를발생시키기위해이 비트에 1 를 write한다. STALL 상황을끝내기위해 MCU가이비트를 clear 한다. 3 R/Set Clear ICFFLU : In Control 1 FIFO Flush bit. IN FIFO를 flush하고자하면 MCU가이비트를 set 한다. FIFO가 flush가되면 USB 에의해이비트는 clear 된다. 이런 상황이발생하면 MCU에인터럽트가 걸린다. Toke이진행중이라면, USB는 FIFO가 flush 되기전에전송이완료될때까지기다린다. 만약에두개의패킷이 FIFO에 load되어있으면, 가장상위의패킷 ( 호스트로보내려고하는것 ) 만 flush이되고그패킷에관련있는 ICIPR 비트가 clear 된다. 2 Reserved 1 R Set ICFNE : In Control 1 FIFO Not Empty bit. FIFO에적어도한개의데이터패킷이있음을나타내다. : FIFO에패킷이없다. 1 : FIFO에패킷이있다. Set / R Clear ICIPR : In Control 1 In Packet Ready bit. FIFO에데이터패킷을쓰고난뒤 MCU가이비트를 set 한다. 호스트로데이터패킷전송이성공적으로 끝나면 USB는이비트를 clear 한다. 이비트를 USB 가 clear 하면인터럽트가발생하고, MCU는다음패킷을로드할수있게된다. 이 비트가 set 되어있는동안에는 MCU는 FIFO에쓰기를 할수없다. MCU에의해 ICSDSTAL 비트가 set 되면, 이비트는 set 될수없다. Advanced Digital Chips, Inc. CONFIDENTIAL 135

Ver 1.6.7 15.3.13 USB IN Control 2 Register (USBIC2) Address : xa_183h Bit R/W MCU USB Description Default Value 31 : 8 R Reserved 7 R/W R ICASET : In Control 2 Auto Set bit. 이 비트가 set 되어 있으면, MCU가 MAXP만큼의데이터를쓰기를하면자동적으로 ICIPR 비트가 set 된다. MAXP데이터보다적은데이터를쓸경우는 MCU가 ICIPR 비트를 set 해줘야한다. 6 Reserved 5 R/W R ICMODIN : In Control 2 Mode In bit. 1 Endpoint의방향을프로그램머블할수있게끔해준다. 1 = endpoint의방향을 IN으로설정된다. = endpoint의방향을 OUT으로설정된다. 4 : Reserved 136 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 15.3.14 USB Out Control Register 1 (USBOC1) Address : xa_1838h Bit R/W MCU USB Description 31 : 8 R Reserved 7 R/W R OCCDT : Out Control 1 Clear Data Toggle bit. MCU가이비트에 1 를 write하면, data toggle sequence 비트가 DATA 로 reset 된다. 6 Clear/ Set OCSTSTAL : Out Control 1 Sent Stall bit. R OUT token이 STALL handshake로 종료될 때 USB가이비트 set 한다. OUT Token에서 MAXP 데이터보다더많은데이터를보낼경우 USB가 host에 stall handshake를발생시킨다. MCU가 를 write하면 clear 된다. 5 W/R R OCSDSTAL : Out Control 1 Send Stall bit. USB에 STALL handshake를 발생시키기 위해 MCU가이비트에 1 를 write 한다. STALL 상황을끝내기위해 MCU가이비트에 을 write 한다. 4 R/W Clear OCFFLU : Out Control 1 FIFO Flush bit. MCU가 FIFO를 flush하기위해 1 를 write 하고 flush를멈추기위해 을 write 한다. OCOPR 비트가 set되어있는동안만이비트가 set 될수 있다. MCU 가가져간데이터패킷은 flush가될 것이다. 3 R R/W OCERR : Out Control 1 Data Error bit 전송받은데이터에에러 (bit stuffing 또는 CRC) 가있음을나타낸다. OCOPR 비트가 clear될 때자동적으로 clear 된다. 2 R R Reserved 1 R R/W OCFFUL : Out Control 1 FIFO Full bit. 더이상의패킷을수용할수없음을나타낸다. : FIFO is not full. 1 : FIFO is full. R/ Set OCOPR : Out Control 1 Out Packet Ready bit. Clear FIFO에데이터패킷이 load가되면 USB 가이 비트를 set 한다. MCU가패킷전체를읽고나면 이 비트는 MCU에 의해 clear 되어야 한다. MCU가 을 write 함으로써 clear 된다. Default Value Advanced Digital Chips, Inc. CONFIDENTIAL 137

Ver 1.6.7 15.3.15 USB OUT Control Register 2 (USBOC2) Address : xa_183ch Bit R/W MCU USB Description Default Value 31 : 8 R Reserved 7 R/W R OCACLR : Out Control 2 Auto Clear bit. 이비트가 set이면, MCU가 OUT FIFO에서데이터를읽을때마다자동적으로 USB core에의해 OCOPR 비트가 clear 된다. 6 : Reserved 15.3.16 USB Low Byte Out Write Count Register (USBLOWC) Address : xa_184h 31 : 8 R Reserved 7 : R/W (LBOWC) Low Byte OEP write count register x 15.3.17 USB High Byte Out Write Count Register (USBHBOWC) Address : xa_1844h 31 : 8 R Reserved 7 : R/W (HBOWC) High Byte OEP write count register x 138 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 15.3.18 EP FIFO Data Register (USBEP) Address : xa_1848h 7 : R/W EP FIFO Data Register x 15.3.19 EP1 FIFO Data Register (USBEP1) Address : xa_184ch 31 : R/W EP1 FIFO Data Register x 15.3.2 EP2 FIFO Data Register (USBEP2) Address : xa_185h 31 : R/W EP2 FIFO Data Register x 15.3.21 EP3 FIFO Data Register (USBEP3) Address : xa_1854h 7 : R/W EP3 FIFO Data Register x 15.3.22 EP4 FIFO Data Register (USBEP4) Address : xa_1858h 7 : R/W EP4 FIFO Data Register x Advanced Digital Chips, Inc. CONFIDENTIAL 139

Ver 1.6.7 16 LCD CONTROLLER 16.1 Features - Supports displays resolutions up to 8 x 6-256 x 32 FIFO controls in LCDC block. - Internal Color Bar Generator - Programmable Horizontal, Vertical and Field Input Sync. Phase. - Programmable Horizontal, Vertical Sync. and Blank Output Signal Timing and Phase 16.2 Register Description LCD Controller Register Summary Address Register Name Description Horizontal Active와 Blank구간을 x82_244h LCD Horizontal Total Register (LCDHT) 포함한 Horizontal Total Scan Value x82_248h LCD Horizontal Sync. Start / End Register Horizontal Sync 구간의 Start(End) (LCDHS) value x82_24ch LCD Horizontal Active Start / End Register Horizontal Active 구간의 Start(End) (LCDHA) value x82_241h LCD Vertical Total Register (LCDVT) Vertical Active와 blank 구간을포함한 Vertical Total scan value x82_2414h LCD Vertical Sync. Start/End Register (LCDVS) Vertical Sync 구간의 Start(End) value x82_2418h LCD Vertical Active Start/End Register (LCDVA) Vertical Active구간의 Start(End) value x82_241ch LCD Display Current X / Y Position Register (LCDXY) Horizontal/Vertical Counter value x82_242h LCD Status Register (LCDSTAT) LCD controller의 Sync상태 x82_2424h LCD Control Register (LCDCON) LCD의 Display, Sync, Memory, FIFO 모드를제어 x82_2428h LCD Overlay & DAC Control Register (LCDOEDAC) Overlay / DAC control x82_242ch LCD VESA Power Management Register VESA Display Power Management (LCDPM) System (DPMS) control x82_243h LCDC Base Address Screen의시작위치를지정 x82_2434h LCDC Base Address 1 Screen의시작위치를지정 x82_2438h LCDC Frame sync. Counter Frame Sync가발생할때마다 count x82_243ch LCD Horizontal Width Horizontal width를결정 x82_244h LCD Flip Command Process flip operation Table 16-1 LCD Controller Registers Table 14 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 16.2.1 LCD Base Address Register(LCDBA) Address : x82_24h 31 : 21 R Reserved - 2 : R/W Base Address These bits indicates the start position of the screen in the memory h 16.2.2 LCD Horizontal Total Register(LCDHT) Horizontal Active 와 Blank 구간을포함한 Horizontal Total scan value Address : x82_244h 31 : 11 R Reserved - 1 : R/W Horizontal Total The value loaded into this field is the total pixel counts per line. h 16.2.3 LCD Horizontal Sync. Start / End Register(LCDHS) Horizontal Sync 구간의 Start(End) value. Address : x82_248h 31 : 27 R Reserved - 26 : 16 R/W Horizontal Sync Start h The value loaded into this field is the value of horizontal sync period start by the horizontal counter 15 : 11 R Reserved - 1 : R/W Horizontal Sync End The value loaded into this field is the value of horizontal sync period end by the horizontal counter h 16.2.4 LCD Horizontal Active Start / End Register(LCDHA) Horizontal Active 구간의 Start(End) value. Address : x82_24ch 31 : 27 R Reserved - 26 : 16 R/W Horizontal Active Start h The value loaded into this field is the value of horizontal active period start by the horizontal counter 15 : 11 R Reserved - 1 : R/W Horizontal Active End The value loaded into this field is the value of horizontal active period start by the horizontal counter h Advanced Digital Chips, Inc. CONFIDENTIAL 141

Ver 1.6.7 16.2.5 LCD Vertical Total Register(LCDVT) Vertical Active 와 Blank 구간을포함한 Vertical Total scan value. Address : x82_241h 31 : 11 R Reserved - 1 : R/W Vertical Total The value loaded into this field is the value of the total vertical line counts. h 16.2.6 LCD Vertical Sync. Start / End Register(LCDVS) Vertical Sync 구간의 Start(End) value. Address : x82_2414h 31 : 27 R Reserved - 26 : 16 R/W Vertical Sync Start h The value loaded into this field is the value of vertical sync period start by the vertical counter 15 : 11 R Reserved - 1 : R/W Vertical Sync end The value loaded into this field is the value of vertical sync period end by the vertical counter h 16.2.7 LCD Vertical Active Start / End Register(LCDVA) Vertical Active 구간의 Start(End) value. Address : x82_2418h 31 : 27 R Reserved - 26 : 16 R/W Vertical Active Start h The value loaded into this field is the value of vertical active period start by the vertical counter 15 : 11 R Reserved - 1 : R/W Vertical Active end The value loaded into this field is the value of vertical active period end by the vertical counter h 142 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 16.2.8 LCD Display Current X / Y Position Register(LCDXY) Display Current X Position 레지스터는 Read Only 레지스터이며, Horizontal Counter 값을반영하고있다. Display Current Y Position 레지스터도 Read Only 레지스터이며, Vertical Counter 값을반영하고있다. Address : x82_241ch 31 : 27 R Reserved - 26 : 16 R The value loaded into this field is the value of the h vertical counter. 15 : 11 R Reserved - 1 : R The value loaded into this field is the value of the horizontal counter. h 16.2.9 LCD Status Register(LCDSTAT) LCD Status 레지스터는 Read Only 이며, LCD controller 의 Sync 상태를읽어볼수있다. Horizontal Sync 와 Vertical Sync 신호는, Control Register [21:2] Bit 이 일때, 둘다 Low active 상태를갖는다. 이두 Bit 이 11 일때, 두 Sync. 신호는 High active 상태를갖게된다. Horizontal / Vertical Active 는신호는 Control Register [21:2] Bit 에상관없이 High active 상태를갖는다. Address : x82_242h 31 : 7 R Reserved - 6 R Current Display Bank b : BANK, 1 : BANK1 4 R Field ( 1 : ODD Field, : EVEN Field ) 1b 3 R Vertical Active (active high) b 2 R Vertical Sync 1b 1 R Horizontal Active (active high). b R Horizontal Sync 1b 16.2.1 LCD Control Register(LCDCON) LCD Control 레지스터는 LCDC 의동작모드제어를위해사용된다. * Frame Memory Bank <n> Ping-Pone Enable : Graphic Engine Flip Command 에의한 Frame Memory Bank 전환을비활성 / 활성시킨다. - 비활성시 LCD Frame Memory Bank 는고정된다. - 활성시 Graphic Engine Flip Command 에의해 LCD Frame Memory Bank 전환이이루어진다 ( CSC Image Capturer Control Register Bit 설명참조 ) * Vertical Double Scan : 한라인을 Vertical 방향으로두번디스플레이한다. * Horizontal Double Scan : 한 Pixel 을 Horizontal 방향으로두번디스플레이한다. Advanced Digital Chips, Inc. CONFIDENTIAL 143

Ver 1.6.7 Address : x82_2424h 31 : 25 R Reserved - 24 R/W Software Reset. 1b : = Normal operation 1=Reset,. 23 R Reserved - 22 R/W DOT CLOCK SELECT : = NORMAL 1 = INVERTED 21 R/W HSYNC. Output Polarity. b : = LOW ACTIVE 1 = HIGH ACTIVE 2 R/W VSYNC. Output Polarity. b : = LOW ACTIVE 1 = HIGH ACTIVE 19 R/W Frame Memory Bank <n> Ping-Pong Enable. b : = Disable 1 = Enable 18 : 17 R/W FIFO Request Control(Total depth : 256) b : one half request(128) 1 : one fourth request(64) 1 : one eighth request(32) 11 : Don t use 16 : 15 R Reserved b 14 R/W WHEN RGB 32BIT MODE, INPUT DATA SEQUENCE b : = drgb 1 = RGBd 13 : 12 R/W Input Source Format b : = YCbCr422 : 1 = RGB 16bit : 1 = RGB 32bit 11 : 4 R Reserved b 3 R/W Vertical Double Scan Enable. b : = Disable 1 = Enable 2 R/W Horizontal Double Scan Enable. b : = Disable 1 = Enable 1 : R/W Screen Display Mode Control. : =Normal operation. : 1=Regular Pattern Generation : 1x=Screen off b 16.2.11 LCD Overlay & DAC Control Register(LCDOEDAC) Address : x82_2428h 31 : 24 R/W Reserved - 23 : 16 R/W Contrast Control 8h FFh : Bright 8h : Default h : Dark 15 : 8 R Reserved - 7 : R/W Brightness Control FFh : Maximum Contrast 8h : Default h : Minimum Contrast 8h 144 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 16.2.12 LCD VESA Power Management Control Register(LCDPM) Address : x82_242ch 31 : 2 R Reserved - 1 : R/W VESA Power Management Control. b 1: Stage Vsync. Hsync. On On On 1 Stand-by On Off 1 Suspend Off On 11 Off Off Off 16.2.13 LCD Base Address n Register (LCDBARn) Address : x82_243h / x82_2434h 31 : 19 R/W Base Address n h SDRAM 영역만가능 18 : R Reserved - 16.2.14 LCD Frame Sync. Count Register (LCDFRAMECNT) Address : x82_2438h 31 : R/W Frame Sync. Count h 16.2.15 LCD Horizontal Width Register (LCDHWIDTH) Address : x82_243ch 31 : 12 R Reserved - 11 : R/W Horizontal Width 4h 16.2.16 LCD Flip Control Register (LCDFCTL) Address : x82_244h 31 : 4 R Reserved - 3 R BANK1 -> BANK completed 2 R BANK -> BANK1 completed 1 R/W Request change to Bank1 R/W Request change to Bank Advanced Digital Chips, Inc. CONFIDENTIAL 145

Ver 1.6.7 다음은국제 TV 신호에대하여각방식에대한신호규격을간단히요약한것이다. NTSC PAL B,D,G,H,I,N M Combi - N Hsync Width 4.7 usec 4.7 usec 4.7 usec 5. usec Front Porch 1.5 usec 1.5 usec 1.75 usec 1.9 usec Back Porch 4.7 usec 5.8 usec 4.55 usec 4. usec H. Display 52.6 usec 52. usec 52.5 usec 53.1 usec H. total 63.556 usec 64. usec 63.556 usec 64. usec / 15,734 Hz / 15,625 Hz / 15,734 Hz / 15,625 Hz H. line/frame 525 625 525 625 Field freq. 59.94 Hz 5 Hz 59.94 Hz 5 Hz I = 5.5MHz Video 4.2 MHz B,G,H = 5.MHz 4.2 MHz 4.2 MHz Bandwidth N = 4.2MHz D = 6.MHz Color Burst 3.579545 MHz 4.433618 MHz 3.575611 MHz 3.58256 MHz Frequency Color Burst 2.51 usec 2.26 usec 2.52 usec 2.51 usec ( 9 cycle ) ( 1 cycle ) ( 9 cycle ) ( 9 cycle ) CB porch 1. usec 1. usec 1. usec 1. usec Pre-equalize 6 pulses 5 pulses 6 pulses 5 pulses Low width 2.35 usec 2.35 usec 2.35 usec 2.35 usec High width 29.43 usec 29.65 usec 29.43 usec 29.65 usec Serration 6 pulses 5 pulses 6 pulses 5 pulses Low width 27.1 usec 27.3 usec 27.1 usec 27.3 usec High width 4.7 usec 4.7 usec 4.7 usec 4.7 usec Post-equalize 6 pulses 5 pulses 6 pulses 5 pulses Low width 2.35 usec 2.35 usec 2.35 usec 2.35 usec High width 29.43 usec 29.65 usec 29.43 usec 29.65 usec Table 16-2 National TV Signal Standard 146 CONFIDENTIAL Advanced Digital Chips, Inc

Ver 1.6.7 LCD Controller Block Diagram LCD Controller 는 Register, Timing Generation, Address Generation, FIFO Control, Sync Control, Request Generation, External Sync Detector 블록등으로구성되어있다. LCD Controller 는 Screen Refresh 를위하여, 프레임메모리의데이터를읽어오기위하여 Request Generation, Request Address Generation, FIFO Control 블록이있으며, VGA 모드를위한 Sync Control 블록이있다. Timing Generation 블록은 LCD Controller 의전반적인 Timing 을제어한다. External Video Decoder ( H / V Sync ) External Sync. Detector Interrupt Reg. R/W Ctrl. Signal (AMBA Interface) REG Timing Gen. SYNC. Ctrl Address Gen. TV/Monitor Control Signal Video Data Address FIFO Ctrl. Signal & Video Data FIFO Ctrl. Request ctrl Video Data Request Decoder Input Video Data (YCbCr -> RGB Internal Conversion) Overlay ctrl Video Data Mux DAC RGB Analog RGB Analog CVBS Figure 16-1 LCD Controller Block Diagram Advanced Digital Chips, Inc. CONFIDENTIAL 147

Ver 1.6.7 - Address Generation Address Generation 블록은 Screen Refresh 를위한 Memory Read Request Address 를생성한다. User 에의해셋팅된 LCD Base Address 에내부적으로해당모드에따른 offset address 가더해져서생성된다. - FIFO / Request Control FIFO Control 블록은내부 FIFO 의 Read Request 및 Write, Read Pointer 를제어한다. Read Request 및 Write, Read Pointer 는 Horizontal Active 구간의끝나는시점에서 Reset 된다. FIFO Control 블록은두개의 Clock Domain 을갖는다. 프레임메모리로부터읽어온데이터를 FIFO 에 Write 하는 System Clock Domain 과 FIFO Data 를읽어 Screen 에디스플레이하기위한 Video(Dot) Clock Domain 으로되어있다. FIFO 의 Write/Read Data Bus 는 32 Bit 이며, Control 레지스터 [16] Bit 에의해 <16 or 24> Bit per Pixel(RGB) Color 모드를선택할수있으며, 초기값은 RGB 16 Bit(5:6:5 Format) Color 모드로되어있다. 만약 RGB 16 Bit(5:6:5 Format) Color 모드를선택한다면, 한번의 FIFO Write/Read 동작에 2 Pixel 을처리하게되며, 32 Bit 중하위 [15:] 16 Bit, 상위 [31:16] 16 Bit 순으로디스플레이된다. 1 Pixel 은 16 Bit 이며 R 값이 [15:11], G 값이 [1:5], B 값이 [4:] 순으로되어있다. Control 레지스터 [16] Bit 에 1 을셋팅하여 RGB 24 Bit(8:8:8 Format) Color 모드를선택한다면, 한번의 FIFO Write/Read 동작에 1 Pixel 을처리하게되며, 32 Bit 은 { Dummy 8 Bit[31:24], R[23:16], G[15:8], B[7:] } 로구성된다. LCD Control 레지스터 [18:17] Bit 에따라, 매라인 Horizontal Active 구간에서 FIFO 의 Read Pointer 를체크하여프레임메모리비디오데이터 Read 에대한 Request 신호가발생한다. 이 Bit 이, 11 일때는 FIFO 가절반비었을때, 1 일때는 4 분의 1 이비었을때, 1 일때는 8 분의 1 이비었을때 Request 신호가발생한다. 그리고, 매라인 Horizontal HSYNC 구간에서 FIFO 는, LCD Control Register [18:17] Bit 에따라,, 11 일때는 Full, 1 일때는절반, 1 일때는 4 분의 1 이채워진다. 내부 FIFO 는 256 x 32 로되어있다. Figure 16-2 LCD FIFO Control Block RGB 16 Bit(5:6:5) Format Operation - Serialization Block 148 CONFIDENTIAL Advanced Digital Chips, Inc