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1 Patterson & Hennessy 이책을공부하면 ; 컴퓨터언어로프로그램을작성하는일에연관된보이지않는비밀, 즉 1) 컴퓨터의내부구조와 2) 그내부구조가컴퓨터프로그램에미치는영향 3) 나아가, 독자적으로컴퓨터를설계하는방법을 알게된다 Patterson : UC Berkeley Hennessy : Stanford Univ. ( 현스탠포드대학교총장, 구글이사 )

2 Why learn this stuff? You want to call yourself a computer scientist You want to build software people use (need performance) You need to make a purchasing decision or offer expert advice Both Hardware and Software affect performance: Algorithm determines number of source-level statements Language/Compiler/Architecture determine machine instructions (Chapter 2 and 3) Processor/Memory determine how fast instructions are executed (Chapter 5, 6, and 7) Assessing and Understanding Performance in Chapter 4

3 왜책의부제목이하드웨어 / 소프트웨어인터페이스인지? PH는현대적인컴구, 즉하드웨어와소프트웨어의연관성을인식하고연구해온대표적인사람 (1980년 RISC, 1984년 CMU 에서컴구배울때들음 ) 컴퓨터구조, 나아가모든컴퓨터의궁극적인목적은 일 즉, 응용프로그램을수행하는데있다. 인터넷 회사 / 오피스 게임 DivX 보기 블로그질 SW 설치한사람도모르는 / 잊어버린잡다한것 시스템소프트웨어 (OS, 컴파일러..) Instruction Set Architecture (x86, PowerPC, ARM/Xscale, 8051, TMS320C6000) : 컴구 HW 컴퓨터원리 : 눈에안보이는것 눈에보이는것 (HW 제조, 드라이버 )

4 Abstraction Delving into the depths reveals more information High-level language program (in C) swap(int v[], int k) {int temp; temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; } An abstraction omits unneeded detail, helps us cope with complexity What are some of the details that appear in these familiar abstractions? Assembly language program (for MIPS) C compiler swap: muli $2, $5,4 add $2, $4,$2 lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31 Assembler Binary machine language program (for MIPS)

5 Where we are headed 1장컴퓨터개요및관련기술 2장명령어 3장컴퓨터연산 4장성능을측정하고이해하기 5장프로세서 : 데이터패스및제어유닛 6장파이프라이닝에의한성능향상 7장크고빠르게 : 메모리계층구조 8장저장장치, 네트워크, 그리고다른주변장치 Key to a good grade: reading the book!

6 How do computers work? Need to understand abstractions such as: Applications software Systems software Assembly Language Machine Language Architectural Issues: i.e., Caches, Virtual Memory, Pipelining Sequential logic, finite state machines Combinational logic, arithmetic circuits Boolean logic, 1s and 0s Transistors used to build logic gates (CMOS) Semiconductors/Silicon used to build transistors Properties of atoms, electrons, and quantum dynamics 머리터지겠다!

7 Instruction Set Architecture (ISA) 컴퓨터구조의핵심, 컴퓨터를규정하는대표적인특성 프로그래밍의관점에서컴퓨터가이해 / 실행하는명령문의근간 특정 CPU( 마이크로프로세서 ) 에서구현된바이너리 ( 기계어 ) 명령문의집합 CISC, RISC, IA-32(x-86, 80x86, 386 부터 ), IA-64, PowerPC, PA-RISC (HP), SPARC (SUN), MIPS/R4000 (SGI, 임베디드, 헤네시설계 ), ARM, 신호처리프로세서 (DSP), 그래픽프로세서도특정한 ISA 를갖는특정목적의 CPU 라고생각할수있다. 컴퓨터계열을규정짓는지표 ( 인텔계열, 애플계열, ARM 계열등 ) 특정컴퓨터계열 ( 윈텔 ) 은기본적으로같은 ISA 또는시간이갈수록이전의 ISA를포함하면서점자로필요에따라새로운 Instruction을추가하는 Upward Compatibility를갖는다 만약이렇지않다면이전에나온프로그램은뒤에나온같은계열의컴퓨터에서구동이되지않을것이다

8 컴퓨터구조 주 1주컴퓨터구조용어 교수내용 수업형태수업 2주 컴퓨터구조발전역사및컴퓨터구조개요 3주 데이터표현, 명령어집합 (Instruction Set), 어셈블러, 컴파일러 4주 컴퓨터시스템의성능 5주 CPU 산술연산 6주 CPU 데이터통로및제어유닛 7주 파이프라이닝개관, 슈퍼스칼라 8주 중간고사 9주 메모리계층 - 캐쉬, RAM, 하드디스크, 플래시메모리 10 주 주변장치와의인터페이스 11 주 버스, 통신 수업수업수업수업수업수업시험수업수업수업 12 주클러스터구조 Linux Virtual Server 및 Google System 수업 13 주 임베디드시스템 14 주 유비쿼터스컴퓨팅 15 주 컴퓨터시스템을어떻게선정하여구성할것인가? 16 주 기말고사, 프로젝트발표 수업수업수업수업

9 Chapter 2

10 Instructions: Instruction : CPU의언어. C, JAVA와같은고급언어에비해매우단순함. e.g., no sophisticated control flow Very restrictive e.g., MIPS Arithmetic Instructions CPU 계열마다 Instruction Set은다르나공통적인 Instruction 들이많음 우리는여기서 MIPS instruction set architecture 공부함. similar to other architectures developed since the 1980's used by NEC, Nintendo, Silicon Graphics, Sony Other SPARC Hitachi SH PowerPC Motorola 68K MIPS IA-32 ARM

11 MIPS arithmetic All instructions have 3 operands Operand order is fixed (destination first) Example: C code: A = B + C MIPS code: add A, B, C (A B + C ) (A,B,C : Operand) add $s0, $s1, $s2 ( 컴파일러가할당 ) 레지스터 (Register) : CPU 내부에있는매우빠른기억장소 $s0, $s1, $s2 : 레지스터명 MIPS 는 32 개의 32bit 레지스터를갖고있음.

12 MIPS arithmetic Design Principle: 단순한것이좋다. 단순함은규칙성을요구한다. Of course this complicates some things... C code: a = b + c + d; MIPS code: add a, b, c add a, a, d Operands must be registers, only 32 registers provided Each register contains 32 bits Design Principle: 작은것이빠르다. Why?

13 Registers vs. Memory Arithmetic instructions operands must be registers, only 32 registers provided Compiler associates variables with registers What about programs with lots of variables Control Input Memory Datapath Output Processor I/O

14 Memory Organization Viewed as a large, single-dimension array, with an address. A memory address is an index into the array "Byte addressing" means that the index points to a byte of memory bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data

15 Memory Organization Bytes are nice, but most data items use larger "words" For MIPS, a word is 32 bits or 4 bytes bits of data 32 bits of data 32 bits of data 32 bits of data Registers hold 32 bits of data bytes with byte addresses from 0 to words with byte addresses 0, 4, 8, Words are aligned i.e., what are the least 2 significant bits of a word address?

16 Instructions MIPS 에서연산은레지스터에있는데이터들에게만적용된다 따라서메모리에있는데이터들을연산하려면이들을레지스터에옮겨오고또연산결과를다시메모리로옮겨야한다. 왜? 연산결과가계속레지스터에있으면메모리에있는데이터들의다른연산을수행하지못하므로 따라서레지스터 메모리간의데이터이동이필요하다 : Load, Store Load and store instructions : lw 레지스터명, 메모리위치 : 메모리위치 에서 레지스터명 의레지스터로데이터이송 sw 레지스터명, 메모리위치 : 레지스터에있는데이터를메모리위치로이동 BYTE Example: C code: MIPS code: A[12] = h + A[8]; lw $t0, 32($s3) add $t0, $s2, $t0 sw $t0, 48($s3) $s A A[0] Store word has destination last Remember arithmetic operands are registers, not memory! Can t write: add 48($s3), $s2, 32($s3) 32 A[8]

17 Our First Example Can we figure out the code? swap(int v[], int k); { int temp; temp = v[k] v[k] = v[k+1]; v[k+1] = temp; } swap: muli $2, $5, 4 add $2, $4, $2 lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31

18 So far we ve learned: MIPS loading words but addressing bytes arithmetic on registers only Instruction Meaning add $s1, $s2, $s3 $s1 = $s2 + $s3 sub $s1, $s2, $s3 $s1 = $s2 $s3 lw $s1, 100($s2) $s1 = Memory[$s2+100] sw $s1, 100($s2) Memory[$s2+100] = $s1

19 기계어 (Machine Language) : 인스트럭션이실제어떻게되어있나? Instructions, like registers and words of data, are also 32 bits long Example: add $t1, $s1, $s2 registers have numbers, $t1=9, $s1=17, $s2=18 Instruction Format: op rs rt rd shamt funct Can you guess what the field names stand for?

20 Machine Language Consider the load-word and store-word instructions, What would the regularity principle have us do? New principle: Good design demands a compromise Introduce a new type of instruction format I-type for data transfer instructions other format was R-type for register Example: lw $t0, 32($s2) ; I-Type op rs rt 16 bit number Where's the compromise?

21 Stored Program Concept Instructions are bits Programs are stored in memory to be read or written just like data Processor Memory memory for data, programs, compilers, editors, etc. Fetch & Execute Cycle Instructions are fetched and put into a special register Bits in the register "control" the subsequent actions Fetch the next instruction and continue

22 Control Decision making instructions alter the control flow, i.e., change the "next" instruction to be executed MIPS conditional branch instructions: bne $t0, $t1, Label beq $t0, $t1, Label Example: if (i==j) h = i + j; bne $s0, $s1, Label add $s3, $s0, $s1 Label:...

23 Control MIPS unconditional branch instructions: j label Example: if (i!=j) beq $s4, $s5, Lab1 h=i+j; add $s3, $s4, $s5 else j Lab2 h=i-j; Lab1: sub $s3, $s4, $s5 Lab2:... Can you build a simple for loop?

24 So far: Instruction Meaning add $s1,$s2,$s3 $s1 = $s2 + $s3 sub $s1,$s2,$s3 $s1 = $s2 $s3 lw $s1,100($s2) $s1 = Memory[$s2+100] sw $s1,100($s2) Memory[$s2+100] = $s1 bne $s4,$s5,l Next instr. is at Label if $s4 $s5 beq $s4,$s5,l Next instr. is at Label if $s4 = $s5 j Label Next instr. is at Label Formats: R I J op rs rt rd shamt funct op rs rt 16 bit address op 26 bit address

25 Control Flow We have: beq, bne, what about Branch-if-less-than? New instruction: slt $t0, $s1, $s2 if $s1 < $s2 then $t0 = 1 else $t0 = 0 Can use this instruction to build "blt $s1, $s2, Label" can now build general control structures Note that the assembler needs a register to do this, there are policy of use conventions for registers

26 Policy of Use Conventions Name Register number Usage $zero 0 the constant value 0 $v0-$v1 2-3 values for results and expression evaluation $a0-$a3 4-7 arguments $t0-$t temporaries $s0-$s saved $t8-$t more temporaries $gp 28 global pointer $sp 29 stack pointer $fp 30 frame pointer $ra 31 return address Register 1 ($at) reserved for assembler, for operating system

27 How about larger constants? We'd like to be able to load a 32 bit constant into a register Must use two instructions, new "load upper immediate" instruction lui $t0, filled with zeros Then must get the lower order bits right, i.e., ori $t0, $t0, ori

28 Assembly Language vs. Machine Language Assembly provides convenient symbolic representation much easier than writing down numbers e.g., destination first Machine language is the underlying reality e.g., destination is no longer first Assembly can provide 'pseudoinstructions' e.g., move $t0, $t1 exists only in Assembly would be implemented using add $t0,$t1,$zero When considering performance you should count real instructions

29 Other Issues Things we are not going to cover support for procedures linkers, loaders, memory layout stacks, frames, recursion manipulating strings and pointers interrupts and exceptions system calls and conventions Some of these we'll talk about later We've focused on architectural issues basics of MIPS assembly language and machine code we ll build a processor to execute these instructions.

30 Overview of MIPS simple instructions all 32 bits wide very structured, no unnecessary baggage only three instruction formats R I op rs rt rd shamt funct op rs rt 16 bit address J op 26 bit address rely on compiler to achieve performance what are the compiler's goals? help compiler where we can

31 Addresses in Branches and Jumps Instructions: bne $t4,$t5,label Next instruction is at Label if $t4 $t5 beq $t4,$t5,label Next instruction is at Label if $t4 = $t5 j Label Next instruction is at Label Formats: I J op rs rt 16 bit address op 26 bit address Addresses are not 32 bits How do we handle this with load and store instructions?

32 Addresses in Branches Instructions: bne $t4,$t5,label beq $t4,$t5,label Formats: Next instruction is at Label if $t4 $t5 Next instruction is at Label if $t4=$t5 I op rs rt 16 bit address Could specify a register (like lw and sw) and add it to address use Instruction Address Register (PC = program counter) most branches are local (principle of locality) Jump instructions just use high order bits of PC address boundaries of 256 MB

33 To summarize: MIPS operands Name Example Comments $s0-$s7, $t0-$t9, $zero, Fast locations for data. In MIPS, data must be in registers to perform 32 registers $a0-$a3, $v0-$v1, $gp, arithmetic. MIPS register $zero always equals 0. Register $at is $fp, $sp, $ra, $at reserved for the assembler to handle large constants. Memory[0], Accessed only by data transfer instructions. MIPS uses byte addresses, so 2 30 memory Memory[4],..., sequential words differ by 4. Memory holds data structures, such as arrays, words Memory[ ] and spilled registers, such as those saved on procedure calls. MIPS assembly language Category Instruction Example Meaning Comments add add $s1, $s2, $s3 $s1 = $s2 + $s3 Three operands; data in registers Arithmetic subtract sub $s1, $s2, $s3 $s1 = $s2 - $s3 Three operands; data in registers add immediate addi $s1, $s2, 100 $s1 = $s Used to add constants load word lw $s1, 100($s2) $s1 = Memory[$s ] Word from memory to register store word sw $s1, 100($s2) Memory[$s ] = $s1 Word from register to memory Data transfer load byte lb $s1, 100($s2) $s1 = Memory[$s ] Byte from memory to register store byte sb $s1, 100($s2) Memory[$s ] = $s1 Byte from register to memory load upper immediate lui $s1, 100 $s1 = 100 * 2 16 Loads constant in upper 16 bits branch on equal beq $s1, $s2, 25 if ($s1 == $s2) go to PC branch on not equal bne $s1, $s2, 25 if ($s1!= $s2) go to Conditional PC branch set on less than slt $s1, $s2, $s3 if ($s2 < $s3) $s1 = 1; else $s1 = 0 Equal test; PC-relative branch Not equal test; PC-relative Compare less than; for beq, bne set less than immediate slti $s1, $s2, 100 if ( $s2 < 100) $s1 = 1; else $s1 = 0 Compare less than constant jump j 2500 go to Jump to target address Uncondi- jump register jr $ra go to $ra For switch, procedure return tional jump jump and link jal 2500 $ra = PC + 4; go to For procedure call

34 C 프로그램이 CPU 에서프로세스로실행되기까지 :

35 Alternative Architectures Design alternative: provide more powerful operations goal is to reduce number of instructions executed danger is a slower cycle time and/or a higher CPI Sometimes referred to as RISC vs. CISC virtually all new instruction sets since 1982 have been RISC VAX: minimize code size, make assembly language easy instructions from 1 to 54 bytes long! We ll look at 80x86 (IA-32)

36 IA : The Intel 8086 is announced (16 bit architecture) 1980: The 8087 floating point coprocessor is added 1982: The increases address space to 24 bits, +instructions 1985: The extends to 32 bits, new addressing modes : The 80486, Pentium, Pentium Pro add a few instructions (mostly designed for higher performance) 1997: 57 new MMX instructions are added, Pentium II 1999: The Pentium III added another 70 instructions (SSE) 2001: Another 144 instructions (SSE2) 2003: AMD extends the architecture to increase address space to 64 bits, widens all registers to 64 bits and other changes (AMD64) 2004: Intel capitulates and embraces AMD64 (calls it EM64T) and adds more media extensions This history illustrates the impact of the golden handcuffs of compatibility adding new features as someone might add clothing to a packed bag an architecture that is difficult to explain and impossible to love

37 IA-32 Overview Complexity: Instructions from 1 to 17 bytes long one operand must act as both a source and destination one operand can come from memory complex addressing modes e.g., base or scaled index with 8 or 32 bit displacement Saving grace: the most frequently used instructions are not too difficult to build compilers avoid the portions of the architecture that are slow what the 80x86 lacks in style is made up in quantity, making it beautiful from the right perspective

38 IA-32 Registers and Data Addressing Registers in the 32-bit subset that originated with Name 31 0 Use EAX GPR 0 ECX GPR 1 EDX GPR 2 EBX GPR 3 ESP GPR 4 EBP GPR 5 ESI GPR 6 EDI GPR 7 CS SS DS ES FS GS Code segment pointer Stack segment pointer (top of stack) Data segment pointer 0 Data segment pointer 1 Data segment pointer 2 Data segment pointer 3 EIP EFLAGS Instruction pointer (PC) Condition codes

39 IA-32 Register Restrictions Registers are not general purpose note the restrictions below

40 IA-32 Typical Instructions Four major types of integer instructions: Data movement including move, push, pop Arithmetic and logical (destination register or memory) Control flow (use of condition codes / flags ) String instructions, including string move and string compare

41 IA-32 instruction Formats Typical formats: (notice the different lengths) a. JE EIP + displacement JE Condition Displacement b. CALL 8 32 CALL Offset c. MOV EBX, [EDI + 45] MOV d w r/m Postbyte Displacement d. PUSH ESI 5 3 PUSH Reg e. ADD EAX, # ADD Reg w Immediate f. TEST EDX, # TEST w Postbyte Immediate

42 Summary Instruction complexity is only one variable lower instruction count vs. higher CPI / lower clock rate Design Principles: simplicity favors regularity smaller is faster good design demands compromise make the common case fast Instruction set architecture a very important abstraction indeed!

INTRO Basic architecture of modern computers Basic and most used assembly instructions on x86 Installing an assembly compiler and RE tools Practice co

INTRO Basic architecture of modern computers Basic and most used assembly instructions on x86 Installing an assembly compiler and RE tools Practice co Basic reverse engineering on x86 This is for those who want to learn about basic reverse engineering on x86 (Feel free to use this, email me if you need a keynote version.) v0.1 SeungJin Beist Lee beist@grayhash.com