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Allegro SI/PDN(Power Delivery Network) Analysis Allegro Package Designer(APD) / SiP 오늘날 PCB 설계는 점점 더 Highspeed design이 요구 되고 있으며, 이런 추세 때문에 PCB 설계가 이미 완성된 이후의 board의 critical signal의 해석은 그 해석 시점상 문제 가 되고 있다. 이런 문제를 해결 하고자, schematic을 작성하는 단계에서의 Pre-SI를 통한 회로의 동작 검증, 그리고 PCB 설계 단계에서의 PCB 기반의 Post-SI를 통한 신 호의 무결성을 확인하고, 아울러 board 전체의 안정성을 높이고자 하는 SI의 필요성이 점점 커져가고 있다. Allegro PCB SI은 schematic 기반의 회로의 전기적 특성을 시뮬 레이션 할 뿐만 아니라, PCB 기반의 다양한 parameter를 고려한 시뮬레이션을 하여 보 다 정확하고 신뢰도 높은 PCB 설계를 하기 위한 통합 디자인 환경을 제공한다. SI(Signal Integrity) SigXP/SigWave 회로도 작성을 위한 Design Entry HDL, PCB 설계를 위한 Allegro PCB Editor, 시뮬레이션 시 필요한 각 소자의 전기적 model을 Manager하는 Model Integrity, 회로 topology 추출 및 해석을 위한 SigXP, 시뮬레이션 결과를 파형으로 보여주는 Sigwave, 시뮬레이 션 결과를 board에 효율적으로 반영할 수 있게 해주는 Constraint Manager 등의 tool이 서로 interface 하여 데이터를 주고 받으면 신 뢰도 높은 시뮬레이션 결과를 제공 - SigXP는 시뮬레이션을 원하는 critical signal을 Xnet(Extended net) 기반으로 추출하며, Differential signal은 Differential signal 형 태로 추출 - 여러 형태의 시뮬레이션 결과를 확인할 수 있으며, 그 결과를 SigWave를 통하여 파형으로 확인 PDN Analysis Model Integrity 시뮬레이션에 각 소자들의 전기적 특성을 포함하고 있는 model들을 생성/편집/검증 할 수 있도록 도와주는 tool로 다양한 종류의 시뮬레 이션 model을 DML (cadence device model library) 형태로 변경 2 - PDN Analysis를 통해 Board Power 안정화를 위한 효과적인 Decoupling Capacitor의 선택 및 효율적인 배치 분석 - 공진 주파수, IR-Drop, Power Bounce 등의 결과에 따른 PreLayout Feedback - VRM 및 Noise Source - 3D Visualization
Wire-bonding Die pad와 Bond pad를 연결하기 위한 Wire-bonding 작업은 다양 한 들과 Wire의 pattern을 이용하여 쉽게 작업 Allegro Package Designer (APD) - Cadence에서는 Package를 설계할 수 있도록 Allegro 기반의 설 계 tool을 제공 - Allegro PCB Editor 환경에 익숙한 사용자들에게 Package 설계 에 쉽게 활용 Dynamic Timing Display Propagation Delay / Relative Propagation Delay Constraint를 갖고 있는 Net에 대해서 해당 Constraint에 맞게 설계가 될 수 있도록 배 선 시 Color로 확인 Below Minimum Above Maximum - Cadence 3D Viewer를 통해 Package Designer에게 설계 중인 package의 입체형태 Within Tolerance 관련 제품 OrCAD PCB SI Allegro PCB SI/PI Allegro Package Designer Allegro Package SI SiP Digital Layout SiP Digital SI - APD는 기존의 Allegro 사용자에게는 친숙한 형태의 UI를 제공 3
Sigrity Product PowerSI PowerDC PowerSI는 향상된 Signal & Power Integrity 및 design-stage EMI solution tool입니다. S-parameter model extraction 및 IC package와 PCB design 전반에서 강력한 frequency domain simulation 환경을 제공합니다. PowerDC는 IC package와 PCB design에서의 electrical/thermal co-simulation을 통해 정밀도를 최대화한 효율적인 DC sign-off solution입니다. IR drop이나 current hot-spot을 신속히 찾아낼 수 있으며 최적의 remote sense 위치를 자동적으로 찾아냅니다. 4
OptimizePI Speed2000 OptimizePI는 고도로 자동화된 board와 IC package의 AC frequency analysis solution입니다. layout 전/후 decap 연 구와 임피던스 이슈를 확인합니다. decap의 수행은 최적화된 performance와 cost를 충족시킬 수 있습니다. SPEED2000은 Signal & Power Integrity 및 design-stage EMI analysis를 위한 포괄적인 PCB/package layout 기반의 time domain EM 시뮬레이션 툴 입니다. Speed 2000은 design signoff와 debug를 해결하기 위한 Layout 검사를 지원합니다. 5
SystemSI PowerSI 3D-FEM SystemSI는 포괄적이고 자동화된 signal integrity 환경을 위해 고 속 chip-to-chip system design의 정밀한 평가를 수행하며, 강력 한 parallel bus 와 serial link 호환 환경을 제공합니다. PowerSI 3D FEM은 PowerSI에 내장된 full-wave solver로 복 잡한 3D 구조의 정밀한 분석이 가능합니다. PowerSI 3D FEM 은 IC package 와 PCB 구조 해석의 맞춤형 툴입니다. Adaptive meshing을 통해 정확하고 빠른 분석 능력을 보장합니다. 6
XtractIM XcitePI XtractIM은 IC Package RLC의 빠른 extraction과 평가 solution으 로 높은 정확도의 broadband model을 생성할 수 있는 옵션을 가 지고 있습니다. BGA, SiP 및 leadframe design을 포함한 광범위한 Package type을 지원합니다. XcitePI는 chip/system co-design application을 목적으로 하는 full-chip power integrity solution 입니다. XcitePI는 초기 chip power 플랜, IO 및 core model extraction 할 수 있으며 time / frequency domain 시뮬레이션을 수행합니다. 7
Broadband Spice Transistor-to-behavioral Model Conversion (T2B) Broadband spice는 S-parameter checking, tuning과 extraction 기능의 연합으로 N-port network parameter를 SPICE 호환 회로 로 바꿔주어 time domain Simulation에서 사용 할 수 있습니다. T2B는 transistor를 behavior model로 conversion 하는 것은 효율 적인 방법으로 SSO와 다른 simulation에 대해 정확한 model를 만 들어 줍니다. 이러한 model들은 original transistor model 보다 수 십 배 더 빠르게 수행합니다. 8
Parallel Computing 4-Pack Voltus Sigrity Parallel Computing 4-Pack은 디자이너가 4개의 다른 컴 퓨터에서 병렬 computing 작업을 실행할 수 있는 라이선스입니다. PCB의 Model을 추출하는데 3배의 스피드 향상을 기대할 수 있어 제품 제작 시간을 단축시킬 수 있습니다. 현재 PowerSI와 3D-EM 에서 사용 가능합니다 Voltus IC Power Integrity는 full chip, cell-level power signoff Tool 입니다. Voltus는 디자이너에게 debugging, IC chip 전력 소 모의 확인 및 수정, IR Drop, EM constraints 및 violations에 대해 정확하고 빠르고 대용량 분석 및 최적화 기술을 제공합니다. PowerSI and 3D-EM support accelerating analysis time through multiple licenses - Prior to Sigrity 2015, additional Licenses of PowerSI and 3DEM needed to be purchased With Sigrity 2015, we now have Sigrity parallel Computing 4-packs available as a licensing option - 4-packs can be used with any tool that supports parallel computing - Currently PowerSI and 3D-EM only Multi-Computer computation is supported for adaptive meshing and discrete frequency solution Performance improvement for adaptive meshing - Speedup with two computers is approximately 1.5X - Speedup with N computers is approximately 0.6N to 0.7N - Speedup with a 4-pack is typecally greater than 3X Power Integrity Chip centric analysis - Package-aware static rail analysis (Voltus + XtractIM) - Package-aware dynamic rail analysis (Voltus + XtractIM) - Die model validation (Voltus + XtractIM) - Thermal-aware power analysis (Voltus + PowerDC) Package centric analysis - DC (IR drop) analysis with die model (Voltus + PowerDC) - AC analysis (impedance) with die model (XcitePI + PowerSI) - Transient analysis with die model (Voltus + Speed2000) - Thermal analysis with die model (Voltus + PowerDC) 9
Allegro Design Authoring (Concept HDL) Base Plus s Features Feature Flat, Hierarchical Schematic Creation Page Navigation, Management, Hierarchy Viewer Variant Editor Project Manager Cross Referencer Archiver Design Differences Properties Worksheet, Differential Pair Worksheet Support for Net Classes User Customization Part Manager Bill-of-Materials Generator Physical Design Reuse, Hierarchical Block Reuse Import Blocks and Sheets Copy Projects or Copy/Paste Within and Between Designs Check Plus Rules Checker Verilog and VHDL Netlisting AMS Integration Build Physical Wizard for Xilinx, Actel, Altera Customizable Menus, Custom Commands Using SKILL Cross-Probing with PCB Editor Electrical Constraints Sets Physical, Spacing Constraints Same Net Spacing High-Speed Model Assignment SigXp Topology Editor Allegro Viewer Plus Component Revision Manager Manage Shared Area Assign, Notify Teams Dashboard View of Blocks in the Project Merge / Split Blocks Locking Out-of-Date Check Table / Spreadsheet-Based Design Creation Design Authoring Schematic Block Reuse Import Verilog Netlist from Existing Design Quick Connectivity Creation Functions Import Connectivity using Text Format Online Packaging Associated Components Schematic Generation for Multi-Style Designs Import Verilog Custom Reports TCL Support for Scripting and Extensions Allegro Design Authoring High-Speed High-Speed High-Speed High-Speed High-Speed High-Speed High-Speed Team Design Team Design Team Design Team Design Team Design Team Design Route-Aware Automatic FPGA Pin Assignment FPGA System Planner Automatic Symbol, Schematic Creation for FPGA Sub-System FPGA System Planner Custom-Board ASIC Prototyping with FPGAs FPGA ASIC Prototyping Create and Publish Intelligent PDFs Design Publisher 10
Allegro PCB Designer Base Plus s Features Feature Allegro Design Authoring Allegro Design Entry CIS Constraint-Manager: Physical, spacing and samenet rules Constraint Manager: Properties and DRCs Constraint Manager: Differential pair rules Constraint Manager: Region rules Floorplanning, placement, placement replication DFA, DFF, DFT Dynamic feedback on DFA compliance during placement IDF3.0, DXF in/out EDMD schema-based ECAD-MCAD co-design Native 3D viewer Hierarchical interconnect flow planning Length-based rules for high-speed signals Constraint-driven flow for length-based high-speed signals Match groups, layer sets, extended nets T-point rules (pin to T-point) 6-layer automatic shape-based autorouter High-speed rules-based autorouting Layer-specific rules-based autorouting Design planning - plan spatial feasibility analysis and feedback Design planning - generate topological plan Design planning - Convert Topological plan to traces (CLINES) Constraint Manager: Electrical rule set (relection, timing, crosstalk) Constraint-driven flow using electrical rules Electrical constraint rule set (ECSets) / topology apply Formula and relationship based (advanced) constraints Backdrilling Die2Die pin delay, dynamic phase control, Z-axis delay Return path management for critical signals Constraint Manager: HDI rule set Micro-via and associated spacing, stacking, and via-in-pad rules Constraint-driven HDI design flow Manufacturing rule support for embedding components Embedd components on inner layers HDI micro-via stack editing Dynamic shape-based filleting, line fattening, and trace filleting Hug contour routing (Flex) Support for cavities on inner layers Concurrent team design - layer by layer partitioning Concurrent team design - functional block partitioning Concurrent team design - team design dashboard Concurrent team design - soft nets Parameterized RF etch elements editing Asymmetrical clearances Bi-directional interface with Agilent ADS Import Agilent ADS schematics into DE-HDL Layout-driven RF design creation Flexible Shape Editor Allegro PCB Designer Design Planning Design Planning Design Planning PCB High-Speed PCB High-Speed PCB High-Speed PCB High-Speed PCB High-Speed PCB High-Speed PCB High-Speed PCB Team Design PCB Team Design PCB Team Design PCB Team Design PCB Analog / RF PCB Analog / RF PCB Analog / RF PCB Analog / RF PCB Analog / RF PCB Analog / RF 11
Feature 256-layer Autorouting DFM rules-based autorouting Automatic trace spreadiing ATP generation Layer-specific rules-based autorouting Allegro PCB Designer PCB Routing PCB Routing PCB Routing PCB Routing PCB Routing Cadence is transforming the global electronics industry through a vision called EDA360. With an application-driven approach to design, our software, hardware, IP, and services help customers realize silicon, SoCs, and complete systems efficiently and profitably. www.cadence.com 2011 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, and Allegro are registered trademarks of Cadence Design Systems, Inc., All rights reserved. 22173 05/11 MP/MV/DM/PDF 12
Allegro Sigrity SI Product Summary Sigrity products Allegro Sigrity SI Base Power-Aware SI System Serial Link Broadband SPICE Transistor to Behavioral Model Conversion Package Assessment/ Extraction CAD Design/Data Translators PowerDC PowerSI 3D EM Full-Wave Extraction PowerSI SPEED2000 SystemSI - Serial Link Analysis SystemSI - Parallel Bus Analysis XtractIM Note: An option license provides access to one product at a time Sigrity products Allegro Sigrity SI Base Power-Aware SI System Serial Link IBIS 5.1 support Package Assessment/ Extraction Graphical topology editor Bus-level topology editor Generate estimated crosstalk tables Detailed HTML simulation reports Differential pair extraction from Allegro Design canvas Differential pair extraction from Allegro Design Entry HDL Multi-terminal black boxes in topologies 13
Sigrity products Post-layout selection from Allegro PCB Editor Allegro Sigrity SI Base Power-Aware SI System Serial Link HSPICE interface Differential signal constraint capture Sweep simulations Constraint development and capture of topologies Constraint-driven floorplanning and placement Allegro Constraint Manager Color-coded real-time feedback on violations Spectre transistor-level model support Source-synchronous bus analysis SSN analysis Batch simulation Constraint-driven routing Allegro route by pick Thermally-aware static IR drop analysis Time domain simulation of S-parameters Coupled via model generator for pre-layout explorations High-capacity channel simulation Optimum pre-emphasis bit configurations ( tap settings ) BER prediction Bathtub curves Channel compliance statistical analysis 2D (static and full-wave) extraction Package Assessment/ Extraction Hybrid-solver (2D/3D) extraction 3D full-wave extraction Signal-quality screening of routed nets Impedance requirements calculator Frequency domain analysis Cadence Design Systems enables global electronic design innovation and plays an essential role in the creation of today s electronics. Customers use Cadence software, hardware, IP, and expertise to design and verify today s mobile, cloud and connectivity applications. www.cadence.com 2013 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, Allegro and Broadband SPICE are registered trademarks and Sigrity, PowerDC, PowerSI, SPEED2000, SystemSI, and XtractIM are trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders. 1595 10/13 SA/DM/PDF 14
Allegro Sigrity SI Product Summary Sigrity products Allegro Sigrity PI Base Signoff and Optimization Package Assessment/ Extraction Note: An option license provides access to one product at a time CAD design/data translators PowerDC technology PowerSI technology PowerSI 3D EM Full-Wave Extraction OptimizePI technology XtractIM technology Allegro Sigrity SI Feature Summary Sigrity products Allegro Sigrity PI Base Signoff and Optimization Static DC IR drop analysis with DRC marker back-annotation Package Assessment/ Extraction IBIS 5.1 support Graphical topology editor Bus-level topology editor Detailed HTML simulation reports Post-layout selection from Allegro PCB Editor HSPICE interface Constraint-driven floorplanning and placement Allegro Constraint Manager Real-time feedback on decoupling capacitor placement violations Constraint-driven routing Allegro route by pick Thermally aware static IR drop analysis AC analysis of PCB and IC package PDNs Decoupling capacitor optimization of cost vs. performance Hybrid-solver (2D/3D) extraction 3D full-wave extraction Signal-quality screening of routed nets Frequency domain analysis Cadence Design Systems enables global electronic design innovation and plays an essential role in the creation of today s electronics. Customers use Cadence software, hardware, IP, and expertise to design and verify today s mobile, cloud and connectivity applications. www.cadence.com 2014 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, and Allegro are registered trademarks and Sigrity, PowerDC, PowerSI, OptimizePI, SystemSI, and XtractIM are trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders. 3636 12/14 CY/DM/PDF 15
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