진공이야기 3권 1호-최종(내지).indd

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1 Trend and issues of the bulk FinFET Jong-Ho Lee and Kyu-Bong Choi FinFETs are able to be scaled down to 22 nm and beyond while suppressing effectively short channel effect, and have superior performance compared to 2-dimensional (2-D) MOSFETs. Bulk FinFETs are built on bulk Si wafers which have less defect density and lower cost than SOI(Silicon-On-Insulator) wafers. In contrast to SOI FinFETs, bulk FinFETs have no floating body effect and better heat transfer rate to the substrate while keeping nearly the same scalability. The bulk FinFET has been developed at 14 nm technology node, and applied in mass production of AP and CPU since In the development of the bulk FinFETs at 10 nm and beyond, self-heating effects (SHE) is becoming important. Accurate control of device geometry and threshold voltage between devices is also important. The random telegraph noise (RTN) would be problematic in scaled FinFET which has narrow fin width and small fin height. 1. 서론 Scaling-down을위한 FinFET의개발 16

SOI FinFET 과벌크 FinFET [Fig. 2] Cross-sectional SEM picture of fin.

2 [Fig. 1] SOI FinFET typical layout and schematic cross sectional structure. Cross-sectional SEM picture of 15 nm Si vertical fin. The height is 50 nm [8, 9]. 2. SOI FinFET 과벌크 FinFET [Fig. 2] Cross-sectional SEM picture of fin. I D-V GS characteristics with respect to the body biases. The inset shows the Fin Channel region only tied to the Si substrate [11]. 17

3 [Fig. 3] 14. ID-VGS curves of 14 nm bulk (circle) and SOI (square) FinFETs. The junction-to-junction length in this figure is 14 nm. The fin height and source/drain junction depth are 100 nm, respectively. Solid and open symbols represent the curves for the V DS values of 0.9 V and 0.05 V, respectively. The fin body is uniformly doped with a concentration of 2x10 17 cm -3. Gate oxide thickness is 1 nm [13]. [Fig. 4] Temperature contour in cross-sectional views of the fin body, cut along the channel length, when the 14 nm FinFET is turned on. The temperature contours in SOI FinFETs are shown with BOX thickness from 300 nm to 20 nm, and are compared to contour of the bulk FinFET (left most). The arrows in the cross-sectional of SOI FinFET indicate the thickness of the BOX [13]. 3. 벌크 FinFET의주요기술동향및이슈 18

path [29]. [Fig. 5] Cross-sectional SEM picture of transistor Fin and Gate.

4 [Fig. 6] Rth from 14 nm to 7 nm node ina single fin structure. Rth icreases monotonically in Si-channel due to reduced heat dissipation path [29]. [Fig. 5] Cross-sectional SEM picture of transistor Fin and Gate. I D-VGS characteristics of NMOS and PMOS at VD = 0.05 and 0.7 V respectively [23]. 19

It increases the gate over drive (V G-V th) to the channel, resulting in increased I ON [29].

5 [Fig. 7] I ON and V th as a function of 1/T. PMOS shows more sensitive temperature dependence of V th compared to NMOS. It increases the gate over drive (V G-V th) to the channel, resulting in increased I ON [29]. [Fig. 8] Dependence of ΔI D on W fin and H fin. Contours of current density on the cross-sectional view cut across the fin body. Here, the H fin and W fin are 4 nm [30] 4. 맺음말 20

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jaeryomading review.pdf

jaeryomading review.pdf 4 5 6 7 8 9 10 11 12 13 1. S. Kim, H. Y. Jeong, S. K. Kim, S. Y. Choi and K. J. Lee, Nano Lett. 11, 5438 (2011). 2. E. Menard, K. J. Lee, D. Y. Khang, R. G. Nuzzo and J. A. Rogers, Appl. Phys. Lett. 84,