9 hamks@dongguk.ac.kr
: Source code Assembly language code x = a + b; ld a, %r1 ld b, %r2 add %r1, %r2, %r3 st %r3, x (Assembler) (bit pattern) (machine code) CPU security (code generator).. (Instruction Format) opcodeoperand opcode ( ) operand ( ) 0, 1, 2, 3operand : opcode opcode dst opcode src dst opcode src1 src2 dst
(Instruction Execution) CPU : PC < while ( PC!= ) { execute ( MEM[PC]); ; fetch (fetch), PC decode (decode) operand fetch execute store 24 ( ),,, 2 01234567 0 8 15 0 8 16 24 31 0 8 16 24 32 40 48 56 63
(Instruction Set) load/store integer (jump ) (OS ) floating point vs (bit pattern) (symbolic representation) (assembler) : A 3,=F 1 RX 5A30B024(hex) 5A 3 B 024 0101 1010 0011 0000 1011 0000 0010 0100 5 A 3 0 B 0 2 4 : (11) (compiler): (statement) (1 ) (disassembler): AR AR R1,R2 AR 3,5 1A35 ; R3 = R3 + R5 SR 3,5 1B35 ; R3 = R3 R5 OR 7,4 1674 ; R7 = R7 Or R4 R 7,4 1474 ; R7 = R7 ad R4 XR 5,6 1756 ; R5 = R5 Xor R6 LR 3,6 1836 ; R3 = R6
L L R1,D2(X2,B2) L R1,D2(X2,B2) L 3,260(7,15) ; 5837F104 USIG *,15 ; (*) 15 ;. L 3,DATA1(7) ;DATA1 7 ; 4 ; 3. DATA1 DC F 10 ;DATA1 4 10 DC F 11 ;DATA1+4 4 11 DC F 12 ;DATA1+8 4 12 DC F 13 ;DATA1+12 4 13 DC F 14 ;DATA1+16 4 14 L 3,260(7,15) ST(STore) O(Or) A(Add) (ad) S(Subtract) X(Xor)
LM LM R1,R3,D2(B2) LM 4,7,FULL1 FULL1 DC F 1 ;R4 DC F 2 ;R5 DC F 3 ;R6 DC F 4 ;R7 I I D1(B1),I2 I KIMT+23,B 00001111 I(ad Immediate) OI(Or Immediate) XI(eXclusiveor Immediate) MVC D1(L,B1),D2(B2) PATA DC CL5 TIGER ; 5 TIGER PATB DC CL8 ELEPHAT ; 8 ELEPHAT MVC PATA,PATB PATA T I G E R PATA E L E P H PATB E L E P H A T PATB E L E P H A T
PATA DC CL5 TIGER ; 5 TIGER PATB DC CL8 ELEPHAT ; 8 ELEPHAT MVC PATB,PATA PATA T I G E R PATA T I G E R PATB E L E P H A T PATB T I G E R T I G ZAP D1(L1,B1),D2(L2,B2) 0 5 7 3 4 C 1 6 5 D ZAP VALUEA,VALUEB..... VALUEA DC C 2413 F 2 F 4 F 1 F 3 VALUEB DC PL3 165 0 0 1 6 5 D 0 0 0 0 1 6 5 D
RXBC mask,d2(x2,b2) RRBCR mask,r2 zero <zero >zero overflow 00 01 10 11 1000 0100 0010 0001 A 3,=F 1 BC B 1000,ZERO BC 4,LTZERO BC B 0010,GTZERO OVERFLOW... BC B 1111,COT ZERO... BC 15,COT LTZERO... BC B 1111,COT GTZERO... COT... 0000 1000 0001 1001 0010 1010 0011 1011 0100 1100 0101 1101 0110 1110 0111 1111 B BR BP BPR BM BMR BZ BZR BAL 14,SUBRT ;R14... ; SUBRT... SUBRT...... BCR 15,14 ;R14 BALR 14,10 ;R14 ;R10 BALR 14,0 ;R14 ;
EXAMPLE CSECT BALR 15,0 USIG EXAMPLE+2,15 L 2,FIVE L 3,TWETY5 SR 4,4 ITER L 5,UM(4) AR 5,3 ST 5,UM(4) A 4,FOUR S 2,OE BP ITER ITER L 5,UM(4) BR 14 AR 5,3 FIVE DC F 5 ST 5,UM(4) TWETY5 DC F 25 L 7,ITER FOUR DC F 4 A 7,FOUR OE DC F 1 ST 7,ITER UM DC F 50 L 7,ITER+6 A 7,FOUR DC F 45 ST 7,ITER+6 DC F 64 S 2,OE DC F 72 BP ITER DC F 69 ED EXAMPLE CSECT BALR BASE,0 0 BALR 15,0 USIG EXAMPLE+2,BASE L 2,=F 5 2 L 2,54(0,15) L 3,=F 25 6 L 3,58(0,15) SR 4,4 10 SR 4,4 ITER L 5,UM(4) 12 L 5,34(4,15) AR 5,3 16 AR 5,3 ST 5,UM(4) 18 ST 5,34(4,15) A 4,=F 4 22 A 4,62(0,15) S 2,=F 1 26 S 2,66(0,15) BP ITER 30 BC 2,10(0,15) BR 14 34 BCR 15,14 UM DC F 50 36 50 DC F 45 40 45 DC F 64 DC F 72 DC F 69 BASE EQU 15 ED 44 64 48 72 52 69 56 5 60 25 64 4 68 1 5854F022 16
EXAMPLE ITER UM BASE F 5 F 25 F 4 F 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 USIG EXAMPLE+2,15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Y 2 DROP 15 USIG EXAMPLE+520,11 1 2 3 4 5 6 7 8 9 10 11 Y 520 12 13 14 15 Y 2 (two pass) (pass) 1: (symbol definition) (pass) 2: (instruction assembly) (pass). 1, (type),, ( ) (mapping). 2 (assemble). (lc: location counter).. < > < > pass1(st) pass2(st)
1 void pass1(st) { unsigned lc = 0; while (not EOF) { ; 2 ; if ( ) lcst ; if ( POT ){ if (DS DC) {len = ; lclen ; if (EQU) ST ; if (ED) LT ; else { len = MOT ; LT ; lc += len; 2 1 void pass2(st) { unsigned lc = 0; while (not EOF) { ; if ( POT ){ if (DS DC) {len = ; lclen ; if (DC ) { if (USIG) BT ; if (DROP) BT? ; if (ED) LT ; if (EQU START) ; else if ( MOT ){ len = MOT ; ; if (RX ) { ; + = 3,4 if (RR ) { ; lc += len; ;
ADD32 CSECT ETRY DATA BEGI BALR BASE,0 USIG 2,BASE SR 4,4 L 3,FIVE LOOP L 2,DATA(4) A 2,THIRTY2 ST 2,DATA(4) A 4,FOUR S 3,OE BP LOOP BR 14 FIVE DC F 5 FOUR DC F 4 OE DC F 1 THIRTY2 DC F 32 DATA DS 5F BASE EQU 13 ED TEXT CARD 0 05D0 BALR 13,0 2 1B44 SR 4,4 4 5830 D022 L 3,34(0,13) 8 5824 D032 L 2,50(4,13) 12 5A20 D02E A 2,46(0,13) 16 5024 D032 ST 2,50(4,13) 20 5A40 D026 A 4,38(0,13) 24 5B30 D02A S 3,42(0,13) 28 4720 D006 BC 2,6(0,13) 32 07FE BCR 15,14 36 0000 0005 40 0000 0004 44 0000 0001 48 0000 0020 52 0000 0000 56 0000 0000 60 0000 0000 64 0000 0000 68 0000 0000
MAI CSECT EXTER ADD32 EXTER DATA BEGI BALR 15,0 USIG BEGI+2,15 L 3,=F 5 LOOP READ 3,ADATA L 4,AADD32 BALR 14,4 L 3,=F 5 WRITE 3,ADATA HALT ADATA DC A(DATA) AADD32 DC A(ADD32) ED TEXT CARD 0 05F0 BALR 15,0 2 5830 F022 L 3,34(0,15) 6 F030 F01A READ 3,26(0,15) 10 5840 F01E L 4,30(0,15) 14 05E4 BALR 14,4 16 5830 F022 L 3,34(0,15) 20 F130 F01A WRITE 3,26(0,15) 24 FF00 HALT 28 0000 0000 32 0000 0000 36 0000 0000 ESD CARD ADD32 SD 0 72 DATA LD 52 1 TEXT CARD 0 05D0 BALR 13,0 2 1B44 SR 4,4 4 5830 D022 L 3,34(0,13) 8 5824 D032 L 2,50(4,13) 12 5A20 D02E A 2,46(0,13) 16 5024 D032 ST 2,50(4,13) 20 5A40 D026 A 4,38(0,13) 24 5B30 D02A S 3,42(0,13) 28 4720 D006 BC 2,6(0,13) 32 07FE BCR 15,14 36 0000 0005 40 0000 0004 44 0000 0001 48 0000 0020 52 0000 0000 56 0000 0000 60 0000 0000 64 0000 0000 68 0000 0000 RLD CARD ED ESD CARD MAI SD 0 40 ADD32 ER 0 0 DATA ER 0 0 TEXT CARD 0 05F0 BALR 15,0 2 5830 F022 L 3,34(0,15) 6 F030 F01A READ 3,26(0,15) 10 5840 F01E L 4,30(0,15) 14 05E4 BALR 14,4 16 5830 F022 L 3,34(0,15) 20 F130 F01A WRITE 3,26(0,15) 24 FF00 HALT 28 0000 0000 32 0000 0000 36 0000 0000 RLD CARD 3 1 A 28 2 1 A 32 ED