ALTERA & MAX+PLUS II
ALTERA & ALTERA Device ALTERA MAX7000, MAX9000 FLEX8000,FLEX10K APEX20K Family MAX+PLUS II MAX+PLUS II 2
Altera & Altera Devices
4
ALTERA Programmable Logic Device Inventor of the EPLD in 1983 Programmable Logic Device families Product term(eprom) MAX3000A, MAX 7000/E/S/A/B, MAX 9000/A Look-up table(sram) FLEX 6000/A, FLEX 8000A, FLEX 10K/A/E Product term & Look-up table (SOC) APEX20K/E : MAX+PLUS II 5
MAX 7000 MAX7000 32 ~ 256 macrocells, 600 ~ 5,000 gates In-System Programmability(ISP) in MAX 7000S output slew-rate 2 global clocks, 6 output enable signals 3.3V or 5.0V protection 6
MAX7000 7
Macrocell MAX7000 8
MAX7000A MAX7000A 32 ~ 512 macrocells, 600 ~ 10,000 gates 3.3V in-system programmability(isp) Built in JTAG boundary-scan test(bst) circuitry Open-drain protection 3.3V 2.5V, 3.3V, 5V 9
FLEX 10K FLEX10K PLD 10,000 ~ 250,000 gates 6,144 ~ 40,960 RAM bits ICR, built-in JTAG, PCI compliant Clock-Lock and Clock-Boost Tri-State Enable 10
FLEX10K FLEX10K 10K -- 5V ( 10,000 ~ 100,000 typical gates) 10KV -- 3.3V ( 50,000, 130,000 typical gates) 10KA -- 3.3V ( 10,000 ~ 250,000 typical gates) 10KE -- 2.5V ( 30,000 ~ 250,000 typical gates) 10K -- 3.3V, 5V interface 10KV -- 3.3V, 5V interface 10KA -- 2.5V, 3.3V, 5V interface 10KE -- 2.5V, 3.3V, 5V interface 11
FLEX10K 12
Logic Element FLEX8000A 13
Embedded Array Block FLEX10K 14
APEX 20K APEX20K System-On-a-programmable-Chip(SOPC) PLD MultiCore (LUT, Product-T, Memory) 6 ~ 100 gates Up to 51,840 logic elements Up to 3,456 product-term-based macrocells Up to 442,368 RAM bits 1.8-V and 2.5V (LVDS,SSTL,GTL+) SignalTap signal : Quartus 15
APEX20K 16
MAX+PLUS II
MAX+plus II PC ( Windows 98 & ME, Windows NT 3.5 or higher ) UNIX Sun SPARCstation HP 9000 Series 700/800 workstation IBM RISC System /6000 workstation PC & UNIX Network 18
MAX+PLUS II MAX+PLUS II Manager Start-up window : : Project name, File name MAX+PLUS II menu : MAX+plus II Help menu : on-line-help 19 Status bar :
Questions about MAX+PLUS II? On-Line Help MAX+plus II MAX+plus II On-Line Help Help Menu MAX+PLUS II Applications AHDL, VHDL, VerilogHDL Libraries Devices and Programming Adapters Context-Sensitive Help (F1 or Shift+F1 or ) Menus Dialog boxes 20
MAX+PLUS II
22
23
Design MAX+PLUS II Graphic Text AHDL, VHDL, Verilog HDL 3rd party EDA tools EDIF(Electronic Design Interchange Format) OrCAD schematics Mixing LPM and Megafunctions 24
25
Graphic Schematic Symbols Net (wires) Symbols Net singal label Save, Save & check the design :.gdf Message Processor Symbol 26
Text Text VHDL Verilog HDL Save the design :.vhd(vhdl),.v(verilog HDL) 27
VHDL VHSIC Hardware Description Language 1987 and 1993 IEEE 1074 standard High-level hardware behavior description language Especially well-suited for large or complex designs Text Editor has VHDL Template and Syntax Color 28
29
MAX+PLUS II Process all design files associated with the project Files can be created with MAX+PLUS II or 3rd party EDA Tools Logic synthesis and place & route MAX+PLUS II or 3rd party EDA Tools 30
Functional Netlist Extractor.cnf netlist file. Database Builder node name database Functional SNF Extractor Functional.snf file 31
Timing Netlist Extractor.cnf netlist file Logic Synthesizer logic synthesis/minimization Design Doctor Partitioner and Fitter place & route algorithm Timing SNF Extractor Timing.snf file 32
Assignments Assignments Device assignments Pin assignments assignments Logic options architectural features Location assignments Lab, Row, Column, LC Clique Timing assignments Device Option assignments 33
Device Assignment Select Device Specific device Auto MAX+PLUS II 34
Pin Assignment Graphic or text source file Assign > Pin/Location/Chip Floorplan Editor. Highlight node and choose Assign Pin/Location/Chip Node name automatically entered in the Node Name field Choose pin or LCELL location then click on Add to enter assignment (Note: You must choose a specific device prior to this step) 35
Floorplan GUI view/create assignments Pins Logic cells Cliques Logic options Drag-and-drop pins/logic cells GUI Assignment assignment LAB view, external Device view 36
Floorplan (Read Only) Display control Highlighted LCELL Fan-in and Fan-out LCELL equation 37
Floorplan (Editable) 38
Start Button Message Processor Info Warning Error Start Compilation Messages 39
Device assignments Error summary Device pin-out diagram Resource utilization Pin LCELL Equations Compiler resources Compilation time Memory usage Report file 40
41
MAX+PLUS II Waveform Vector Functional synthesis functional. Timing sythesis logical & delay. 42
Run Functional Simulation Click on Start Button Output change on clock edge Open.scf file 43
Run Timing Simulation Output change after timing delay 44
45
MAX+PLUS II Delay Matrix MAX+PLUS II Floorplan Editor MAX+PLUS II Compiler Setup/Hold Matrix MAX+PLUS II Graphic Editor Registered Performance MAX+PLUS II Text Editor MAX+PLUS II Timing Analyzer 46
3 Registered Performance calculates fastest possible internal clock frequency Delay Matrix calculates combinatorial delays Setup/Hold Matrix calculates setup & hold times for device flipflops Design file Floorplan Editor 47
Registered Performance Analysis Source/Destination, Clock period and Frequency of the longest path are displayed List Paths clock delay path 48
Delay Matrix Analysis Matrix shows all paths, longest path, or shortest path depending on Time Restrictions option selected List Paths delay path 49
Setup/Hold Matrix Analysis Setup/Hold times are displayed with respect to the clocks 50
51
Altera LP6 ISA Bus Programming Card Master Programming Unit (PL-MPU) Stand-alone Programmer (PL-ASAP2 = LP6 + PL-MPU + S/W) Programming adapters ICR, ISP, JTAG Programming BitBlaster (Serial) ByteBlaster (Parallel) MasterBlaster (Serial/USB) Third-party ex. Data IO, BP Microsystems 52
53
54