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System-on-Chip Design Jong-Wha Chong Wireless Location and SOC Lab. Hanyang University

Agenda Introduction of SoC Technology Trend Technical SoC Challenges - Electronic System Level (ESL) Design - Low-Power Design - Design-For-Manufacturability (DFM) Closing Remarks 2

History of IT Industry D-TV Radio C-TV PC Internet HHP 1950~70 s 1980 s 1990 s 2000 s IMT2000 6.0 ~ 3.0um 2.0 ~ 1.0um 0.8 ~ 0.6um 0.5 ~ 0.25um 0.18 ~ 0.06 um 256K DRAM 4M DRAM 256M DRAM 8G NAND Transistor Logic IC 4 VLSI SOC

What is SoC? = SoC System + Chip MODEM R F CPU IMAGE MEMORY I/O Need expertise of System & Semiconductor Complete system in a single package 5

Inside SoC Hardware-independent Software Applications User defined Interface Libraries Hardware-Dependent Software Device Drivers Operating Systems (Kernel) Middle ware An IC dedicated to a specific application that contains a computation engine (microprocessor core, DSP core, MPEG core or graphics core), memory and logic on a single chip Hardware MPEG CPU Logic Cache Core [Gartner, 2003.2Q ] Analog DRAM ROM DSP 6

SoC Applications Media Players Home Entertainment SOC Mobile Communication Mobile Computing 7

Digital TV on SoC 2000 2001 ~ 2002 2003 ~ 2005 D-TV CPU A/V Decoder Format Converter Channel Decoder Channel EQ. TS OSGM 7Chip CPU A/V Decoder Format Converter Channel Decoder Channel EQ. TS OSGM 2Chip CPU A/V Decoder Format Converter Channel Decoder Channel EQ. TS OSGM 1Chip HDTV Channel EQ. HDTV Channel Decoder CPU MPEG2 TS MPEG2 A/V Decoder FORMAT Converter OSGM MPEG2 A/V Decoder HDTV Channel Decoder HDTV Channel EQ. CPU FORMAT Converter MPEG2 TS OSGM 8

Cellular Phone on SoC 2000 2001 ~ 2003 2004 ~ 2005 HHP (CDMA) MP3 BBA Modem RF Memory 5Chip Multimedia RF BBA Modem Memory 3Chip Multimedia RF BBA Modem Memory GPS 1Chip RF MP3 BBA Modem Memory Memory BBA RF Modem & GPS DSP MP3/ MPEG-4 CPU 9

CD-MP3 player on SoC ~2000 2001 ~ 2002 2003 ~ CD-MP3 player Digital Servo CD DSP Audio DAC MP3 Decoder ESP Digital Servo CD DSP Audio DAC MP3 Decoder ESP 3 Die 2 Die Digital Servo CD DSP Audio DAC MP3 Decoder ESP MCU RF 7Chip MCU RF 4Chip MCU RF 1Chip MCU Digital Servo CD DSP Audio DAC RF Digital Servo + CD DSP + Audio DAC MP3 Decoder + ESP MCU MP3 Decoder ESP RF 10

Data Processor RF DVD player on SoC ~2000 2001 ~ 2002 2003 ~ Data Processor Data Processor Data Processor Servo Servo 2 Die Servo CD-MP3 player MPEG2 Audio Decoder MPEG2 Video Decoder MPEG2 Audio Decoder MPEG2 Video Decoder MPEG2 Audio Decoder MPEG2 Video Decoder MCU MCU 3 Die MCU RF 6Chip RF 3Chip RF 1Chip Servo RF Data Processor + Servo MPEG2 A/V Decoder + MCU MCU MPEG2 A/V Decoder 11

SoC Market Vision 12

Key SoC Challenges Requirement Challenges High-Performance Design Technology Low power - System-Level Design - Low-Power Design Small Size Low-Cost Manufacturing Technology - DFM(Design-For-Manufacturability) / DFY(Design-For-Yield) Others in Nano Technology 13

Market Trend 15

Convergence of Mobile/Home Platforms Convergence will continue on each side of mobile/home platforms - Home platform case, IBS 2004. Television Set-top Box Consumer Electronics CE World Game console PC Information Tech. IT World IT vs. CE War! 16

Chip Architecture MPSoC w/ Reconfigurability Currently (90nm) 3G modem+ap+rf IC s HW CPU DSP Application Proc. RF IC 3G modem chip 5M gates, 100MHz, 250mW Application processor chip 15M gates, 500MHz, 500mW Reconf. HW In 2010 (45nm) Single MPSoC HW-S DSP s Multi CPU cores Multi-mode/band RF Multi-CPU 10M gates, +1GHz, 400mW HW-accelerated scalable (HW-S) multi- DSP 10M gates, +1GHz, 300mW Reconfigurable HW for SDR 10M gates, 100mW 17

Battery Capacity Requirement Low Power 2x / year increase in power efficiency! 18

Process Technology Scaling Vs. Cost 10M 100M 19

SubWavelength & Process Variation 20

Electronic System Level (ESL) Design Low-Power Design Design for Manufacturability (DFM) 21

abstract abstract abstract abstract abstract Evolution of Design Abstract Multi-core SoC with HW/SW virtual components SW SW communication HW Register-transfer-level model Gate-level model cluster Transistor model Platform with IP reuses cluster MCU MEM DSP IP IP IP SW models SW models SW models OS/Drivers MCU SW DSP On Chip Bus cluster SW tasks SW SW SW tasks tasks adaptor SW SW MCU adaptor adaptor core MCU MCU HW core core adaptor HW HW adaptor adaptor On Chip Network HW HW adator adator HW IP s IP s adator IP s cluster IP IP IP 1970 s 1980 s 1990 s 2000 s 2010+ 23

SoC Design and Verification Flow System Spec. System-level design HW-SW Co-Design System Design HW/SW Partitioning HW IP SW IP HW-SW Co- Verification Functional Verification HW Development SW Development Software Verification Gate-Level Verification HW refinement (UT->T->RTL) SW refinement (RTOS mapping) HW-SW codevelopment Gate Final code HW-SW co-development is important at early design stage. 24

ESL Definition Electronic System Level (ESL) design and verification is an emerging electronic design methodology that focuses on the higher abstraction level concerns first and foremost. It is defined in the ESL Design and Verification book [1] as: "the utilization of appropriate abstractions in order to increase comprehension about a system, and to enhance the probability of a successful implementation of functionality in a cost-effective manner." The basic premise is to model the behavior of the entire system using a high-level language such as C, C++, or MATLAB. Rapid and correct-by-construction implementation of the system can be automated using EDA and embedded software tools, although much of it is performed manually today. ESL can also be accomplished through the use of SystemC as an abstract modeling language. [1] Brian Bailey, Grant Martin and Andrew Piziali, ESL Design and Verification: A Prescription for Electronic System Level Methodology. Morgan Kaufmann/Elsevier, 2007. 25

ESL for SoC Electronic System Level is now an established approach at most of the world s leading System-on-a-chip (SoC) design companies, and is being used increasingly in system design. From its genesis as an algorithm modeling methodology with no links to implementation, ESL is evolving into a set of complementary methodologies that enable embedded system design, verification, and debugging through to the hardware/software implementation of custom SoC. Challenges Huge complexity (i.e., many heterogeneous IP modules) Configurable IP (used to avoid over design) adds another dimension of difficulty in verification and functional/code coverage Hardware/software co-development makes the integration harder especially early in the design flow 26

Need of Virtual Platform Relative Effort by Designer Role 250% 200% 150% 100% 50% Software Validation Physical Verification Architecture HW designer SW designer 0% 350nm 250nm 180nm 130nm 90nm IBS Nov. 2002 Architecture effort & Software costs!!!! Get HW/SW designers into a common playground!! Challenges Hardware and software co-verification Early development and verification of software Quantitative analysis and exploration of system architecture Executable spec for HW/SW/System designer Managing large scale SoCs Requirements Fast & Accurate Early Availability & Reusability 27

An Evolution of the Traditional Flow High Level Model Virtual Platform Co-Verification Consistent Verification Requirement Follow Up 28

Main Features of Virtual Platform Design methodology based on high-level design abstraction Captures the concept of platform-based design approach Emphasizes the systematic IP reuse The main features Modeled at transaction-level (TL) Architecture exploration and software development can happen early in design process Software designers can prepare fully-optimized and error minimized code before RTL design 29

What is TLM? (untimed) Functional Level Modeling executable specification (C/C++, Matlab, SystemC) can verify only algorithm or function UTFU TF UTF UTFU TF Transaction Level Modeling analyze SoC architecture early SW development can estimate timing/power accurately TL MT LM TL M TL M TL M Register-Transfer Level Modeling RTL/behavioral HW design and verification can simulate very accurately, but slow RTLR TL RTL RTL RTL At TLM, concerns only focus on mapping out data flow details: the type of data that flo ws and where it is stored 30

Basic of Transaction-Level Modeling Transaction RTL Req Grant Addr ctrl1/cmd1 Data ack0 ack1 Transaction : exchange of a data or an event between two components of a modeled and simulated system Module : structural entity, which contain processes, ports, channels, and other modules Channel : implements one or more interfaces, and serves as a container for communication functionality Port : object through which a module can access a channel s interface.

Abstraction Models Time granularity for communication/computation objects can be classified into 3 basic categories. Models B, C, D and E could be classified as TLMs. Communication A. "Specification model" "Untimed functional models" Cycletimed D F B. "Component-assembly model" "Architecture model" "Timed functional model" Approximatetimed C E C. "Bus-arbitration model" "Transaction model" D. "Bus-functional model" "Communication model" "Behavior level model" Untimed Untimed A B Approximatetimed Cycletimed Computation E. "Cycle-accurate computation model" F. "Implementation model" "Register transfer model" 32

A: Specification Model Objects - Computation -Behaviors - Communication -Variables B1 v1 = a*a; v1 B2B3 B2 v2 = v1 + b*b; B3 v3= v1- b*b; v2 v3 Communication Cycletimed D F B4 v4 = v2 + v3; c = sequ(v4); Approximatetimed C E Cycletimed Untimed A B Untimed Approximatetimed Computation 33

cv12 B: Component-Assembly Model Objects - Computation - Proc - IPs - Memories - Communication -Variable channels PE1 B1 v1 = a*a; PE2 cv11 PE3 B3 v3= v1- b*b; v3 B2 v2 = v1 + b*b; cv2 B4 v4 = v2 + v3; c = sequ(v4); Communication Cycletimed D F A B1 v1 = a*a; v1 Approximatetimed C E B2B3 B2 v2 = v1 + b*b; B3 v3= v1- b*b; v2 v3 Cycletimed Untimed A B Untimed Approximatetimed Computation B4 v4 = v2 + v3; c = sequ(v4); 34

cv12 C: Bus-Arbitration Model Objects - Computation - Proc - IPs (Arbiters) - Memories - Communication - Abstract bus channels PE1 B1 PE2 v1 = a*a; B2 v2 = v1 + b*b; PE4 (Arbiter) 3 cv12 1 cv2 2 cv11 1. Master interface 2. Slave interface 3. Arbiter interface PE3 B3 v3= v1- b*b; v3 B4 v4 = v2 + v3; c = sequ(v4); Communication PE1 Cycletimed D F B1 v1 = a*a; cv11 Approximatetimed C E B PE3 B3 v3= v1- b*b; PE2 v3 Cycletimed Untimed A B Untimed Approximatetimed Computation B2 v2 = v1 + b*b; cv2 B4 v4 = v2 + v3; c = sequ(v4); 35

PE1 B1 v1 = a*a; PE2 B2 v2 = v1 + b*b; PE4 (Arbiter) 3 address[15:0] address[15:0] data[31:0] data[31:0] 1 ready 2 e D: Bus-Functional Model Objects - Computation - Proc - IPs (Arbiters) - Memories - Communication - Protocol bus channels ack ready ack 1: master interface 2: slave interface 3: arbitor interface IProtocolSlav PE3 B3 v3= v1- b*b; v3 B4 v4 = v2 + v3; c = sequ(v4); Communication Approximatetimed Cycletimed Untimed Cycletimed A D C B F E Untimed Approximatetimed Computation PE1 B1 v1 = a*a; PE2 B2 v2 = v1 + b*b; PE4 (Arbiter) 3 cv12 cv2 1 2 cv11 1. Master interface 2. Slave interface 3. Arbiter interface C PE3 B3 v3= v1- b*b; v3 B4 v4 = v2 + v3; c = sequ(v4); 36

E: Cycle-Accurate Computation Model Objects - Computation - Proc - IPs (Arbiters) - Memories - Wrappers - Communication - Abstract bus channels PE1 MOV r1, 10 MUL r1, r1, r1... PE2 4 PE4 S0 S1 S2 S3 4 3 cv12 1 cv2 2 cv11 4 PE3 S0 S1 S2 S3 Communication MLA... r1, r2, r2, r1... 4 1. Master interface 2. Slave interface 3. Arbiter interface 4. Wrapper S4 Approximatetimed Cycletimed D C F E PE1 B1 v1 = a*a; PE4 (Arbiter) 3 cv12 PE3 C B3 v3= v1- b*b; Cycletimed Untimed A B Untimed Approximatetimed Computation PE2 B2 v2 = v1 + b*b; cv2 1 2 cv11 1. Master interface 2. Slave interface 3. Arbiter interface v3 B4 v4 = v2 + v3; c = sequ(v4); 37

address[15:0] address[15:0] data[31:0] data[31:0] ready ack ready ack e F: Implementation Model Objects - Computation - Proc - IPs (Arbiters) - Memories - Communication -Buses (wires) interrupt req PE4 PE1 MOV r1, 10 MUL r1, r1, r1... interrupt req PE3 PE2 MLA... r1, r2, r2, r1... MCNTR MADDR MDATA S0 S1 S2 S3 interrupt S0 S1 S2 S3 S4 Communication Approximatetimed Cycletimed D C F E PE1 D B1 v1 = a*a; PE4 (Arbiter) 3 PE3 B3 v3= v1- b*b; PE1 E B1 v1 = a*a; PE4 (Arbiter) 3 cv12 PE3 S0 S1 Cycletimed Untimed A B Untimed Approximatetimed Computation PE2 B2 v2 = v1 + b*b; 1 2 1: master interface 2: slave interface 3: arbitor interface IProtocolSlav v3 B4 v4 = v2 + v3; c = sequ(v4); PE2 B2 v2 = v1 + b*b; cv2 1 2 cv11 1. Master interface 2. Slave interface 3. Arbiter interface 4. Wrapper 4 S2 S3 S4 38

Characteristics of Different Abstraction Models Models Specification model Componentassembly model Bus-arbitration model Bus-functional model Cycle-accurate computation model Implementation model Communication Computation Communication PE interface time time scheme no no variable (no PE) no approximate variable channel abstract approximate approximate abstract bus channel time/cycle approximate protocol bus accurate channel approximate cycle-accurate abstract bus channel abstract abstract pin-accurate cycle-accurate cycle-accurate bus (wire) pin-accurate 39

Hardware vs. Software 40

System Architect vs. Chip Designer 41

Design through Various Levels of Abstraction Architecture level - Behavior - Area,PWR, - Speed estimation Register Transfer Level - Functions - Timing 43

Logic Level 0 & 0 - Bits - Timing 0 Tr. Level - Voltages - Currents Physical Level (=Layout) - Dimensions 44

Device Level - In Characteristic Technology Level - Impurity Profiles Doping Dopant A Dopant B 45 Depth

Behavioral Domain Structure Domain Physical Domain System Level Performance specs. CPU`s Memories Switches Controllers Buses Physical partitions Algorithm Level Algorithms (manipulation of data structure) Hardware modules Data structures Clusters Microarchitect ural Level Operations Register transfers State sequencing ALUs MUXs Registers Microstore Floorplans Logic Level Boolean equations FSM Gates Flip-Flops Cells Cells, module plan Circuit Level Transfer functions, timing Transistors Wires Contacts Layout 46

Memory element input equations J x K Y1 Y1 x J Z ( x y ) y Y 0 1 0 K ( x y ) y Y 0 1 0 The next state equation for J-K Flip-Flop y J y K y v 1 v v v (1) (2) (3) For the memory element y0, y1, the next state equation of (1), (2) y x y x y x v 1 v v v v v 1 1 1 (4) y [( x y ) y ] y [( x y ) y ] y ( x y ) y v 1 v v v v v v v v v v v 0 1 0 0 1 0 0 1 0 48 X Y1 Y0 Q Q Q Q SET Y1 CLR SET Y0 CLR J K J K (5) JY1 JY0 Z Clock

Transition table y y v v 1 0 0 0 0 1 1 0 1 1 v x y 0 1 0 1 0 0 0 0 0 0 0 1 y v 1 v 1 1 0 v z 1 1 1 0 0 1 1 1 0 0 0 1 1 0 0 1 q 1 q 2 q 3 y y 1 2 state = 0 0 state = 0 1 state = 1 1 q 4 state = 1 0 49

State table State diagram v 1 q q q1 3 q1 q4 q1 q4 q2 q3 Present states v q q 1 q 2 q 3 q 4 0 1 0 0 0 1 v x 1 0 0 1 0/0 q 1 q 2 0/0 X/ Z 1/1 0/0 1/0 0/1 q 3 Input 1/0 1/1 q 4 Output v z 50

Analysis Process State diagram State assignment Memory Element Input equation Functional description State table Minimal State table Transition table Circuit Design Process (Logic Synthesis) 51

Structure of Digital System 52

DATA Buffer B - Reg Acc T - Reg Inst. Reg HL Reg PC ALU Decoder + 1 MEMORY Cont. Signal ADD Buffer 8 bits Timing Control Contrl Bus 16 bits CPU 53

1 T1 address bus (PC) T2 PC (PC) + 1 T3 IR (M) T4 decode T1 address bus (PC) 2 T2 PC (PC) + 1 T3 Z (M) T1 address bus (PC) 3 T2 PC (PC) + 1 T3 W (M) T1 address bus (WZ) 4 T2 -------- T3 Acc (M) 54

+1 IAR 10 bits 16 bits MAR 10 bits Memory Op ADR IAR Adder Control ACC IAR 55

Logic Design Flow & Data, Instruction Format Logic Design Flow Data Format 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SPEC s M A G Func. Design S : Sign (+ if 0, - if 1 ) MAG : Magnitude Functional Simulation Data & Instruction Format 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Collection of Condions op A D R Gate Level Circuit Design OP : OP Code ADR : Address 56

Instruction Set OP Code Operation LOAD 000100 ACC (M(ADR)) STORE 001000 M(ADR) ACC ADD 010000 ACC ACC+(M(ADR)) BRANCH 100000 BRANCH TO ADR BRANCH-POSITIVE 100001 BRANCH TO ADR IF (ACC)>=0 ACC : Accumulator ADR : Address part in instruction M(ADR) : Address No. of memory 57

State Diagram for instruction Cycle ADS ADS : Address Set IFT : Instruction Fetch DEC : Decode LDA : Load STA : Store ADD : Add BRA : Branch BRP : Branch-Positive IFT DEC LDA STA ADD BRA BRP 58

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_misc.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_components.all; use WORK.MATH.all; entity CPU is port ( CLOCK : in std_logic; RESET : in std_logic); end CPU; architecture BEHAVIORAL of CPU is type STATE_TYPE is (ADS, IFT, DEC, LDA, STA, ADD, BRA, BRP); type MEMORY is array(0 to 6) of std_logic_vector(15 downto 0); signal CURRENT_STATE, NEXT_STATE : STATE_TYPE; signal MEM : MEMORY := MEMORY'("0001000000000011", "0100000000000100", "0010000000000101", "0000000000000111", "0000000000001001", "0000000000000000", "0000000000000000" ); signal ACC, IR : std_logic_vector(15 downto 0); signal MAR, IAR : integer range 0 to 1023; begin -- process to hold combinational logic COMBIN : process(current_state, RESET) variable temp : std_logic_vector(15 downto 0); begin if RESET = '1' then MAR <= '0'; IAR <= '0'; NEXT_STATE <= ADS; 59

else case CURRENT_STATE is when ADS => MAR <= IAR; IAR <= IAR+1; NEXT_STATE <= IFT; when IFT => IR <= MEM(MAR); NEXT_STATE <= DEC; when DEC => MAR <= vector2int(ir(9 downto 0)); case IR(15 downto 10) is when "000100" => NEXT_STATE <= LDA; when "001000" => NEXT_STATE <= STA; when "010000" => NEXT_STATE <= ADD; when "100000" => NEXT_STATE <= BRA; when "100001" => NEXT_STATE <= BRP; when others => null; end case; 60

when LDA => ACC <= MEM(MAR); NEXT_STATE <= ADS; when STA => MEM(MAR) <= ACC; NEXT_STATE <= ADS; when ADD => temp := add_sub(acc, MEM(MAR), TRUE); ACC <= temp; NEXT_STATE <= ADS; when BRA => IAR <= MAR; NEXT_STATE <= ADS; when BRP => if ACC(15) = '0' then IAR <= MAR; end if; end case; end if; end process; -- process to hold syschronous elements (flip-flops) SYSCH : process begin wait until CLOCK'event and CLOCK = '1'; CURRENT_STATE <= NEXT_STATE; end process; end BEHAVIORAL; configuration CFG_CPU_BEHAVIORAL of CPU is for BEHAVIORAL end for; end CFG_CPU_BEHAVIORAL; 61

library IEEE; use IEEE.std_logic_1164.all; package MATH is function add_sub(l, R : std_logic_vector; ADD : BOOLEAN) return std_logic_vector; function vector2int(s : std_logic_vector(9 downto 0)) return INTEGER; end MATH; package body MATH is function add_sub(l, R : std_logic_vector; ADD : BOOLEAN) return std_logic_vector is variable carry : std_logic; variable A, B, sum : std_logic_vector(l'length-1 downto 0); begin if ADD then -- prepare for an "add" operation A := L; B := R; carry := '0'; else -- prepare for a "subtract" operation A := L; B := not R; carry := '1'; end if; -- create a ripple-carry chain; sum up bits for i in 0 to A'left loop sum(i) := A(i) xor B(i) xor carry; carry := (A(i) and B(i)) or (A(i) and carry) or (carry and B(i)); end loop; return sum; -- result end; 62

function vector2int(s : std_logic_vector(9 downto 0)) return INTEGER is variable result : INTEGER range 0 to 1023 := 0; begin for i in 9 downto 0 loop result := result * 2; if S(i) = '1' then result := result + 1; end if; end loop; return result; end vector2int; end MATH; 63

Time CLK <(10)> <TIME> CLK <(10)>. <AUTOMATION> CPU : CLK : <STATES> ADS : MAR <- IAR, IAR <- IAR+1, -> IFT IFT : IR <- M(MAR), -> DEC. DEC : MAR <- ADR,?OP #4 -> LDA #8 -> STA #16 -> ADD #32 -> BRA #33 -> BPR. LDA : ACC <- M(MAR), -> ADS. STA : M(MAR) <- ACC, -> ADS. ADD : ACC <- ACC+M(MAR), -> ADS. BRA : IAR <- ADR, -> ADS. BRP : * -ACC(0) * IAR <- ADR, -> ADS. <END>. <END> CPU. MAR IAR ADS IFT n-1 n n n+1 <TIME> CLK<(1)>. <STATES> ADS : MAR<-IAR, IAR<-IAR+1, ->IFT. 65

SCL (Simulation Control Language) Memory Address 0 LOAD 3 Program 1 ADD 4 Program 2 STORE 5 Program 3 7 Data 4 9 Data 5 16 Result 66

Slmulation Control program by SCL INIT M(0) = X 1003 Memory Initialization INIT M(1) = X 4004 INIT M(2) = X 2005 INIT M(3) = X 0007 INIT M(4) = X 0009 INIT CPU = ADS = B 0 CPU CPU Initialization TRACEX AT 0 AT 1000 IAR, MAR, IR, ACC, M(5) START 0 Output Format Simulation Start Time Setting 67

Program Example & memory Initialization 68

Simulation Execution Result CLK IAR MAR IR ACC M(5) 0 X 000 X 0000 X 0000 X 0000 X 0000 10 X 001 X 0000 X 0000 X 0000 X 0000 20 X 001 X 0000 X 1003 X 0000 X 0000 30 X 001 X 0003 X 1003 X 0000 X 0000 40 X 001 X 0003 X 1003 X 0007 X 0000 50 X 002 X 0001 X 1003 X 0007 X 0000 60 X 002 X 0001 X 4004 X 0007 X 0000 70 X 002 X 0004 X 4004 X 0007 X 0000 80 X 002 X 0004 X 4004 X 0010 X 0000 90 X 003 X 0002 X 4004 X 0010 X 0000 100 X 003 X 0002 X 2005 X 0010 X 0000 110 X 003 X 0005 X 2005 X 0010 X 0000 120 X 003 X 0005 X 2005 X 0010 X 0010 69 LOAD 3 ADD 4 STORE 5

Circuit Design Terminal HDL Description Circuit Symbol BUS a <Terminal> A, B, C ----A ----B ----C BUS b <Terminal> BUS(4) ----BUS(0) ----BUS(1) --/--BUS ----BUS(2) 4 ----BUS(3) 70

Boolean 71

Combination Logic 72

Register HDL Description Circuit Diagram F L I P - F L O P R E G I S T E R a R E G I S T E R b <REGISTER> R <REGISTER> R(4) <TERMINAL> DATA 1(4) DATA 2(4), C1, C2, DATA1 <REGISTER> R(4) <AUTOMATION> MPXR:CLK: <LOGIC> *C1* R<-DATA1., *C2* R<-DATA2.. <END> MPXR Data 1 C1 Data 2 C2 73 R Input Data L Clock CG 4 / 4 / R(0) R(1) R(2) R(3) / 4 / 4 cond / 4 / 4 clk / 4 Output Data R / 4 R / 4

Flip-Flop Name Circuit Symbol Truth Table SET RSFF S R Q Q S Q R CLR Q 0 0 0 1 1 0 1 1 Q 0 Q 0 0 1 1 0 JKFF J K Q Q J K SET CLR Q Q 0 0 0 1 1 0 1 1 Q 0 Q 0 0 1 1 0 Q 0 Q 0 GLFF G L Q Q L S R SET CLR Q Q 0 0 0 1 1 0 1 1 Q 0 Q 0 Q 0 Q 0 0 1 1 0 G 74

Collection of Conditions <AUTOMATION> CPU:CLK: <LOGIC> *ADS* MAR(0:9) <- IAR(0:9), *ADS* IAR(0:9) <- IAR(0:9) +1., *ADS* -> IFT., *IFT* IR(0:15) <- M(MAR(0:9), 0:15)., *IFT* -> DEC., *DEC* MAR(0:9) <- IR(6:15)., *DEC & (IR(0:5) := 4)* -> LDA., *DEC & (IR(0:5) := 8)* -> STA., *DEC & (IR(0:5) := 16)* -> ADD., *DEC & (IR(0:5) := 32)* -> BRA., *DEC & (IR(0:5) := 33)* -> BRP., *LDA* ACC(0:15) <- M(MAR(0:9), 0:15)., *LDA* -> ADS., *STA* M(MAR(0:9), 0:15) <- ACC(0:15)., *STA* -> ADS., *ADD* ACC(0:15) <- ACC(0:15)+M(MAR(0:9), 0:15)., *ADD* -> ADS., *BRA* IAR(0:9) <- IR(6:15)., *BRA* -> ADS., *BRP & ACC(0)* IAR(0:9) <- IR(6:15)., *BRP* ->ADS., <END> CPU. Transition Condition to Reg. & Memory Device Name Source Transfer Condi. MAR(0:9) IAR(0:9) IR(6:15) ADS DEC IR(0:15) M(MAR(0:9), 0:15) IFT IAR(0:9) ACC(0:15) M(MAR(0:9),0: 15) IAR(0:9)+1 IR(6:15) M(MAR(0:9), 0:15) ACC(0:15)+M(MAR(0:9), 0:15) ACC(0:15) ADS BRA BRP & ~ACC(0) LDA ADD STA 75

*ADS* -> IFT., *IFT* -> DEC., *DEC & (IR(0:5) := 4)* -> LDA., *DEC & (IR(0:5) := 8)* -> STA., *DEC & (IR(0:5) :=16)* -> ADD., *DEC & (IR(0:5) :=32)* -> BRA., *DEC & (IR(0:5) :=33)* -> BRP., *LDA* -> ADS., *STA* -> ADS., *ADD* -> ADS., *BRA* -> ADS., *BRP* -> ADS., Next State ADS IFT DEC Current State LDA STA ADD BRA BRP ADS IFT Transfer Condition LDA DEC IR(0:5):=4 STA DEC IR(0:5):=8 ADD DEC IR(0:5):=16 BRA DEC IR(0:5):=32 BRP DEC IR(0:5):=33 76

Circuit Design IAR ADS IR(6:15) DAC DEC 10 10 10 10 MAR 10 10 MAR(0:9) CLK MAR Design M(MAR,0:15) IR 16 16 IR(0:15) CLK IFT IR Design 77

IAR(0:9)+1 10 10 IAR ADS IR(6:15) 10 10 10 10 IAR(0:9) BRA CLK BRP ACC(0) IAR Design M(MAR,0:15) 16 16 ACC LDA ACC(0:15)+M(MAR,0:15) 16 16 16 16 ACC(0:15) ADD CLK ACC Design 78

ACC(0:15) 16 STA MAR(0:9) 10 M 16 M(MAR,0:15) Data Transfer of M source Cond M(MAR(0:9),0:15) ACC(0:15) STA 79

Data Path Design ADS +1 10 10 IAR(0:9) 10 10 10 CLK CLK 16 IR(0:15) ADR 16 OP 10 6 ACC(0) ADS DEC 10 10 CLK MAR(0:9) 10 10 16 WRITE ENABLE 16 M 16 16 16 CONTROL LOGIC ADS IFT DEC LDS STA ADD BRA BRP LDA ADD 16 ACC 16 ADDER CLK ACC(0:15) STA 80

Control Logic Design State ST(0) ST(1) St(2) ADS 0 0 0 IFT 0 0 1 DEC 0 1 0 LDA 0 1 1 STA 1 0 0 ADD 1 0 1 Number of States : 8 Required F.F : 3 ST(0) ST(1) ST(2) BRA 1 1 0 BRP 1 1 1 81

State Assignment 1. 목적 순서회로 (Sequential circuit) 에대해 최소길이의 2진코드를이용. 각상태에서로다른코드를할당. 조합회로부를최소화. 2. 필요성 순서회로의최적설계를위함 각내부상태에대한코드할당 최종회로의논리관계형성. 할당방식에따라서로다른회로면적을갖음. 상태간의연관관계를고려최적할당코드를구함. 82

State Assignment 3. 순서회로의기본구조 현상태및입력조건에의한다음상태및출력을결정. 구성 조합회로 (PLA, random logic) 기억소자 (register) 주입력 주출력 그림 1. 순서회로의일반구조 순서회로는상태천이도 or 상태천이표로나타냄 83

State Assignment 4. 상태할당의기본개념 Present State Q 1 Q 2 S1 S2 S3 S4 Input X 0 1 S4 S3 S1 -- S4 S2 S4 S2 그림 2. 상태천이표 S1->00, S2->01 S3->11, S4->10 Present State Q 1 Q 2 00 01 11 10 Input X 0 1 10 11 00 -- 10 01 10 01 그림 3. 상태천이표 X 0 1 Q 1 Q 2 00 1 1 01 1 0 11 0 1 10-0 그림 4. Output(D1) 그림 5. Output(D2) D1 = Q 1`Q 2`+Q 1`X`+Q 1 Q 2 X D2 = Q 1`Q 2 + Q 1 Q 2` X 0 1 Q 1 Q 2 00 0 0 01 1 1 11 0 0 10-1 84

* ㄱ ST(0)& ㄱ ST(1)& ㄱ ST(2)* ST(2)<-1 * ㄱ ST(0)& ㄱ ST(1)&ST(2)* ST(1)<-1, ST(2)<-0. * ㄱ ST(0)&ST(1)& ㄱ ST(2)&(IR(0:5):=4)* ST(2)<-1. * ㄱ ST(0)&ST(1)& ㄱ ST(2)&(IR(0:5):=8)* ST(0)<-1,ST(1)<-0. * ㄱ ST(0)&ST(1)& ㄱ ST(2)&(IR(0:5):=16)* ST(0)<-1,ST(1)<-0.ST(2)<-1 * ㄱ ST(0)&ST(1)& ㄱ ST(2)&(IR(0:5):=32)* ST(0)<-1. * ㄱ ST(0)&ST(1)& ㄱ ST(2)&(IR(0:5):=33)* ST(0)<-1.ST(2)<-1 * ㄱ ST(0)&ST(1)&ST(2)* ST(1)<-0, ST(2)<-0. *ST(0)& ㄱ ST(1)& ㄱ ST(2)* ST(0)<-0. *ST(0)& ㄱ ST(1)&ST(2)* ST(0)<-0, ST(2)<-0. *ST(0)&ST(1)& ㄱ ST(2)* ST(0)<-0, ST(1)<-0. *ST(0)&ST(1)&ST(2)* ST(0)<-0, ST(1)<-0,ST(2)<-0. ST(0) SET CONDITION ㄱ ST(0)&ST(1)& ㄱ ST(2)&(IR(0:5):=8 IR(0:5):=16 IR(0:5):=32 IR(0:5):=33) ST(0) RESET CONDITION ST(0) ST(1) SET CONDITION ㄱ ST(0)& ㄱ ST(1)&ST(2) ST(1) RESET CONDITION ST(1)&( ㄱ ST(0)& ㄱ ST(2)&((IR(0:5):=8) (IR(0:5):=16)) ST(2)) ST(2) SET CONDITION ㄱ ST(0)& ㄱ ST(2) &( ㄱ ST(1) IR(0:5):=4) (IR(0:5):=16 IR(0:5):=33) ST(2) RESET CONDITION ST(2) 85

Control Path 0 1 2 3 4 5 op S ST(0) Q R S Q ST(1) Q R S ST(2) Q Q R Q ADS IFT DEC LDA STA ADD BRA BRP 86

ADS ST(0) ST(1) ADS 0 0 IFT IFT 0 1 DEC 1 1 DEC EXC EXC 1 0 LDA = EXC & (OP := 4) STA = EXC & (OP := 8) ADD = EXC & (OP := 16) BRA = EXC & (OP := 32) BRP = EXC & (OP := 33) Op code is stored in IR Reg. OP during decode the instruction and execution the instruction. 87

Simplified Control Bus S R Q Q S R Q Q ADS IFT DEC EXE OP 0 1 2 3 4 5 LDA STA ADD BRA EXE 88

Design of Adder HDL Descript Symbol Truth table Circuit Diagram A B C S C <TERMINAL> (a) Full Adder A B c F A C S 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 A,B,C,S,C. <BOOLEAN> C = A & B A B c S C 1 1 0 0 1 (A @ B) & C, 1 1 1 1 1 S = A@B@C (b) Half Adder A B H A C S A B S C 0 0 0 0 0 1 1 0 1 0 1 0 <TERMINAL> A, B, S, C. <BOOLEAN> A B C S 1 1 0 1 C=A&B. S=A@B. 89

A(0) B(0) FA C(0) S(0) A(1) B(1) C(2) FA C(1) S(1) A(14) B(14) FA C(14) S(14) A(15) B(15) FA C(15) S(15) < OPERATOR > S<(A, B)> (16) < TERMINAL > A(16), B(16), C(16). < BOOLEAN > C = A & B (A @ B) & C(1:15) B 0, S = A @ B @ C(1:15) B 0. < END > S. 90

A(0) HA C(0) I(0) A(1) HA C(1) I(1) C(2) A(8) HA C(8) I(8) A(9) I HA C(9) I(9) < OPERATOR > I <A> (10) < TERMINAL > A(10), C(10). < BOOLEAN > C = A & C (1:9) B 1, I = A @ C(1:9) B 1. < END > I. 91

Micro-Programmed CPU Design 16 LSI 1 16 LSI 2 ABUS LSI 3 16 16 16 BBUS LSI 6 16 15 6 16 IR SIR LIR 6 16 ACC IR SACC LACC 6 16 IAR IR SIAR LIAR LSI 4 ADDER 10 MAR MAD LMAR 16 M READ WRITE B 1(16) ONE OPC 16 SOP 6 NEG 16 COND LSI 7 4 10 CBUS NEXT 16 10 16 OPA 4 4 4 RBUS 4 ROM ADR 4 RAD ROM ABUS = sir& IR SACC&ACC siar& B 000000 IAR BBUS = READ&M(MAR) ONE&B 0000000000000001 CBUS INPUT = ABUS + BBUS CBUS OUTPUT ACC <- *LACC* CBUS., IR <- *LIR* CBUS., IAR <- *LIAR* CBUS(0:9)., MAR <- *LMAR* CBUS(0:9)., M(MAR) <- *WRITE* CBUS.. 92

S L S L S L L R W O S C I I A A I I M E R N O O R R C C A A A A I E P N C C R R R D T D E NEXT(4) 0 1 1 0 0 0 1 1 1 1 1 0 0 1 0 2 1 1 0 0 1 1 3 1 1 1 4 1 1 0 0 0 0 5 1 1 0 0 0 0 6 1 1 1 0 0 0 0 7 1 1 0 0 0 8 1 1 0 0 0 0 9 0 0 0 0 ADS : MAR <- IAR IAR <- IAR + 1L. IFT : IR <- M(MAR). DEC : MAR <- ADR. LDA : ACC <- M(MAR). STA : M(MAR) <- ACC. ADD : ACC <- ACC + M(MAR). BRP : BRA : IAR <- ADR. -> ADS. 93

Empties represent 0 Control Rom 16 bit first 10bit => control signal final 4bit => next address to read add change => set 10th, 11th SOP COND to 1 Address 0 : SIAR, LMAR is 1, then MAR IAR next address is 0001 Address 1 : SIAR, LIAR, ONE is 1, then IAR IAR+1 Address 3 : SIR, LMAR is 1, so MAR ADR of IR Next instruction <= OP (set SOP=1) Address 7 : COND=1, first bit of ACC = 0 then ROM ADR become 1000, first bit of ACC = 1 then ROM ADR become 1001. 94

<SYSTEM> MICRO: <TIME> CLK<(10)>. <STORAGE> M(1024,16), ROM(16,16). <REGISTER> IR(16)=OP(6) ADR(10). ACC(16),IAR(10),MAR(10),ROMADR(4). <TERMINAL> ABUS(16),BBUS(16),CBUS(16),RBUS(4),OPA(4), CONTROL(16) =SIR LIR SACC LACC SIAR LIAR LMAR READ WRITE ONE SOP COND NEXT(4). <BOOLEAN> ABUS=SIR & IR SACC & ACC SIAR & B 000000 IAR, BBUS=READ & M(MAR) ONE & B 1(16), CBUS=ABUS+BBUS, CONTROL=ROM(ROMADR), RBUS=SOP & OPA ~SO[P & NEXT B 000 (COND & ~ACC(0),? OP # B 000100 OPA = B 0100 # B 001000 OPA = B 0101 # B 010000 OPA = B 0110 # B 100000 OPA = B 1000 # B 100001 OPA = B 0111.. <AUTOMATION> CPU:CLK: <LOGIC> * LIR * IR <- CBUS., * LACC * ACC <- CBUS., * LIAR * IAR <- CBUS(0:9)., * LMAR * MAR <- CBUS(0:9)., * WRITE * M(MAR) <- CBUS., ROMADR <- RBUS. <END> CPU. <END> MICRO. 95

Partition <SYSTEM> LSIS: <TIME> CLK<(10).. <STORAGE> M(1024,16), ROM(16,16). <TERMINAL> ABUS(16), BBUS(16), CBUS(16), OPC(6), NEG, MAD(10), RAD(4), CONTROL(16)=SIR LIR SACC LACC SIAR LMAR READ WRITE ONE SOP COND NEXT(4),ABUS1(16),AB US2(16),ABUS3(16). <BOOLEAN> ABUS=ABUS1 ABUS2 ABUS3, CONTROL=ROM(RAD). <AUTOMATION> LSI1: CLK: <REGISTER> IR(16)=OP(6) ADR(10). <LOGIC> ABUS1=SIR&IR, IR & a peripheral circuit OPC=OP, * LIR * IR <- CBUS.. <END> LSI1. <AUTOMATION> LSI2: CLK: <REGISTER> ACC(16). <LOGIC> ABUS2 = SACC & ACC, NEG = ~ACC(0), ACC & a peripheral circuit * LACC * ACC <- CBUS.. <END> LSI2. <AUTOMATION> LSI3: CLK: <REGISTER> IAR(10). <LOGIC> ABUS3(0:9) = SIAR & IAR, * LIAR * IAR <- CBUS.. <END> LSI3. 96

<AUTOMATION> LSI4: CLK: <BOOLEAN> CBUS = S < (ABUS,BBUS) >. <OPERATOR> S < (A,B) > (16) <TERMINAL> A(16), B(16), C(16). <BOOLEAN> C = A & B (A@B) & C(1:15) B1 0, S = A@B@C(1:15) B 0. <END> S. <END> LSI4. <AUTOMATION> LSI5: CLK: <REGISTER> MAR(10). <LOGIC> MAD = MAR, * LMAR * MAR <- CBUS(0:9).. <END> LSI5. <AUTOMATION> LSI6: CLK: <BOOLEAN> BBUS = READ & M(MAD) ONE & B 1(16). <END> LSI6. <AUTOMATION> LSI7: CLK: <REGISTER> ROMADR(4). <TERMINAL> OPA(4), RBUS(4). <LOGIC> RBUS = SOP & OPA ~SOP & NEXT B 000 (NEG & COND), RAD = ROMADR,? OPC # B 000100 OPA = B 0100 # B 001000 OPA = B 0101 # B 010000 OPA = B 0110 # B 100000 OPA = B 1000 # B 100001 OPA = B 0111., ROMADR <- RBUS. <END> LSI7. <END> LSIS. 97

<AUTOMATION> LSI1 IR -- and its peripherals <AUTOMATION> LSI2 ACC -- and its peripherals <AUTOMATION> LSI3 IAR -- and its peripherals <AUTOMATION> LSI4 ADDER <AUTOMATION> LSI5 MAR --and its peripherals <AUTOMATION> LSI6 BBUS -- and its peripherals <AUTOMATION> LSI7 ROMADR, RBUS -- and its peripherals <SYSTEM> TEST7: <ENTERANCE> OPC(6), NEG. <TIME> CLK <(10)>. <STORAGE> ROM(16,16). <TERMINAL> RAD(4), CONTROL(16) = SIR LISR SACC LACC SIAR LIAR LMAR READ WRITE ONE SOP COND NEXT (4). <BOOLEAN> CONTROL = ROM(RAD). <AUTOMATION> LSI7: CLK: <END> LSI7. <END> TEST7. 98