Microsoft PowerPoint - VHDL01_chapter1.ppt [호환 모드]

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1 VHDL 프로그래밍 1. 문법기초 - 간단한조합회로및문법 학습목표 VHDL 기술과소프트웨어와차이파악 Signal assignment 의의미파악 Architecture body 의개념파악 Entity declaration 의개념파악 Process 문의사용법 Variable 과 signal 의차이파악 Library, Use, Package 의사용법 2/53

2 간단한논리회로예제 A B t1 X B C C A t2 t3 Y Boolean 수식 X = AB + BC, Y = BC + CA t2=bc, X = AB + t2, Y = t2 + CA 3/53 Boolean VHDL t2=bc, X = AB + t2, Y = t2 + CA t2 <= B and C; Boolean/logic op X <= (A and B) or t2; 문장끝 ; Y <= t2 or (C and A); Assignment op. variable? ibl? signal (time, value) 4/53

3 Wire?InVHDL Signal ( 시간에따라다른값을가짐 ) Y <= t2 or (C and A); X <= (A and B) or t2; t2 <= B and C; To use signals? Define Before Use!! Where? Within Architecture body!! 5/5353 Architecture Body architecture netlist of first is signal t2 : std_logic; begin Y <= t2 or (C and A); X <= (A and B) or t2; t2 <= B and C; end netlist; 6/53

4 소프트웨어와다른점? 각문장이병렬로수행됨 따라서, 문장순서가중요하지않음. Concurrent Signal Assignment 문 아래두개의 H/W 기술은같은동작 t2 <= B and C; X <= (A and B) or t2; X <= (A and B) or t2; t2 <= B and C; Y <= t2 or (C and A); Y <= t2 or (C and A); 7/53 신호할당문은언제수행되나? RHS 의한신호에값의변화가있을때 (Event 가생겼을때 ) X<= (A and B) or t2; A B t2 X 8/53

5 Entity 선언? A B B C C A t1 t2 t3 X Y Entity first is Port (A, B, C : in std_logic; inout X, Y : out std_logic); buffer End first; std_logic?? 9/53 std_logic 전선 /node/wire를모델링하는 type 가질수있는값? 0 -- Forcing Forcing 1 Z -- High Impedance - -- Don t care U -- Uninitialized X -- Forcing Unknown W -- Weak Unknown L -- Weak 0 H -- Weak 1 IEEE 의 std_logic_1164 package 에정의된 type (std_logic, std_logic_vector ) 10/53

6 std_logic 을사용하려면? library IEEE ; use IEEE.std_logic_1164.all; Library : 여러가지패키지포함 Use : library 의특정패키지사용 11/53 Libraries i and Packages Standard Library: IEEE, STD IEEE library std_logic_1164 std_logic, std_logic_vector std_logic_arith, std_logic_unsigned, std_logic_signed, std_logic_textio STD library : 기본적으로포함됨. library WORK, STD; use STD.STANDARD.all; STANDARD 12/53

7 Arch. Body, Entity decl. 외에? Design unit Primary unit Package declaration package body Secondary unit Entity declaration Architecture body Configuration declaration 13/53 Another way to describe Y <= t2 or (C and A); X <= (A and B) or t2; t2 <= B and C; process (A,B,C) variable ibl t2 : std_logic; dl begin Sequential exec. t2 := BandC; X <= (A and B) or t2; Sensitivity i i list Y <= t2 or (C and A); RHS signals end process; In Sig. Assignment. 14/53

8 Architecture t body (updated) d) architecture netlist of first is begin process (A,B,C), variable t2 : std_logic; begin t2 := B and C; X <= (A and B) or t2; Y <= t2 or (C and A); end process; end netlist; 15/5353 Y<= outside of process architecture netlist of first is begin process (A,B,C) variable t2 : std_logic; begin t2 := B and C; X <= (A and B) or t2; end process; Y <= (B and C) or (C and A); end netlist; No Problem? 16/53

9 To share AND gate? architecture netlist of first is Signal t2 : std_logic; begin t2 <= B and C; process (A, B, t2) begin X <= (A and B) or t2; end process; Y <= t2 or (C and A); end netlist; 17/53 The order of statements t t architecture netlist of first is begin process (A,B,C) variable t2 : std_logic; begin t2 := B and C; Y <= t2 or (C and A); X <= (A and B) or t2; end process; end netlist; 18/53

10 ALU (1/2) library IEEE; use IEEE.std_logic_1164.all; _ use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity alu is port ( A, B, M : IN std_logic_vector(2 downto 0); Y : out std_logic_vector(2 downto 0); CO : out std_logic ); end alu; 19/53 ALU (2/2) architecture t behav of alu is signal temp : std_logic_vector(3 downto 0); begin y <= temp(2 downto 0); CO <= temp(3); process (A, B, M) begin temp <= (others => '0'); case M is when "000" => temp(2 downto 0) <= not A; when "001" => temp(2 downto 0) <= A xor B; when "010" => temp(2 downto 0) <= A or B; when "011" => temp(2 downto 0) <= A and B; when "100" => temp <= ('0' & A) + B; when "101" => temp <= ( A(2) & A) + (not (B(2) & B)) + 1; when "110" => temp <= ('0' & A) + 1; when others => temp(2 downto 0) <= A; end case; end process; end behav; 20/53

11 문법기초 주석, 식별자, Literal 상수 Object class( 객체의종류 ) variable, signal, constant, file Object Data type Scalar, composite, file, access Operators (arithmetic ti & logical) l) Design units & Libraries 21/53 Comments in VHDL -- 로시작, 행의끝까지 -- this is a comment Entity test is... End test; -- the beginning of architecture... 22/53

12 Identifiers in VHDL Identifier ( 식별자 ) 변수, 신호, 상수, name 등. Letter 로시작 << VHDL 은대소문자구별이없음!! >> 다음에 letter, digit, _ 가옴. _ (underscore) 는연속해올수없음! 23/53 Literals in VHDL 정수형 literal 21, 0, 1E2, 123_000 실수형 literal 11.0, 0.436, 3.141_592_6, 2.0E+4 문자형 literal 1, A, % 24/53

13 Literals in VHDL ( 계속 ) Base 를포함한숫자형 literal 2#1111_1100#, 1100# 16#FC#, 016#0FC#, 7#510# ( 모두 252 의미 ) 스트링 literal ad# sd 비트스트링 literal Prefix: B, O, X (Binary, Octal, Hexa) X F_FF, FF O 7777, B 1111_1111_ /5353 Objects in VHDL Object: 사용자가정의해서사용하는객체들 Object class( 객체의종류 ): 사용방식 variables, signals, constants, files Object type( 객체의 type): 데이터유형 Scalar, composite, file, access 26/53

14 Object data types VHDL object types scalar type access type File type composite type enumeration Integer real Physical array record 27/53 Object class (constant) 변경불가 Entity, architecture, process, package 내에서선언가능 예 : Constant vcc: real := 4.5; Constant t five : bit_vector t := 1010 ; 28/53

15 Object class (variable) 변경가능 ( 즉시변경됨 signal 과차이 ) Process, subprogram(proc., func.) 내에서만선언가능 예 : variable index : integer range 1 to 60; variable R : std_ logic _ vector(7 downto 0); 할당연산자 (variable assignment operator) R := ; index := 27; 29/53 Object class (signal) Entity, architecture내에서선언, process 내에서는선언불가. Entity decl. 의 port 들은모두 signal 임. 선언예 : Signal count : integer range 1 to 31; Signal ground : bit := 0 ; 할당연산자 : 신호 (time, value) pair 로표현 Ground <= 0 ; 0; count <= 23 after 20 ns; 30/53

16 Object class (file) VHDL-87 에서 (IEEE std ) File <id> : <name> is [in out] <logical_name>; File infile : TEXT is in sample.dat ; VHDL-93 (IEEE std ) 1993) File <id> : <file_type_name> [open file_open_mode] is <logical_name> File infile : text open read_mode is sample.dat File infile :text; file_open(infile, sample.dat, read_mode); file_close(infile) l 31/53 Object data type (scalar type) Enumeration type : ordered list Std_ulogic, std_logic, bit 등 Type bit is ( 0, 1 ); type state is (s0, s1, s2); Integer type Real type Physical type : 시간등단위가있는수 Type time is range -. To +.; Units fs; -- femto second ps = 1000 fs; ns = 1000 ps;... End units 32/53

17 Object data type (composite) Array type : 주의!!: 첨자표시 (, ) Type string is array (positive range <> ) of character; Type mem is array(0 to 1023, 7 downto 0) of bit; Record type Type instruction is record Op_field : OPR; OPD1 : integer range 0 to 127; OPD2 : integer range 0 to 127; End record; Variable cmd : instruction;... cmd.opd1 := 2; cmd.opr := ADD; 33/53 선언 Object data type (file type) type <file_type_name> >is file of f<t <type_name>; type vec_file is file of std_logic_vector(15 downto 0); 사용 file filea : vec_file is in test.dat ; 34/53

18 Object data type (access) C 에서 pointer type 과같음. 정의는되어있으나거의사용되지않음 35/5353 Subtype 이미정의된 type(base type) 에어떤조건을추가해새이름의 type 정의. 예 : Subtype eightval is integer range 0 to 7; Signal b : subtype; Subtype 사용하지않고도 range 제한가능. Signal b : integer range 0 to 7; 36/53

19 산술및논리연산자 Logical operator Relational operator Adding operator Sign Multiplying operator 기타 operator 37/53 연산자우선순위 구분 종류 우선순위 논리연산자 and, or, nand, nor, xor 6 관계연산자 =, /=, <, >, >=, <= 5 덧셈연산자 +, -, & 4 부호 +, - 3 곱셈연산자 *,/,mod,rem 2 기타연산자 **, abs, not 1 38/53

20 논리연산자사용예 잘못된논리연산자사용예 올바른논리연산자사용예 A <= x and y or z A <= x nor y nor z; A <= (x and y) or z ; B <= (x nor y) nor z; C <= x and y and z; 39/53 Concatenation 연산자사용예 signal sig6 : std_logic_vector(5 downto 0); signal sig4 : std_logic_vector(3 downto 0) ; signal sig3 : std_logic_vector(2 downto 0); signal sig2 : std_logic_vector(1 t downto 0); signal S1 : std_logic_vector(3 downto 0); signal S2 : std_logic_vector(4 t downto 0); sig3 <= sig2 & 1 ; sig6 <= 00 &sig4; sig8 <= sig2 & sig6; S1 <= 00 & 10 ; S2 <= 0 & S1; 40/53

21 Remainder Operator Integer division and remainder are defined by the following relation: A = (A/B)*B + (A rem B) where (A rem B) has the sign of A and an absolute value less than the absolute value aueof B. 41/53 Modulus Operator The result of the modulus operation is such that (A mod B) has the sign of B and absolute value less than the absolute value of B; in addition, for some integer value N, this result must satisfy the relation: A = B*N + (A mod B) 42/53

22 /, rem, mod 연산자의사용예 A B A/B A rem B A mod B /53 Work Library WORK library? 현재읽히는 VHDL 코드의분석결과가 default로저장되는위치. 라이브러리 : 논리적이름, 물리적이름 물리적이름 :HDD 의디렉토리 (folder) 이름 논리적이름 : VHDL 소스내에서의 lib. 이름 둘간대응시키는일 simulator의환경설정에서할일 44/53

23 VHDL analysis VHDL analyzer WORK LIB2 VHDL sources simulation results (waveform or text) VHDL simulator IEEE STD library Simulation commands 45/5353 표준자료형과표준패키지 중요표준패키지 std.textio, std.standard ieee.std_logic_1164, std_logic_unsigned, std_logic_arith 46/53

24 Std.standard 패키지 Boolean, character, integer, real, time, string, bit, bit_vector : type Natural, positive : subtype 47/53 Std.textiotextio 패키지 Plain text file 입출력위한데이터타입, 함수선언 Type: TEXT(file of character), LINE(access string) ti Input( STD_INPUT file), output( STD_OUTPUT file) : file object READ, WRITE, READ_LINE, WRITE_LINE 등입출력 function 48/53

25 IEEE.std_logic_1164 package Std_logic, std_ulogic Std_logic_vector, std_ulogic_vector and, nand, or, nor, xor, xnor, not (logical operator ) Type conversion functions To_bit(std_(u)logic td ( i bit) To_bitvector, to_stdulogic(bit std_ulogic) To_stdLogicVector(bitvector std_logic_ve ctor Falling_edge, rising_edge : 함수 49/53 Std_logic_1164, std_logic_arith std_logic_1164 std_logic std_logic_vector unsigned signed std_logic_arith type UNSIGNED is array (NATURAL range <>) of STD_LOGIC; type SIGNED is array (NATURAL range <>) of STD_LOGIC; 50/5353

26 Std_logic_unsigned/signed 산술 / 관계연산자 ( 내부적으로 unsigned/signed type으로해석해서계산하는 ) overloaded 둘중하나만사용해야혼돈이없음. 예 : function "+"(L: std_logic_vector; R: std_logic_vector) return STD_LOGIC_VECTOR; function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR; function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR; function "+"(L:"(L STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; 51/5353 Std_logic_unsigned/signed 필요성? 내부계산을 signed 로하고싶을때 Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_signed.all; signed 52/5353

27 Std_logic_arith Integer, unsigned, signed, std_logic_vector간 conversion 함수제공 예 :(size: 결과의비트수 ) function CONV_INTEGER(ARG: INTEGER) return INTEGER; function CONV_INTEGER(ARG: SIGNED) return INTEGER; function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED; function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER) return UNSIGNED; function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED; 53/53