MSI & PLD MSI (Medium Scale Integrate Circuit) gate adder, subtractor, comparator, decoder, encoder, multiplexer, demultiplexer, ROM, PLA PLD (programmable logic device) fuse( ) array IC AND OR array sum of product fuse, fuse PLDANDOR array fuse PROM, PLA, PAL
ROM(Read Only Memory), ( ) 8 x 4 ROM K (address) 2 K x n ROM n (data) I 2 I I 3 x 8 decoder 2 3 4 5 6 7 3 inputs(address line) 8 words 4bits/word 2 K x n ROM D 3 D 2 D D K x 2 K decoder, 2 K OR gate K address line, 2 K words, wordn bits
8x4 ROM Structure I 2 I I 3 x 8 decoder 2 3 4 5 6 7 D 3 D 2 D D
32x3 ROM Structure I 4 I 3 I 2 I I 5 x 32 decoder 2 K x n ROM 3 3 K x 2 K decoder2 K OR gate K address line 2 K words wordn bits......... D 3 D 2 D
8x4 ROM Programming I 2 I I 3 x 8 decoder 2 3 4 5 6 7 D 3 D 2 D D
8x4 ROM Programming I 2 I I 3 x 8 decoder 2 3 4 5 6 7 D 3 D 2 D D
ROM (ex) F(A,B) = (,2,3) G(A,B) = (,2) ROM with ANDOR ROM with ANDORNOT A B 2 x 4 decoder 2 3 A B 2 x 4 decoder 2 3 F G F G
ROM : 3bit, : B =, B = A ROM : 3, 4 ( 8x4 ROM) 8x4 ROM
ROM A 2 A A 3 x 8 decoder 2 3 4 5 6 7 8x4 ROM F F 2 F 3 F 4 B 5 B 4 B 3 B 2 B B
ROM ROM ROM fuse (mask programming) PROM (Programmable ReadOnly Memory) fuse PROMfuse EPROM (Erasable Programmable ReadOnly Memory) EEPROM(Electrically Erasable Programmable ReadOnly Memory)
PLD(Programmable Logic Device) PLD (programmable logic device) fuse( ) array IC AND OR array sum of product PLD fuse fuse PLDANDOR array fuse PROM, PLA, PAL PROM inputs Fixed AND array fuses Fused Programmable OR array outputs PAL inputs fuses Fused Programmable OR array Fixed OR array outputs PLA inputs fuses Fused Programmable AND array fuses Fused Programmable OR array outputs
Programmable Logic Array( PLA) PLA AND, OR gatefuse sum of product fuse PLAPROM decoder product term PROM PLA : product term,, PLA IC : 6 inputs, 48 product terms, 8 outputs n inputs n xk fuses n xk fuses k product terms (AND gates) k x m fuses m sum terms (OR gates) m fuses m outputs fuse = 2nxk + kxm + m, ROMfuse = 2 n xm
PLA PLA with 5 inputs, 7 product terms, 3 outputs I I 2 I 3 I 4 AND plane : 5x2x7 fuses OR plane : 7x3 fuses output : 3 fuses I 5 F F 2 F 3
PLA (ex) F (A,B,C) = (4,5,7), F 2 (A,B,C) = (3,5,7) BC A BC A F = AB +AC A B C F 2 = AC+BC F F 2
PLA (ex) F (A,B,C) = (,,2,4) F 2 (A,B,C) = (,5,6,7) BC A BC F = A B +A C +B C F = AB+AC+BC A F 2 = AB+AC+A B C F 2 = A C+A B+AB C F, F F 2, F 2 product term F F 2 PLA
PLA Product A B C term A B C F F 2 AB AC BC A B C C T F F 2
ROM versus PLA ROMs are advantageous when Design time is short Need most or all input combinations (ex, code converter) Little sharing of product terms ROM problems Size doubles for each additional input Can t exploit don t care PLAs are advantageous when Design tools allow logic minimization Relatively unique minterms Minterms are shared among output functions PLA problems Hardwired fanins on OP plane
Programmable Array Logic(PAL) OR gate, AND array buffer inverter AND gatefeedback PLA product term, Cheaper and faster than PLA PLA and PAL PLA Programmable AND array Programmable OR array Sharing of AND term PAL Programmable AND array Fixed OR array No sharing of AND term
PAL I 2 3 4 5 6 2 3 4 5 6 7 8 9 F F 2 I 2 I 3 I 4 7 8 9 2 F 3 F 4 2 3 4 5 6 7 8 9
PAL W(A,B,C,D) = (2,2,3) X(A,B,C,D) = (7,8,9,,,2,3,4,5) Y(A,B,C,D) = (,2,3,4,5,6,7,8,,,5) Z(A,B,C,D) = (,2,8,2,3) AND A B C D W ABC A B CD W= ABC + A B CD W = ABC + A B CD X = A + BCD Y = A B + CD + B D Z = ABC + A B CD + AC D + A B C D = W + AC D + A B C D A BCD A B CD B D W AC D A B C D X= A + BCD Y= A B + CD + B D Z= W + AC D + A B C D
PAL A B C D 2 3 4 5 6 7 8 9 2 A A B B C C D D W W A A B B C C D D W W X X W X Y Z
ROM/PLA/PAL ROM Full AND plane, general OR plane Simple to design Can implement any function of n inputs PLA Programmable AND and OR plane Complex to design Slow because of two programmable planes Can implement any function up to the number of product terms PAL Programmable AND plane and fixed OR plane Moderate to design Fast because of one programmable plane that is smaller than ROM decoder Can implement any function limited by the number of AND or OR terms
I I 2 I 3 I 4 I 5 F F 2 F 3