Hardware User Manual AnyDIO Series SIO-DB32P G G

Hardware User Manual AnyDIO Series SIO-DB32P G G

Product Information Full information about other AJINEXTEK products is available by visiting our Web Site at: www.ajinextek.com Useful Contact Information Customer Support Seoul Tel : 82-31-389-1580~2 Fax: 82-31-389-1583 E-mail : marketing@ajinextek.com G Customer Support Daegu Tel : 82-53-593-3700 Fax: 82-53-593-3703 E-mail : support@ajinextek.com G G AJINEXTEK s sales team is always available to assist you in making your decision the final choice of boards or systems is solely and wholly the responsibility of the buyer. AJINEXTEK s entire liability in respect of the board or systems is as set out in AJINEXTEK s standard terms and conditions of sale Copyright 2001 AJINEXTEK Co.Ltd. All Rights Reserved. ii

Hardware User Manual Rev.0.9 sÿ Contents 1. 개요 1G 1.1. j...1g 1.2....1G 2. 특징 2G 2.1. p Œ s scheme... 2G 3. 설치 4G 3.1. Œ... 4G 3.2. ³ Œ... 4G 4. 구성 5G 4.1. Œ s o... 5G 4.2. p Œ i n... 10G 4.2.1. Œ i n...11g 4.2.2. o... 12G 4.3. SIO-DB32P p v Champ t s o... 21G 4.4. SIO-DB32P p v s o... 23G 5. 액세서리 ( 옵션품목 ) 24G 5.1. p m... 24G 5.2.... 25G 6. 주문정보 (Family) 29G G G G G Revision History Manual PCB Comments Rev. 1.0 issue 1.0 Rev. 1.0 2001. 12. 18 G iii

Hardware User Manual Rev. 1.0 1. 1. 개요 1.1. 서론 AnyDIO sd yd AnyBus Series yd Ÿ d ˆ¹ l l sd, l sd, l ¹ sd r, sd 32 l µ m ƒ. AnyDIO sd yd s SIO-DB32P l16 / l(± TR l wˆ)16 d l sd yd. 1.2. 적용 AnyDIO sd yd z d l v l ˆ¹p ³ m º v, ˆ, d. d s p ˆ¹ º x s p ³ ( p) Industrial measurement ƒ ºd ˆ¹ zƒ d l 24 V ˆ¹p ˆ 1

2. š Hardware User Manual Rev.1.0 2. 특징 2.1. 모듈사양및 scheme 1. SIO-DB32P v 1. SIO-DB32P p e v s SIO-DB32P l 16 l 16 v v m ƒ l (g l ) active r l vƒ r, ƒ l vƒ º. l k {lp p. Interrupt sd l l 4.7 l 16 l 16 v v m write v read l Ž x 12~24Vdc l o 50 Ñ (68Pin CHAMP ƒ v) Option : T36-PR p ˆ 50 APC-EB36 p ˆ 500 l l wˆ l ºm ˆª(z p) sd l ³ z ˆ¹ m z 12V, 24V ˆ¹p ˆ g. ³ lp 2

Hardware User Manual Rev.1.0 2. š 2. SIO-DB32P k l 16 l x z wˆ(12v ~ 24V) l sd Voltage( Ž) l p w LPF l Ž x Low (min : 0v ~ max : 12.0V) l z o High (min : 12.5V! max : 24V) Low (2mA ON) High (2.1mA OFF) l 16 l x z wˆ(12v ~ 24V) l wˆ l «l sd Voltage( Ž) Turn ON/OFF «20 Active Indicator º LED 2 (5VDC, 3.3VDC) «³ l ƒ : 2500VRMS 3

3. ƒ Hardware User Manual Rev.1.0 G 3. 설치 3.1. 하드웨어설치 ƒ y¹ x yd o ek Add-On wˆ AnyPack sd(sio-db32p) Ÿ w k m x yd q d ƒr sd vp Ÿˆ «x yd q d ƒ ƒp ek ƒ. 3.2. 소프트웨어설치 EzConfig 1.0 ƒrƒp EzConfigp ƒ. m k ƒ ˆ ƒ ³ p e m ŽŽ C:\Program Files\EzConfig EzDioAgent.exe ˆ ± r m EzDioAgent m k ƒ n. pž, ƒ ³ p em r ³ Ž ƒ EzDioAgent.exe ˆ ± tp º r. 4

Hardware User Manual Rev.1.0 4. ƒ 4. 구성 4.1. 하드웨어구성및설명 Simplified block diagram A PORT Address Bus Data Bus Control signals PLD (Address Decode & Inerrupt t ) OPTOCOUPLER ISOLATION INTERFACE LOW PASS FILTER OUTPUT OPTOCOUPLER ISOLATION INTERFACE INPUT protection against pole reversal protection against pole reversal B PORT 2. SIO-DB32P 3. SIO-DB32P pv G 3. SIO-DB32P p n yd 120 x 45 mm Ž 3.3V, 5V, 24V (12V) AnyBus yd AnyDIO sd f ek l p ˆ ƒ m l p º x. y¹ x ydp BPFR(PCI Full Size)m ƒ 32 AnyDIO sd m 5

4. ƒ Hardware User Manual Rev.1.0 128 ƒ r AnyDIO ˆp ƒ ek 128 l yd, l 64/ l 64 yd, 128 l yd d m ƒ. BPFRyd ƒ SUB1 CPU m m 3 SUB m DIO 32 AnyDIOp Ÿ 96 DIO. ƒ wx AnyDIO sd ek l 96 (SIO-DI32 3 ), l 96 (SIO-DO32P 3 ), l 48/ l48 (SIO-DB32P 3 )yd d m x. 4. SIO-DB32P p 4 SIO-DB32P z(pld),sub sd, ³ l, l dk {, Indication LED d «. z ª ƒ. wš l 16 l 16 Read v Write, wš y¹ x yd m sd yd ¼p, ƒ wš m yd ƒ vƒ l p d p. wš / l y¹ x yd z p Read Write w² k p mƒ z p º v. wš d p ƒ z xm l p zp umƒ y¹ x yd m sd. p p m l pz l p ªm p l pp z lˆ¹ xº (Change Of State)p v ƒ x v ˆ p ƒ l p vƒˆ y¹ x yd zm ƒ m m. A port, B port 64 PMC(PCI Mezzanine Card) SUB sd k½ Ž r. A port AnyBus x ydmz 5V 3.3V sd. A port ˆ¹ƒ 8, dl 9 ˆ¹, sd ƒ ˆ¹, l ˆ¹ d m ƒ. B port z v, l16/ l16 d l 68P CHAMP 6

Hardware User Manual Rev.1.0 4. ƒ. p l ³ lm v m k d ƒm m l d l y ƒo ƒm q.. 5. p e p Š ƒ n m 16 d l z ³ lm l ºmp (LPF)p ƒ Ž d ˆ w ˆ vƒ p. 7

4. ƒ Hardware User Manual Rev.1.0 6. e p Š ƒ 16 d l z z ˆ¹ ³ lm. 7. ro } 8

Hardware User Manual Rev.1.0 4. ƒ p 7 sd z pp y p. ³ 8 m ƒ r ³ 1 ³ 3 ƒ m, ³ 2, ³ 4 ƒ m ˆ p p ƒ q vƒ ƒ zpp. 8. ro e LED SIO-DB32P sd yd zÿ LED AnyBus x ydmz 3.3V 5V v ˆ ƒ zÿ. pž AnyBus x ƒ r LED d, l Ž Ž r LED d. 9

4. ƒ Hardware User Manual Rev.1.0 4.2. 모듈어드레스맵 9. EzConfig ol pn SIO-DB32P r 4. SUBl l d ml Region BIFR, BV6R, BPFR, BC6R (FULL SIZE / 6U) BIHR, BV3R, BPHR, BC3R (HALF SIZE / 3U) 0000h 1FFFh 0000h 1FFFh 0000h 03FFh SUB 1 dl SUB 1 dl 1Kbyte 0400h 07FFh SUB 2 dl SUB 2 dl 1Kbyte 0800h 0BFFh SUB 3 dl - 1Kbyte 0C00h 0FFFh SUB 4 dl - 1Kbyte p 9 y¹ x ydp BIFR(ISA Full Size) ydm ƒ EzConfig p SUB3 Ÿ SIO-DB32Psd yy p sd3 dl SIO-DB32P ˆ dl y. Address = x dl + 0800h(SUB 3 dl ) yy m ƒ x yd(b) pr x yd yp Ž. 10

Hardware User Manual Rev.1.0 4. ƒ 4.2.1. Œ i n 5. SIO-DB32P l d Offset w 00h Preamble 8 bit R B6h 02h ID 8 bit R 99h (153) 04h Version 8 bit R 00h 06h Software Reset Bit0 : 1(ON)m Writeˆ Software reset 1 bit R/W 00h..0Fh Reserved 10h Output port 1 Bit0..7 : 0(OFF)/1(ON) 8 bit R/W 00h 12h Output port 2 Bit0..7 : 0(OFF)/1(ON) 8 bit R/W 00h 14h Reserved 16h Reserved 20h Input port 1 Bit0..7 : 0(OFF)/1(ON) 8 bit R 22h Input port 2 Bit0..7 : 0(OFF)/1(ON) 8 bit R 24h Reserved 26h Reserved 30h Interrupt Flag port 1 Bit0..7 : 0(OFF)/1(ON) Writeˆ clear 8 bit R 00h 32h Interrupt Flag port 2 Bit0..7 : 0(OFF)/1(ON) Writeˆ clear 8 bit R 00h 34h Reserved 36h Reserved 40h Interrupt Rising edge port 1 Bit0..7 : 0=None / 1=Rising 8 bit R/W 00h 42h Interrupt Rising edge port 2 Bit0..7 : 0=None / 1=Rising 8 bit R/W 00h 44h Reserved 46h Reserved 50h Interrupt Falling edge port 1 Bit0..7 : 0=None / 1=Falling 8 bit R/W 00h 52h Interrupt Falling edge port 2 Bit0..7 : 0=None / 1=Falling 8 bit R/W 00h 54h Reserved 56h Reserved 60h 62h Interrupt Enable control Interrupt status Bit0 : 1(ON)=Enable 0(OFF)=Disable Bit0 : 1(ON)=vƒ, Flag Register clearˆ Clear 1 bit R/W 00h 1 bit R 00h SIO-DB32P dl 1kbyte. ƒ ˆ m 00h ~62h. 11

4. ƒ Hardware User Manual Rev.1.0 4.2.2. o G A. Preamble Register : (00h) Preamble l 0 1 Ÿm m m 10110110 (0xB6) ½. l w ƒ ½um, ID l sd yd ˆ. 7 6 5 4 3 2 1 0 Data Bit D0 - [ 0 ] D1 - [ 1 ] D2 - [ 1 ] D3 - [ 0 ] D4 - [ 1 ] D5 - [ 1 ] D6 - [ 0 ] D7 - [ 1 ] Gi] G B. ID Register : (02h) sd xm ID(identifier)p x yd sd yd Ÿ e ¹ x yd f sd yd Ÿ p ˆx y. SIO-DB32P sd yd ID 10011001 (0x99h). 7 6 5 4 3 2 1 0 Data Bit D0 - [ 1 ] D1 - [ 0 ] D2 - [ 0 ] D3 - [ 1 ] D4 - [ 1 ] D5 - [ 0 ] D6 - [ 0 ] D7 - [ 1 ] G`` G 12

Hardware User Manual Rev.1.0 4. ƒ C. Version Register : (04h) ¹ sd yd «² d ¹ yp ±Ž. l w p r SIO-DB32P w. 7 6 5 4 3 2 1 0 Data Bit D0 - [ 0 ] D1 - [ 0 ] D2 - [ 0 ] D3 - [ 0 ] D4 - [ 0 ] D5 - [ 0 ] D6 - [ 0 ] D7 - [ 0 ] GWW G D. Software Reset : (06h) x yd p p g PC z± ƒ sd yd p º p, PC ƒ m k m 06h w D0 1 Write r sd l 5 ƒ m ƒ. x yd p. 7 6 5 4 3 2 1 0 Data Bit G D0 : ³ ŒGm E. Output Port1 Register : (10h) z l ƒ l p ƒp. Output Port1 Register Write p ˆ Read (Read Back) Write º. 7 6 5 4 3 2 1 0 68 Gj ˆ T36-PR w 36 w 20 Output port 1, bit 0 37 21 Output port 1, bit 1 38 22 Output port 1, bit 2 39 40 23 24 Output port 1, bit 3 Output port 1, bit 4 [ 0 ] = OFF [ 1 ] = ON 41 25 Output port 1, bit 5 42 43 26 27 Output port 1, bit 6 Output port 1, bit 7 13

4. ƒ Hardware User Manual Rev.1.0 F. Output Port2 Register : (12h) z l ƒ l p ƒp. Output Port2 Register Write p ˆ Read (Read Back) Write º. 7 6 5 4 3 2 1 0 68 Gj ˆ w 45 T36-PR w 29 Output port 2, bit 8 46 47 48 49 50 30 31 32 33 34 Output port 2, bit 9 Output port 2, bit 10 Output port 2, bit 11 Output port 2, bit 12 [ 0 ] = OFF [ 1 ] = ON 51 35 Output port 2, bit 13 52 36 Output port 2, bit 14 G. Input Port1 Register : (20h) z l ³ 1 p m «l r p ƒ w p. 7 6 5 4 3 2 1 0 68 Gj ˆ T36-PR w 2 3 w 2 3 Input port 1, bit 0 Input port 1, bit 1 4 4 Input port 1, bit 2 5 6 5 6 Input port 1, bit 3 Input port 1, bit 4 [ 0 ] = OFF [ 1 ] = ON 7 7 Input port 1, bit 5 8 9 8 9 Input port 1, bit 6 Input port 1, bit 7 H. Input Port2 Register : (22h) z l ³ 2 p m «l r p ƒ w p. 7 6 5 4 3 2 1 0 68 Gj ˆ w w 11 11 Input port 2, bit 8 12 13 14 15 16 17 18 T36-PR 12 13 14 15 16 17 18 Input port 2, bit 9 Input port 2, bit 10 Input port 2, bit 11 Input port 2, bit 12 Input port 2, bit 13 Input port 2, bit 14 Input port 2, bit 15 [ 0 ] = OFF [ 1 ] = ON 14

Hardware User Manual Rev.1.0 4. ƒ I. Interrupt Flag Port1 : (30h) ¹ sd yd ƒ l p ƒ ƒ l vƒ r Interrupt Flag Port1 yp «, l vƒ 1 m x. 7 6 5 4 3 2 1 0 Data Bit 68 Gj ˆ T36-PR D0 w 2 w 2 Input port 1, bit 0 D1 3 3 Input port 1, bit 1 D2 D3 4 5 4 5 Input port 1, bit 2 Input port 1, bit 3 [ 0 ] = OFF [ 1 ] = ON D4 D5 6 7 6 7 Input port 1, bit 4 Input port 1, bit 5 Write GRegister Clear D6 8 8 Input port 1, bit 6 D7 9 9 Input port 1, bit 7 J. Interrupt Flag Port2 : (32h) ¹ sd yd ƒ l p ƒ ƒ l vƒ r Interrupt Flag Port2 yp «, l vƒ 1 m x. 7 6 5 4 3 2 1 0 Data Bit 68 Gj ˆ T36-PR D0 w w 11 11 Input port 2, bit 8 D1 12 12 Input port 2, bit 9 D2 D3 D4 D5 13 14 15 16 13 14 15 16 Input port 2, bit 10 Input port 2, bit 11 Input port 2, bit 12 Input port 2, bit 13 [ 0 ] = OFF [ 1 ] = ON Write GRegister Clear D6 17 17 Input port 2, bit 14 D7 18 18 Input port 2, bit 15 15

4. ƒ Hardware User Manual Rev.1.0 K. Interrupt Rising edge Port1 : (40h) Rising ƒ l p ƒ l. Interrupt Rising edge Port1 Register 1, Input Port1 Register l 0 ƒ 1 m x r Interrupt Flag Port1 1 m ±, l vƒ. (, l Enable e) 7 6 5 4 3 2 1 0 Data Bit 68 Gj ˆ T36-PR D0 w 2 w 2 Input port 1, bit 0 D1 3 3 Input port 1, bit 1 D2 4 4 Input port 1, bit 2 D3 D4 5 6 5 6 Input port 1, bit 3 Input port 1, bit 4 [ 0 ] = None [ 1 ] = Rising Edge Active D5 7 7 Input port 1, bit 5 D6 8 8 Input port 1, bit 6 D7 9 9 Input port 1, bit 7 L. Interrupt Rising edge Port2 : (42h) Rising ƒ l p ƒ l. Interrupt Rising edge Port2 Register 1, Input Port2 Register l 0 ƒ 1 m x r Interrupt Flag Port2 1 m ±, l vƒ. (, l Enable e) 7 6 5 4 3 2 1 0 Data Bit 68 Gj ˆ T36-PR D0 w w 11 11 Input port 2, bit 8 D1 12 12 Input port 2, bit 9 D2 13 13 Input port 2, bit 10 D3 D4 14 15 14 15 Input port 2, bit 11 Input port 2, bit 12 [ 0 ] = None [ 1 ] = Rising Edge Active D5 16 16 Input port 2, bit 13 D6 17 17 Input port 2, bit 14 D7 18 18 Input port 2, bit 15 16

Hardware User Manual Rev.1.0 4. ƒ M. Interrupt Falling edge Port1 : (50h) Falling ƒ l p ƒ ƒ l. Interrupt Falling edge Port1 Register 1, Input Port1 Register l 1 ƒ 0 m x r Interrupt Flag Port1 1 m ±, l vƒ. (, l Enable e). 7 6 5 4 3 2 1 0 Data Bit 68 Gj ˆ T36-PR D0 w 2 w 2 Input port 1, bit 0 D1 3 3 Input port 1, bit 1 D2 4 4 Input port 1, bit 2 D3 D4 5 6 5 6 Input port 1, bit 3 Input port 1, bit 4 [ 0 ] = None [ 1 ] = Falling Edge Active D5 7 7 Input port 1, bit 5 D6 8 8 Input port 1, bit 6 D7 9 9 Input port 1, bit 7 N. Interrupt Falling edge Port2 : (52h) Falling ƒ l p ƒ ƒ l. Interrupt Falling edge Port2 Register 1, Input Port2 Register l 1 ƒ 0 m x r Interrupt Flag Port2 1 m ±, l vƒ. (, l Enable e) 7 6 5 4 3 2 1 0 Data Bit 68 Gj ˆ T36-PR D0 11 11 w w Input port 2, bit 8 D1 12 12 Input port 2, bit 9 D2 13 13 Input port 2, bit 10 D3 D4 14 15 14 15 Input port 2, bit 11 Input port 2, bit 12 [ 0 ] = None [ 1 ] = Falling Edge Active D5 16 16 Input port 2, bit 13 D6 17 17 Input port 2, bit 14 D7 18 18 Input port 2, bit 15 17

4. ƒ Hardware User Manual Rev.1.0 O. Interrupt Enable Control : (60h) l p Enable / Disable. '0' e sd l s, '1' e l p (Enable). l wx Ž ƒ ƒr Interrupt Rising edge Register Interrupt Falling edge Register ƒ ek k vƒ r m l (IRQ)p pd. m Interrupt Rising edge Register Interrupt Falling edge Registerp ƒ ˆ ƒ ƒ r Rising Falling p ˆ. 7 6 5 4 3 2 1 0 G Data Bit D0 [ 0 ] = Disable [ 1 ] = Enable P. Interrupt Status : (62h) ¹ sd yd ƒ k l vƒ r Interrupt Status Register 0 1 m x, Interrupt Flag Port s ªp r Interrupt Status ªp. 7 6 5 4 3 2 1 0 G Data Bit D0 [ 0 ] = i G [ 1 ] = i t 18

Hardware User Manual Rev.1.0 4. ƒ 10. Flag } l p p ƒ p p m ¹. p 10 ƒ k l 20h 22h ƒ, xº(rising edge, Falling edge)p ƒ ƒ l p vƒˆ«. ˆ Rising edge, Falling edgep ƒ ˆ Ž r l ˆ¹ p ± ƒ l vƒ. ˆ¹ ƒ l vƒ. p dr k l k p Rising edge, Falling edge s Ž±{ ƒ l Falling edge r IRQ l vƒ ˆ l Rising edge 19

4. ƒ Hardware User Manual Rev.1.0 ˆ¹ d r IRQ g l ˆ¹ vƒ. Interrupter Enable Control(60h) Ž±{ Ž l vƒ. Interrupter Enable Control l. Interrupter Status(62h) l vƒ r l p ƒ ¹ Flag Register yp ªp ˆ Ž, Flag Register vƒ l p Ž ƒ Interrupter Status Registerp y k Flag Register 1 r ¹ Flag Registerp s ªp ˆ l p p. p 11 p 10 k ¹ p. 11. Flag } m p } G 20

Hardware User Manual Rev.1.0 4. ƒ 4.3.SIO-DB32P 모듈보드 Champ 커넥터핀배열및설명 SIO-DB32P l 16, l 16 d l yd r, p z m. z v p ƒ e vdˆ 6p m. DCOM Ports J3 J4 J1 J2 CHAMP 12. BIFR SUB1l SIO-DB32P q n BIFR yd SUB1/CPU sd SIO-DB32P Ÿ p «. g x { zm zio ³ z 68 CHAMP z p sd DCOM Portm n r, 68 DCOM Port SUBsd. DCOM Port AnyField Series µ Ÿ um q ƒ Ž. 6. SIO-DB32P q e 68 CHAMP ƒ l J1 r w ƒr J1 r 1 P1-3_P24V PORT1 +24V 35 P1-3_N24V w ƒr PORT1-3 0V 2 P1_IN0 I Inport 1, bit0 36 P3_OUT0 O Outport 1, bit 0 3 P1_IN1 I Inport 1, bit1 37 P3_OUT1 O Outport 1, bit 1 4 P1_IN2 I Inport 1, bit2 38 P3_OUT2 O Outport 1, bit 2 5 P1_IN3 I Inport 1, bit3 39 P3_OUT3 O Outport 1, bit 3 6 P1_IN4 I Inport 1, bit4 40 P3_OUT4 O Outport 1, bit 4 7 P1_IN5 I Inport 1, bit5 41 P3_OUT5 O Outport 1, bit 5 8 P1_IN6 I Inport 1, bit6 42 P3_OUT6 O Outport 1, bit 6 9 P1_IN7 I Inport 1, bit7 43 P3_OUT7 O Outport 1, bit 7 10 P2-4_P24V PORT2-4 +24V 44 P2-4_N24V PORT2-4 0V 11 P2_IN0 I Inport 2, bit8 45 P4_OUT0 O Outport 2, bit 8 12 P2_IN1 I Inport 2, bit9 46 P4_OUT0 O Outport 2, bit 9 13 P2_IN2 I Inport 2, bit10 47 P4_OUT0 O Outport 2, bit 10 14 P2_IN3 I Inport 2, bit11 48 P4_OUT0 O Outport 2, bit 11 15 P2_IN4 I Inport 2, bit12 49 P4_OUT0 O Outport 2, bit 12 16 P2_IN5 I Inport 2, bit13 50 P4_OUT0 O Outport 2, bit 13 17 P2_IN6 I Inport 2, bit14 51 P4_OUT0 O Outport 2, bit 14 18 P2_IN7 I Inport 2, bit15 52 P4_OUT0 O Outport 2, bit 15 19 N.C 53 N.C 21

4. ƒ Hardware User Manual Rev.1.0 J1 r w ƒr J1 r w ƒr 20 N.C 54 N.C 21 N.C 55 N.C 22 N.C 56 N.C 23 N.C 57 N.C 24 N.C 58 N.C 25 N.C 59 N.C 26 N.C 60 N.C 27 N.C 61 N.C 28 N.C 62 N.C 29 N.C 63 N.C 30 N.C 64 N.C 31 N.C 65 N.C 32 N.C 66 N.C 33 N.C 67 N.C 34 N.C 68 N.C J1 SUB1 J2, J3, J4 SUB2, SUB3, SUB4 ƒm { g z. ekƒ p 8 SUB1 SIO-DB32P sd Ÿ 68 CHAMP J1 ˆ¹ 6 p r, 68 l16, l16, 4 36 p r Ž. 13. CHAMP ƒ p 13 SIO-DB32P sd 68 CHAMP ƒr. 22

Hardware User Manual Rev.1.0 4. ƒ 4.4.SIO-DB32P 모듈보드단자대핀결선및설명 7. T36-PR, APC-EB36 q T36-PR APC-EB36 r w ƒr T36-PR APC-EB36 r w ƒr 1 P1-3_P24V PORT1-3 +24V 19 P1-3_N24V PORT1-3 0V 2 P1_IN0 I Inport 1, bit0 20 P3_OUT0 O Outport 1, bit 0 3 P1_IN1 I Inport 1, bit1 21 P3_OUT1 O Outport 1, bit 1 4 P1_IN2 I Inport 1, bit2 22 P3_OUT2 O Outport 1, bit 2 5 P1_IN3 I Inport 1, bit3 23 P3_OUT3 O Outport 1, bit 3 6 P1_IN4 I Inport 1, bit4 24 P3_OUT4 O Outport 1, bit 4 7 P1_IN5 I Inport 1, bit5 25 P3_OUT5 O Outport 1, bit 5 8 P1_IN6 I Inport 1, bit6 26 P3_OUT6 O Outport 1, bit 6 9 P1_IN7 I Inport 1, bit7 27 P3_OUT7 O Outport 1, bit 7 10 P2-4_P24V PORT3-4 +24V 28 P2-4_N24V PORT2-4 0V 11 P2_IN0 I Inport 2, bit8 29 P4_OUT0 O Outport 2, bit 8 12 P2_IN1 I Inport 2, bit9 30 P4_OUT1 O Outport 2, bit 9 13 P2_IN2 I Inport 2, bit10 31 P4_OUT2 O Outport 2, bit 10 14 P2_IN3 I Inport 2, bit11 32 P4_OUT3 O Outport 2, bit 11 15 P2_IN4 I Inport 2, bit12 33 P4_OUT4 O Outport 2, bit 12 16 P2_IN5 I Inport 2, bit13 34 P4_OUT5 O Outport 2, bit 13 17 P2_IN6 I Inport 2, bit14 35 P4_OUT6 O Outport 2, bit 14 18 P2_IN7 I Inport 2, bit15 36 P4_OUT7 O Outport 2, bit 15 SIO-DB32P sd Ÿˆ ƒ y ƒ ƒr. 14. q 36 ƒ rp 23

5. Žƒƒp( µs) Hardware User Manual Rev.1.0 5. 액세서리 ( 옵션품목 ) 5.1. 모듈악세서리와구성 AnyDIO sd z p 8. AnyDIO q e q m p { Žk. sdr { SIO-DI32 APC-EI36 or T36-PR C68/36TS SIO-DO32P APC-EO36 or T36-PR C68/36TS SIO-DB32P APC-EB36 or T36-PR C68/36TS SIO-DI16 SIO-DO16T SIO-DB16T Ž { A. { 15. C68/36TS C68/36TS Pitch( ) 0.8, 1.27 {. {d AnyBus x yd z (J1, J2, J3, J4) p 1 1m ˆ. 68 1w 35w, 2w 36w,, 34 w 68w Twist Pairp ƒ, 50mA op ¼p. { 1m, 2m, 3m r, ek 5m t¹ µ. 24

Hardware User Manual Rev.1.0 5. Žƒƒp( µs) B. T36-PR p p q APC-EB36 v p rn q 76. q s p p q (ny) IOrn q (m y) AnyDIO sd ƒ l o ³ ºm ( 500 ) d (APC-EB36)p m x (T36-PR)p. T36-PR v APC-EB36 35mm³ k d¹ Ÿ m ƒ ƒ v wƒ ˆ «Ÿ. g d m ˆ«. 5.2. 장치결선 87. SIO-DB32P m t q ( )p l p 17 ˆ BIHRyd SIO-DB32Psd yd Ÿ z p C68/36TS { APC-EB36 p p. p z ƒd p m p d ˆ. p ƒ ˆ ƒd ƒd. 25

5. Žƒƒp( µs) Hardware User Manual Rev.1.0 98. q p 18 p p «. l ºm l ºm 19. q p p 19 l ºm p y. 26

Hardware User Manual Rev.1.0 5. Žƒƒp( µs) 20. T36-PR q pn p 20 T36-PR zµ ƒ p «. k PORT4 OUT0, p v PORT1 IN3. T36-PR l o 50mA ¼p. l l ˆª(z p)m. 27

5. Žƒƒp( µs) Hardware User Manual Rev.1.0 21. APC-EB36 q pn p 21 APC-EB36 zµ ƒ p «. k PORT4 OUT1, pv PORT1 IN3. APC-EB36 z 2 q. p l o 500mA ¼p r, l l ˆª(z p)m. 28

Hardware User Manual Rev.1.0 6. t y(family) 6. 주문정보 (Family) SIO-D B xx P wgag «³iG igt GO lp ygagmi G igt {GaG G{y igt GO lp sgag{{sg igt 9. AnyDIO p r 32 : 32 X]GaGX] I : ig vgag ig igag ig kgagk Ž ˆ igp G 22. AnyDIO Series p µ ƒr SIO-DI32 ( ¹)32 d l sd SIO-DI16 (z ¹)16 d l sd SIO-DO32P ( ¹)32 d l sd SIO-DO16T (z ¹)16 d l sd SIO-DB32P ( ¹)16 d l/ 16 d l, ± TR(2803) l SIO-DB16T (z ¹)8 d l/ 8 d l, ± TR(2803) l 29

Hardware User Manual Rev.1.0 G ô Û Ñ úñä àá. î ä, ÕÑ,, ö ø Ð æ â Ï ààá. è, ÕÑ,, ö éà ÐÑã Ñ ãï ô ÔîÐ ã äàá. á Óù à Ð àá. Ó Óò à úãï, ô è üüã ( ) ô ô à è Û á( Õ, ÕÑ, ú Õ ú, æ ú éà áñ øù) éà áñ ô ïã ú äðû, Ð éà ã äðû, ä àá. ( ) ô ú Ñîä Ó, Ó, Ó éà Õ Ó æ ú àá. ô Ó Ñ æì ( ) ïü Ó Ð ô ï Ñä Óò, ô Ñ Ó Ð í Ó, Ó éà Õ Ó æ á è Óã àá. G 30