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J. of the Korean Sensors Society Vol. 18, No. 1 (2009) pp. 95 101» e z Potentiostat circuits for amperometric sensor Shin-Il Lim Abstract A simple and new CMOS potentiostat circuit for amperometric sensor is described. To maintain a constant potential between the reference and working electrodes, only one differential difference amplifier (DDA) is needed in proposed design, while conventional potentiosatat requires at least 2 operational amplifiers and 2 resistors, or more than 3 operational amplifiers and 4 resistors for low voltage CMOS integrated potentiostat. The DDA with rail-to-rail design not only enables the full range operation to supply voltage but also provides simple potentiostat system with small hardwares and low power consumption. Key Word : Amperometric sensor interface, DDA, CMOS potentiostat 1. yw, y, ƒwš k ü» (amperometric) e(potentiostat) w [1]. w» e» m. ù x l ù w» l š, z xwš d w» w, x y, yƒ ƒ w eƒ š. wr l ƒ y, y š p»» x w» w, d z e xw z, x x w ù, z CMOS» e ü j x x ƒwš. p x { w», w»»» w w x e x w fulœw (Dept. of Computer Engineering, Seokyeong University) Corresponding author: silim@skuniv.ac.kr (Received : October 13, 2008, Revised : December 23, 2008 Accepted : January 21, 2009) ƒ» w š, š, d z y, ƒ y, y š [2-4,10]. w w» w e CMOS» e z w. z wù s»(differential difference amplifier: DDA) w» z w w x ƒ w., s» w w t» z ƒ wù s», ƒ wš, w. wr CMOS e w w p l p ¼ j» w 3.3 V w w xw, s» w MOS p l l (threshold voltage) w w. NMOS s» 3.3 V œ z œm 1V y š w œm y w w. œ œ ƒ w w» w, s» NMOS PMOS 95

96 w œ ƒ w w. 2.» e z» e 2 (electrode) w [11] 3 w ƒ [2-4]. 2 w w w w y yw d ƒ. w w w» w w» e (auxiliary) (AE) ( (counter) ),» (reference) (RE) (working) (WE) 3 w [2-4].» 3 z Fig. 1(a) ù kù 2 s»(a1, A2) w», ƒ w ƒ xw [4]. Fig. 1(a) s» A3 w Rf y y ã - y s»(trans-impedance amplifier: TIA). wr, CMOS e 3.3 V w û w, Fig. 1(a) z w ƒwš d w, y, w y ƒ yw y w w. w w w» w Fig. 1(b) J. Zhang w x (fully differential) eƒ. [4] ù Fig. 1(b) ùkù (A4, A5, A6) ƒ s» w wš wš, s» w f š, w w w ƒ f ƒ, ƒ. w w» w ƒw» w E. Sackinger Hussain Alzaher w s» w, w e w. [5,6] w» s» ƒ w w š, s» j ƒw» w ƒ w. s» w w ü» w. Fig. 1. Conventional potentiostat circuits (a) single-ended implementation and (b) fully differential implementation [4]. 3. e 3.1. z Fig. 2 ùkù z s»(dda) w w e. s» wù w ƒw» ƒ w. s» Fig. 2 ùkù 4 (V PP, V PN, V NP, V NN ) ƒ, V PP -V PN + V NP -V NN w. s» p (1) w [5,6]. V o = A o [(V PP V PN ) (V NP V NN )] (1)» V PP V PN +, V NP V NN ùküš, A o s» v (open loop gain), š V o s» ùkü. s»ƒ Fig. 2 wz 18«1y, 2009 96

» e z 97 Fig. 2. Proposed potentiostat circuits. s» (V PP -V PN +, V NP -V NN ) w (Vcell= Vs) v A o ƒ j w. = = ----------------------- V Cell ( V S ) I out R FW (2)» V S w ƒ, R FW» w, Vcell R FW, Iout. R FW w, w ƒw R FW y y Ioutƒ. z y w» w - yw y y sw z A/D yw. w Fig. 2 - y s» TIA ƒ w. A/D y w. (2)ƒ w» w s» A o ƒ f w 97 db j w. z s» wù w ƒw ƒ w. s» w t v w ƒ š, w. w s» w f w w». w z k, DNA (array) x z w. wr s» œ ü ƒ w w e y w. 3.2. s» z s» e ü z ƒ Fig. 3 ùkù. ƒ w w» w,» E. Sackinger Hussain Alzaher w 2 s» NMOS PMOS w œ ü y k w.» s» v 60 db j œm x s» ù, s» 90 db j š œm (common mode rejection ratio: CMRR) 120 db j w» w jš w folded cascode s» w. s» folded cascode» [7]» w w. j e g (cascode)x, ƒ AB ƒ w, 100 Hz y v 97 db ƒ w. j w (2) Vcell = Vsƒ ƒ w. Fig. 3 ƒx A(V PP, V PN )(y B(V NP, V NN )) ƒƒ PMOS p l NMOS p l (rail-to-rail xk ) w, œ ü ƒ w. A, B e g» w. p l j» (W/L) j w w w ƒ œ w. p l ƒƒ œ ƒ w. wr s» œm x s»ƒ AB t t(push-pull) xk ƒ. p VBP, VBN ƒ p l w p lƒ É w. w w eq l Cc cascode w. eq l Cc Vout p l p w š, BIAS2ù BIAS3ƒ p p l ù w. w q p z ƒ. [8] s» 3.4 ua, w w 1mA¾ ƒ w. w w» w ( w 1mA w w» w 97 J. Kor. Sensors Soc., Vol. 18, No. 1, 2009

98 Fig. 3. Ciruits of differential difference amplifier (DDA). Fig. 4. Results of AC simulation for DDA (gain, phase, CMRR). ) j» j w. 4. x z 0.35 um CMOS t œ w w. e s» z x (circuits simulator) SPICE w x ww. AC x(simulation) œm x ƒ Fig. 4 ùkù. Fig. 4 ƒ q (Hz), v (db) ù kü 100 Hz ¾ 97 db š. Fig. 4 ƒ q (Hz), (phase margin) (degree, o ) š, w 4pF ƒ w 101 o š. Fig. 4 ƒ q (Hz), œm (db) ùkü, œm x wz 18«1y, 2009 98

전류법 기반 센서의 정전압 분극 장치 회로 99 Fig. 5. Results of transient simulation for proposed potentiostat; (a) input voltage signals, (b) current signal through RFW, (c) voltage signal at RE and (d) output voltage of TIA. 약 170 db로서 보통 120 db 이상이 요구되는 센서 시 스템에서 적용할 수 있도록 충분한 큰 값을 보여주고 있다. 만약 센서 부하 캐패시터 성분이 추가되어 더 커 진다 해도 현재 충분한 위상 여유를 가지고 있어, 회로 가 안정적으로 동작하게 된다. Fig. 2의 제안된 회로에서, 센서 저항 R 를 1 MΩ 이라고 가정하고, TIA의 Rf 저항도 1 MΩ을 사용했을 때, 10 KHz의 정현파 입력에 대한 입출력 특성을 Fig. FW 5에 보여 주고 있다. 공급 전원 3.3 V의 전원을 사용해 서 입력 단 V 에는 1.65 V의 공통 전압을 넣고, 또 다 른 입력 단 V 에는 공통전압 1.65 V에 10 KHz의 피 크치 50 mv 신호를 추가하여 Fig. 5(a)와 같이 입력으 로 인가하였다. Fig. 5(b)의 모의실험 결과에 보듯이 R (=1 MΩ)에 피크 값 전류 50 na(=50 mv/1 MΩ)가 흐르는 것을 확인할 수 있다. Fig. 5(c)에는 기준 전극 (WE)에 입력 전압과 동일한 전압이 나타난 것을 확인 99 PN PP FW J. Kor. Sensors Soc., Vol. 18, No. 1, 2009

100 Fig. 6. Results of DC sweep simulation for proposed potentiostat. w. w d w» w ƒw w ƒ ùkù y w, z ƒ» e w w x mw y w. z TIA ù Fig. 5(d) 180 o ëš ƒ y 10 KHz vje 50 mv yƒ ù z ƒ y w y w. w eq l, q x q 10 KHz { û 100 Hz w j w, ƒ š y ùkú. wr cyclic voltametric ƒ q xk w (û q ) qx [9]. ƒ y y w ƒq xk x w y w š, w ƒqxk x w. wr ƒ w y w» w DC (sweep) x ww. e z Fig. 2 TIAƒ k w, x ww. TIA Rf w 1MΩ w x w, Fig. 6 3.3 V w û œ w d w y w., V PP 1.65 V» ƒwš V PN 0V l 3.3 V¾ ƒw, Vout 3.3 V l 0V¾ w y w. 5. yw, y,» y d w» w,» e z w. z x mw w y w. z wù s» w» z w w x ƒ w. s» w w t» e ƒ z ƒ wù s», w š, w. p ƒ w, s» ƒ w w, œ ƒ w w. IT» y» Implantable System (A1100-0702-0117)», IDEC CAD n w». wz 18«1y, 2009 100

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