THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE. vol. 26, no. 1, Jan 서론 PC PMIC(Power Management IC) [1]. PMIC DC-D

Transcription

1 THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE Jan.; 26(1), ISSN (Print)ISSN X (Online) LDO PSR Stability and PSR(Power-Supply Rejection) Models for Design Optimization of Capacitor-less LDO Regulators 주소연 김진태 김소영 Soyeon JooJintae Kim*SoYoung Kim 요약 PMIC (Power Management IC) LDO(Low Drop-Out). Dongbu HiTek 0.5 μm BCDMOS (Geometric Programming: GP) LDO. (monomial) (stability) PSR(Power-Supply Rejection) LDO (Geometric Programming: GP). (phase margin) PSR 9.3 % 13.1 %. PSR,,. PSR. Abstract LDO(Low Drop-Out) regulators have become an essential building block in modern PMIC(Power Managment IC) to extend battery life of electronic devices. In this paper, we optimize capacitor-less LDO regulator via Geometric Programming(GP) designed using Dongbu HiTek 0.5 μm BCDMOS process. GP-compatible models for stability and PSR of LDO regulators are derived based on monomial formulation of transistor characteristics. Average errors between simulation and the proposed model are 9.3 % and 13.1 %, for phase margin and PSR, respectively. Based on the proposed models, the capacitor-less LDO optimization can be performed by changing the PSR constraint of the design. The GP-compatible performance models developed in this work enables the design automation of capacitor-less LDO regulator for different design target specification. Key words: LDO Regulator, Convex Optimization, Geometric Programming, Stability, Power-Supply Rejection(PSR) 2014 () (No. 2014R1A1A ). IDEC. (College of Information and Communication Engineering, Sungkyunkwan University) * (Department of Electronics Engineering, Konkuk University) Manuscript received September 23, 2014 ; Revised November 17, 2014 ; Accepted November 29, (ID No S) Corresponding Author: SoYoung Kim ( ksyoung@skku.edu) c Copyright The Korean Institute of Electromagnetic Engineering and Science. All Rights Reserved. 71

2 THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE. vol. 26, no. 1, Jan 서론 PC PMIC(Power Management IC) [1]. PMIC DC-DC LDO(Low Drop-Out). DC-DC, [2]. LDO,,. LDO RF(Radio Frequency). LDO (stability).. (transient response) (Equivalent Series Resistance: ESR) (left half plane), (ESR) LDO, - [3]. (ESR) LDO. PMIC IC. (power plane) LDO., LDO DC-DC, LDO PSR(Power-Supply Rejection) [4]. LDO PSR,, trade-off. LDO LDO.,, LDO. (global solution) (Geometric Programming: GP) LDO [5]. (GP) (convex optimization) (monomial) (posynomial). (monomial) (posynomial) (GP), (convex) (convex) (convex) (GP). 1 (GP)., (GP) (monimial)., PSR 72

3 LDO PSR 그림 1. Fig. 1. Flow chart of circuit optimization via GP. (GP) (monomial) (posynomial). (GP) LDO PSR (monomial) (posynomial), LDO PSR, trade-off.. 트랜지스터모델링 (GP) (monomial). (L). LDO (Error Amplifier, EA) (saturation),, (subthreshold) (triode). (saturation), (subthreshold), (triode). (L), (I DS ), - (V DS ). (m) - (V GS), (V OV), (V TH), - (C gs), - (C gd), (junction) (C jd ), (g m ), (g ds). (1), (2). (1) (2) a 1 a 4 b 1 b 4 (fitting).. 1 / ( f model 표 1. / % Table 1. Max/mean % modeling error in saturation region. % (/) NMOS PMOS V GS L, I DS, V DS 0.2/ /0.32 V OV L, I DS, V DS 13.79/ /0.08 V TH L, I DS, V DS 0.004/ /0.002 g m L, I DS, V DS 2.52/ /0.28 g ds L, I DS, V DS 1.84/ /0.91 C gs L, I DS, V DS 6.04/ /0.02 C gd L, I DS, V DS 0.14/ /0.01 C jd L, I DS, V DS 0.02/ /

4 THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE. vol. 26, no. 1, Jan 그림 2. LDO Fig. 2. Schematic of capacitor-less LDO regulator. f spice )/f spice ) %. Dongbu HiTek 0.5 μm BCD- MOS., NMOS 10 %. 1 % 16 %.. 제약조건과성능모델 (GP) LDO, PSR. 2 LDO. (EA) 2, - (Miller) (C C ) PMOS. (V REF) 1.24 V. 3-1 트랜지스터의크기와바이어스제약조건. m in m ax m in m ax (3).,,. 4 μm. (EA) (saturation). (EA) (saturation). (4), LDO (quiescent current) (subthreshold), (subthreshold). (5) (EA) M p1 M n M p1 M n1. (EA) (KVL), -. (7) V DD V OUT (6) 74

5 LDO PSR LDO., (EA) KVL [5]. (8) (EA) M p1, M p2, M p3 (differential pair) [7].. R 1. (9), 1.24 V, (9) R 1 R 2. (10) LDO, LDO (dropout) (triode). m ax (11), LDO - (12). 3-2 외부커패시터가없는 LDO 레귤레이터의안정 도모델 LDO. (pole) (phase margin).. (EA) (differential pair). (13) g ds,p5n2 g ds,p3n3 (g ds,p5 +g ds,n2 ) (g ds,p3 +g ds,n3 ) (monomial). (subthreshold). (14) R OUT (g ds,pass ) R 1 R 2 (monomial). (feedback factor) R 1 R 2. (15) 75

6 THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE. vol. 26, no. 1, Jan (13)(15) LDO (A). (16) (EA) (dominant pole) (non-dominant pole). LDO, (dominant pole). LDO (dominant pole) (EA). (17) (miller) -, -. (subthreshold) (Miller), (dominant pole) (monomial) 1.5. LDO,. (18) (C L) -. (C L ) LDO (metal layer). (EA),. (19) (EA),. (20) - - (feed-forward zero). (21) (non-dominant pole) (dominant pole). (phase margin) tan tan (22), (GP) (phase margin) (arctan) (monomial). (arctant) tan (23) (monomial). 3-3 외부커패시터가없는 LDO 레귤레이터의 PSR 모델 76

7 LDO PSR PSR LDO (superposition method). (differential) 2 (EA), (differential pair) (EA). PMOS PSR. PM- OS (common-gate), AC LDO.. 외부커패시터가없는 LDO 레귤레이터의최적화결과 (24) 4-1 PSR 제약조건변화에따른외부커패시터가 없는레귤레이터의성능최적화 PSR 54 db 46 db LDO. Linux CVX Matlab Toolbox [8], PSR Intel (R) Xeon (R) CPU X5650 GHz 4 GHz. 3 PSR LDO (quiescent current). Cadence Spectre. Dongbu HiTek 그림 3. PSR LDO (I quiescent) Fig. 3. Optimization results of quiescent current of LDO regulator and area of pass transistor according to various PSR specification. 0.5 μm BCDMOS. PSR (phase margin) 45, (dropout) 0.3 V. (24), PSR (EA),., (EA) LDO PSR. PSR (EA), (EA) (dominant pole). (phase margin) 3. 3 (quiescent current) 50 % PSR 8 db, 77

8 THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE. vol. 26, no. 1, Jan PSR 13.1 %., (phase margin), 9.3 %., PSR 40 (phase margin) (stability). 3 LDO PSR PSR, (quiescent current) LDO. 4-2 외부커패시터가없는 LDO 레귤레이터의최적설계결과 2 (GP) LDO. PSR db, (phase margin) 45., 100 ma, 1.8 V. (dropout), DC 6.25 %,. (A) (phase margin), (monomial) (posynomial) DC., 21.1 %. PSR 12.8 %., LDO (dominant pole) (monomial) 표 2. LDO Table 2. Comparison results between model and simulation of capacitor-less LDO regulator. (%) I MAX(mA) V dropout(v) V OUT(V) I quiescent(ma) PSR (@DC) (db) A (db) Phase margin( ) f c(mhz) 표 3. (GP) Table 3. Result of GP optimization. Value W p1/l p1(μm/μm) 1.2/2.85 W p2/l p2(μm/μm) 79.45/2.42 W p3/l p3(μm/μm) 22.84/2.42 W p4,5/l p4,5(μm/μm) 30.62/0.5 W n1,2/l n1,2(μm/μm) 1.55/0.5 W n3/l n3(μm/μm) 1.2/0.67 W pass/l pass(μm/μm) 11885/0.5 R 1(Ω) R 2(Ω) C L(pF) 10 I BIAS(μA) 1.92 (Miller) 1.5,. 3 (GP), 2 (EA),, 78

9 LDO PSR.. 결론 Dongbu HiTek 0.5 μm BCDMOS NMOS PMOS, - (monomial). LDO (stability) PSR (monomial) (posynomial) LDO. (phase margin) PSR 9.3 % 13.1 %. (saturation) (subthreshold), (phase margin) PSR LDO (phase margin) PSR. (GP), PSR LDO, PSR.. References [1] K. N. Leung, P. K. T. Mok, "A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency", IEEE J. Solid-State Circuits, vol. 37, no. 10, pp , Oct [2],,, " LDC ",, 24(8), pp , [3] S. DasGupta, P. Mandal, "An automated design approach for CMOS LDO regulators", in Proc. Int. Symp. Asia South Pac. Des. Aut. Conf., pp , Jan [4] M. El-Nozahi, A. Amer, J. Torres, K. Entesari, and E. Sanchez-Sinencio, "High PSR low drop-out regulator with feedforward ripple cancellation technique", IEEE J. Solid- State Circuits, vol. 45, no. 3, pp , Mar [5],,,, "Differential amplifier design based on modeling with GP optimization",, 23(1), p. 190, [6] J. Kim, J. Lee, L. Vandenberghe, and C. K. K. Yang, "Techniques for improving the accuracy of geometricprogramming based analog circuit design optimization", in Proc. Int. Conf. Comput. Aided Des., pp , Nov [7] M. Hershenson, S. Boyd, and T. H. Lee, "Optimal design of a CMOS op-amp via geometric programming", IEEE Trans. Comput-aided Design Integr. Circuits Syst., vol. 20, no. 1, pp. 1-21, Jan [8] M. Grant, S. Boyd, and Y. Ye, CVX: Matlab Software for Disciplined Convex Programming, [Online]. Available: 79

10 THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE. vol. 26, no. 1, Jan : () : () : [ 주관심분야 ] EMI/EMC, 1997: () 1999: Stanford University () 2004: Stanford University () : Intel Corporation : Cadence Design Systems 2009: [ 주관심분야 ] Device and Interconnect Modeling, Power Integrity, Signal Integrity, Computer-Aided Design, Electromagnetic Compatibility 1997: () 2004: University of California () 2008: University of California () 2012: [ 주관심분야 ],, CMOS, 80