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2 Product Information Full information about other AJINEXTEK products is available by visiting our Web Site at: Useful Contact Information Customer Support Seoul Tel : ~2 Fax: marketing@ajinextek.com Customer Support Daegu Tel : Fax: support@ajinextek.com Customer Support Cheonan Tel : ~2 Fax: ljh001024@ajinextek.com AJINEXTEK s sales team is always available to assist you in making your decision the final choice of boards or systems is solely and wholly theresponsibility of the buyer. AJINEXTEK s entire liability in respect of the board or systems is as set out in AJINEXTEK s standard terms and conditions of sale Copyright 2001 AJINEXTEK co.ltd. All rights reserved. ii

3 Hardware Chip User Manual Rev. 4.0 sÿ Contents 1. 개요 1 2. 사양 Œ Block Diagram i t o 기능개요 h x PRESET PULSE DRIVE CONTINUOUS DRIVE SINAL SEARCH-1 DRIVE SINAL SEARCH-2 DRIVE HOME SEARCH DRIVE SENSOR POSITIONIN DRIVE MP DRIVE p q p y q p p y p t v p n u i Žw i Œ i t w m (Internal Ring Counter) m Žw m (External Ring Counter) m w y Žw y w/žw Scale Žw Clear Žw tµ s iii

4 sÿ Hardware Chip User Manual Rev h / h p i t Œi (Off-Range) m PWM i Žw (Bandwidth) m (Script) qm(caption) Address Map Port 설명 DATA1 WRITE PORT DATA2 WRITE PORT DATA3 WRITE PORT DATA4 WRITE PORT COMMAND WRITE PORT DATA1 READ PORT DATA2 READ PORT DATA3 READ PORT DATA4 READ PORT COMMAND 설명 COMMAND h² COMMAND o COMMAND µ tu TIMIN DATA BUS TIMIN i TIMIN i TIMIN i TIMIN 보충사항 ICLK i ƒ PARAMETER u iv

5 Hardware Chip User Manual Rev. 4.0 sÿ 8.3. DATA ERROR S UP, CONST, DOWN PULSE s ( ) i žm LIMIT Œ 2 CHATTERIN Œ 2 COUNT POINT 외형치수 부록 Address Map PORT o COMMAND h²(compact, register map) COMMAND w o Revision History Manual PCB Comments Rev. 4.0 issue v

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7 Hardware Chip User Manual Rev 개요 CAMC FS CAMC 5M ƒ Single Motor Control LSI. CPU w ³ p Commandp Stepping v Servo Motord v. ekƒ CPU z p ˆ«rƒ s p ¹ r,, wk d v k wk dp ƒ g S curve m± m. CAMC FS s vƒ x ˆ ˆ Commandp vp Script/Caption. s softwarem ¹. sd ±kv d m ƒ r, ² l x. CAMC FS ƒ š. S Curve S curve /. ( ) p p m ƒ. 4 Mpps ² l ² l l ªl MHz( ± )p m Ž 4 Mpps(pulse per second). 8/16 bit CPU interface 8 bit v 16 bit Data busp. 7 dk { sd dk {, ˆ¹ v dk {, ² ƒ dk {, ƒ dk {, MP dk {p. d z ² v 2 1 w, 2 w, 4 w ƒ vƒ ˆ¹p z ƒ r ² ³Ÿk d y. ƒ Data Error ± ƒ l, ƒ l dk { ˆ 1

8 1. Hardware Chip User Manual Rev. 4.0 dk {p ˆ r vm n. l vƒ CAMC FS l vƒ 32 l l p g z pd 32 l p ª. q l CAMC-FS p SYNC(Synchronization) l. l ºƒº dk {p ˆ k ² p l Ž. ekƒ, l CAMC-FS ² l ˆ ˆ. ² l CAMC FS s dk { q ² lwˆ ƒ m 8 o l wˆ. ² l ¹ Software m ƒ. Limit CAMC FS over-run limit ˆ¹mƒ / w / limit ˆ¹ l r l lx x. «CAMC FS z z Ÿ x p «l ƒ. z z Ÿ «y r, p. ˆ p ² dk { ˆ ˆ ˆ pm, z l ² m ˆ Ÿp ˆ«. PWM l dk { PWM(Pulse Width Modulation) ˆ¹p l. ªp (Script) p CAMC FS ˆ 96 rl dp Ž ˆ. tp(caption) s p 96 rl p Ž º. 2

9 Hardware Chip User Manual Rev ƒ ˆ¹ v ˆ¹ ƒ z ƒ l ƒ ˆ¹ v ˆ¹p Enable/Disable. ƒ v ˆ¹ Enable/Disable ƒ Registerº Software m. sd º sd ƒ ek dk { rl ˆ» dk { p,» d m dk {. d l (A, B, Z l p) A, B l m z ¹ p Ž Z z p timing clear. e Z l ˆ¹ 4 x l ˆ¹ ƒ. l ³ ƒ z ƒ l limit ƒ ˆ¹ l p ƒ ˆ¹ l p. Tclk~255*Tclk x ƒ. (Tclk : clock ) z p z p r, M_DATA, P_DATAp ƒ 2 32-bit l. p k ƒ x ƒ t m. z p z p r, M_DATA, P_DATAp ƒ 2 32-bit l. p k ƒ x ƒ t m. Scale Scale k ² scale w ª p«r z/ z +1., ƒ scale w wm. e Scale 8-bit(0~255) r z/ z m. pv ƒ z/ z ƒ ek p pv m. 3

10 1. Hardware Chip User Manual Rev. 4.0 x l (4 ) x l (8 ) x ˆ¹ IO l ƒ (1 ) 4

11 Hardware Chip User Manual Rev 사양 2.1. 사양 : +5V ± 5%, +3.3V ± 5% (40,47,89,90w vdˆ +3.3V. r VDD +5V g +3.3V ) clock : MHz(standard) : 1 ƒ x : 16-bit (65,535) / ƒ x : 16-bit (65,535) w ƒ x : ~ 250( clock MHz) w ~ pps 1 w ~ 16,384 pps 125 w ~ 2,047,932 pps 250 w ~ 4,095,375 pps Slow down point ƒ x : 32-bit (0 ~ 4,294,967,295) dk { sd : ² dk {, dk { ˆ¹ -1 dk {, ˆ¹ -2 dk { dk {, ƒ dk {, MP dk { wk d : wk d, k wk d : / Full S, / Quasi-S / ƒ, d Servo Interface : d ² wˆ l ² wˆ : 1² /2² wˆ ƒ ( 8 o ) ³Ÿk : 15-bit ( ~ 32,767) Limit : ±ELM(Emergency stop Limit), ±SLM(Slow down stop Limit), SSTOP(Slow down Stop), ESTOP(Emergency Stop) rl : SSC(Slow down Stop Command), ESC(Emergency Stop Command) CPU ³ : 8/16 bit ƒ x l : 4 TTL Schmitt Trigger Level x l x l ƒ : : 8 CMOS Level, 8mA 1 Comparator : z/ z 32-bit 1 Ž Interrupt vƒ : l source 32 ƒ q : z sync l ˆ¹ ² l ˆ ENABLE / DISABLE ƒ 5

12 2. Hardware Chip User Manual Rev. 4.0 z, z : 32-bit l : (UP/DOWN l), 2 (1, 2, 4 w) ¹ Read Port : 13-bit pv : z, z ƒ, Slow Down Stop, Emergency Stop 2.2.Block Diagram jzq yq ~Q h YaW k ^aw pjsrvjsr i zjvu{yvs pu{lyuhs{ptpun nlulyh{vy _ X Y Z [ X Y Z [ kh{h~yp{li mmly kh{hylhki mmly jvtthuk yln zš Vjˆ ylnpz{lyz pu{lyuhs jv u{ly jvtwhyh{vy Qž Y_T ŒŽ š Œ jvtwhyh{vy Qž Y_T ŒŽ š Œ l{lyuhs jv u{ly kl}ph{pvu kh{h jhsj sh{vy jvtthuk kljvkly }hyphisl zwllk yln lz{w zz{w jvu{yvs zpn XZ kyp}l z{vw jvu{yvs w szl nlulyh{vy tvk sl X]š ŒŒ ˆ ˆ XZOsziP [OsziP [OtziP tvup{vy kh{h zlslj{vy w szl wwsz kpy i z pu ZaW v { ZaW lj w ljku tvup puw hst Tzst Rzst Tlst Rlst zpnuvjvt luk tk XYaW k X\a_ _VX]zls lj w ljku 2.1. CAMC FS r~ 6

13 Hardware Chip User Manual Rev 입출력핀배치도 { X Z Y [ ] \ ^ ` _ X W X Y X X X Z X [ Z[ ZX ZZ ZY Z_ Z\ Z^ Z] [Y Z` [X [W ^ Z ^ X ^ Y ] ` ^ W ] _ ] ] ] ^ ] \ ] Z ] [ ] Y ] W ] X \ ` \ ^ \ _ \ ] \ [ \ \ \ Z \ X \ Y ^ [ [Z [[ [] [\ `[ `\ `] `W `Z `X `Y _] _` _^ \ _X _[ _Y _Z k X k W y l z l { Q h Y h X h W n u k } j j j z Q y k Q ~ y Q pu { v { n u k t v u p u z s t u l s t w z s t w l s t n u k k v ~ u v { j v u z { v { w v { pu w v z } j j n u k h s h y t z z { v w l z { v w w ~ t v { y pn n l y v { t h y r pj s v { pj n v { } j j n u k l j s v { l j n v { l w w v {X v {W }jj nuk i z v { puz puy puxopuklp puwovynp p }jj p nuk nuk pjsrv pjsr vjsr v { wws z v { tk v {YVkXW tk v {ZVkXX tk v {[VkXY tk v {\VkXZ nuk p nuk p }jj p }jj tk v {]VkX[ tk v {^VkX\ tk v {_Vl pvw tk v {`Vl vx tk v {XWVl vy nuk }jj tk v {XXVl vz \W [^ [` [_ p }jj nuk w s zl v { kpy v { ^ ` ^ ^ ^ _ ^ \ ^ ] _ W l t w l j k u n u k l j w z pn u v { Vj t k l u k t k v { X Y Vl v [ `_ `` XWW `^ tk v {WVk_ tk v {XVk` }jj nuk X ] X \ X ^ X ` X _ Y W Y Y Y X Y Z Y \ Y [ Y ] Y^ z u j n u k } j j k ^ k ] k \ n u k } j j k [ k Z k Y n u k } j j Y ` Y _ Z W v { Y v { Z _ X ] z l s CAMC-FS2.1 mww[^www rvylh 2.2. p 7

14 2. Hardware Chip User Manual Rev 핀의기능설명 D7 ~ D0 (Data Bus) STATE l 8 Bit 3 State w Data Bus. CPU Data Bus. D15 ~ D8 (Data Bus) *(MD7~MD0 m ) STATE l 8 Bit 3 State w Data Bus. CPU Data Bus. 16-Bit Data Access sd(8_16sel = High) Data Busm, 8-Bit Data Access sd ƒ MD7~MD0(s )p l ˆ¹m A2 ~ A0 (Address) --- l *(A0 16bit accessˆ Ž ) CAMC-FS 8 ³ p ƒ. CPU Address Bus. CS* (Chip Select) --- l CS* = Lm m CAMC-FS Access. RD* (Read Strobe) --- l z w² ˆ RD* = Lm. WR* (Write Strobe) --- l z w² ˆ WR* = Lm. RESET* (Reset) --- l RESET* = L CAMC-FS Reset m. Tclk*8 LOW e º.(Tclk = Main clock ) ICLK (Input Clock) --- l ªl l. CAMC-FS ICLK l MHzy ± ªl CAMC-FS y. OCLK (Output Clock) --- l l ªl 2z ˆ¹p l. ) MHzp ICLKm r OCLK l 8.192MHz. 8

15 Hardware Chip User Manual Rev DIR/PULSE (Direction / Pulse) --- l s dk { lˆ¹m l ˆ¹. dk { w ˆ¹ v Duty 50% dk { ² l. PWM_OUT(PWM output) --- l PWM ˆ¹p l. ˆ¹ ¹ p«pwm ˆ¹ um DC s. PPLS (P_Pulse) --- l ªl l 2 ³(OCLK l 1 ³)p«High l ² ˆ¹p l. BUSY (Busy) --- l dk { (PULSE l ) BUSY = H m ¹ ² l «ˆ¹.. q dk { ˆ SYNCˆ¹ v PULSE l n» INPˆ¹ Ž BUSY = Hm. UP (Up) --- l dk { UP = Hm dk { «ˆ¹. CONST (Constant) --- l dk { CONST = Hm ¹ d dk { «ˆ¹. DOWN (Down) --- l dk { DOWN = Hm ¹ dk { «ˆ¹. 8_16SEL (Bus Select) --- l 8-bit Data Bus(Low) 16-bit Data Bus(High) Accessp l ˆ¹. ˆ¹p m 16-bit CPU 8-bit CPU s ³. ˆ¹ Low e MONI (Monitor Select) --- l MD12~MD0m l ˆ¹p ƒ ˆ¹. MD12~MD0 ¹ ³Ÿk p l Monitor Data ˆ¹mƒ MONI l ek l x. MONI = Low, SIN ³Ÿk z¹p, MD12~MD0 ³Ÿk p l. ˆ ³Ÿk 16-bitª r 13-bitp l. MONI = High SIN z¹p, MD12~MD0 p l. ˆ 16-bit ª r 13-bitp 9

16 2. Hardware Chip User Manual Rev. 4.0 zm l. 16-bit Data Bus Access sd(8_16sel = High) ƒ MD7~MD0 w m um 8-bit Data Bus Access sd ƒp n. SIN/ CMD_END (Monitor Data SIN/ COMMAND END) --- l Monitor Data z¹p l, z ƒ rl ˆ p «ˆ¹. 8-bit Data Bus Access sd(8_16sel = Low) ƒ Monitor Data(MD12~MD0) z¹p l. Monitor Data z¹ (Low) w º «, (High) e w º «. Monitor Data ³Ÿk z¹p «.( =Low, =High) 16-bit Data Bus Access sd(8_16sel = High) ƒ z rl p e Highp l, rl ˆ mƒ n Lowp l. MD12 ~ MD00/DATA15~DATA8(Monitor Data/Msb Data Bus) --- l s p l 16-bit Data Busp 8-bit Data Busm ˆ¹. 8/16SEL = Low (8bit Data Bus Access sdm ƒ ) MONI ˆ¹ ƒ (¹ g ³Ÿk )p l. l z¹p ³ Ž 13-bit. MONI = High ¹ l (16-bit) 13-bitp l. MONI = Low ³Ÿk (16-bit) 13-bitp l. 8_16SEL = High (16bit DATA BUSm ƒ ) DATA15~DATA8( 8-bitm Data Bus. e r 5bit EUO/EUIO ƒ ep. ESTOP (Emergency Stop) --- l l ˆ¹. dk { ESTOP = High l r ² l. g ESTOP ˆ¹ PULSE l, END STATUS READ PORT( dk { «l ) ESSED BIT( «bit) 1m. SSTOP (Slow Down Stop) --- l l ˆ¹. dk { SSTOP = High l r ˆ ² l. g SSTOPˆ¹ ² l, END STATUS READ PORT SSSED BIT( «bit) 1m. CAMC-FS ˆ» vm r, ˆ» vm Ž ˆ¹ rl l e d m ² l.. +ELM (+Emergency Limit) --- l º w LIMIT l ˆ¹. º w Drive Active Level l r ¹ l 10

17 Hardware Chip User Manual Rev PULSE Not Activem» PULSE l., +ELMˆ¹ Active Level User Program. g, +ELMˆ¹ PULSE l, END STATUS READ PORT z ƒ n «BIT 1m. -ELM (-Emergency Limit) --- l º w LIMIT l ˆ¹. º w Drive Active Level l r ¹ l PULSE Not Activem» PULSE l., -ELMˆ¹ Active Level User Program. g, -ELMˆ¹ PULSE l, END STATUS READ PORT z ƒ n «BIT 1 m. +SLM (+Slow Down Limit) --- l º w LIMIT l ˆ¹ º w Drive Active Level l r Start / Stop Speed l PULSE Not Activem rƒ» PULSE l., +SLMˆ¹ Active Level User Program. g, +SLMˆ¹ PULSE l, END STATUS READ PORT z ƒ n «BIT 1 m. -SLM (-Slow Down Limit) --- l º w LIMIT l ˆ¹ º w Drive Active Level l r Start / Stop Speed l PULSE Not Activem rƒ» PULSE l., -SLMˆ¹ Active Level User Program. g, -SLMˆ¹ PULSE l, END STATUS READ PORT z ƒ n «BIT 1 m. ALM (Alarm) --- l Motor Drivermz ALARM l ˆ¹. Drive Active Level l r ¹ l PULSE Not Activem,» PULSE l., ALMˆ¹ Active Levelv ALMˆ¹ ˆ º/tº User Program ƒ. g, ALMˆ¹ PULSE l END STATUS READ PORT alarm n «BIT 1m. INP(Inposition) --- l Motor Drivermz INPOSITION l ˆ¹. PULSE l n» Active Level l e BUSY = Hp. INPˆ¹ Active Levelv INPˆ¹ ˆ º/tº User Program ƒ. 11

18 2. Hardware Chip User Manual Rev. 4.0 SYNC (Syncronise) --- l Start l. Drive Commandˆ»k SYNC = L l Ž PULSE l ˆ Ž.» SYNC = H l m PULSE l ˆ. q m Ž SYNC = Hm ˆ Sync ƒ disablem, ˆ PULSE l ˆ. ECUP (External Counter Up) --- l External Counter l ˆ¹. UPˆ¹ g 2 ˆ¹ A ˆ¹p l. l (UP/DOWNˆ¹, 2 ˆ¹ xº v 2 ˆ¹ˆ w( ) ) User Program. ECDN(External Counter Down) --- l External Counter l ˆ¹. DOWNˆ¹ g 2 ˆ¹ B ˆ¹p l. l (UP/DOWNˆ¹, 2 ˆ¹ xº v 2 ˆ¹ˆ w( ) ) User Program. ICL (Internal Counter Low) --- l z Address Comparate p l. Internal Comparate Data > Internal Counter ˆ ICL = Hm. IC (Internal Counter reat) --- l z Address Comparate p l. Internal Comparate Data < Internal Counter ˆ IC = Hm. ECL (External Counter Low) --- l z Address Comparate p l. external Comparate Data > external Counter ˆ ECL = Hm. EC (External Counter reat) --- l z Address Comparate p l. external Comparate Data < external Counter ˆ EC = Hm. OUT3 ~ OUT0 (Universal Output) --- l User Program ˆ l x l. 12

19 Hardware Chip User Manual Rev IN3 ~ IN0 (Universal Input) --- l User Program ˆ x l ˆ¹. Signal Search-1 Drive, Signal Search-2 Drive ƒ ˆ¹m, tp(caption) v ªp (script) e ƒ m m k. y ƒ m IN1(Index) Z l m. INT (Interrupt) --- l l lˆ¹. l Flag l p Read r l ƒ. INTˆ¹ l Resource, Mask l, Active Level User Program. EXPP* (External Puls Pulse) --- l (+) w MP dk { l ˆ¹. dk { (BUSY= L ) Active r MP dk { (BUSY= H ) ² p l. EXMP* (External Minus Pulse) --- l (-) w MP dk { l ˆ¹. dk { (BUSY= L ) Active r MP dk { (BUSY= H ) ² p l. MARK --- l Sensor Positioning / / dk { ƒ sd º ˆ¹. Sensor Positioning / / dk { ƒ MARK ˆ¹ Active Levelm xº ˆ ƒ vp ƒ ² p«. MARK Active Level User Program. TRIER_OUT --- l ƒ ƒ ¹ pp l trigger ˆ¹. l Active Level, Active Level l ˆ ƒ v trigger l g ƒ. EUO 4~1, EUIO0 (MD12~MD8 m ) --- l, l/ l ƒ l, / l. ƒ ek EUO4~1, EUIO0 MD12~MD8 ƒ. EUO4~1 x l, EUIO0 x l. EUIO0 z l ƒ ek l m VDD +5V g +3.3V l. z. ND 5V g 3.3V ND. z. I_VDD 13

20 2. Hardware Chip User Manual Rev V l. 40, 47, 89, 90w m vdˆ +3.3V. z. I_ND 3.3V ND. z. v ND tw. 14

21 Hardware Chip User Manual Rev 기능개요 CAMC-FS l ± 4MPPS v Override, k Override, ƒ, S (³t ƒ) ˆ¹ CAMC-5M Compatible Single Chip Motor Control LSI. sd Parameter User Program ƒ x r, p ˆ¹. Motor Stepping v Servo Motor r 100 Pin QFPm ƒ 드라이브기능 Preset Pulse Drive s p ƒ k( p)p«ˆ«e dk {m w. k vp ƒ» dk {p ˆ r p«² ( k)p l», pp«s p ˆ«. e ± ƒ. k x. ³ ( ˆ ) ƒ m ƒ ( y), ³ ² p. ˆ ² y m» d m ² r, ³ ƒ ¹ l ² ˆ ƒ ˆ m. ² 0(0x ) ~ 4,294,967,295(0xFFFFFFFF)., PM register change z. š ŒŒ ˆ ˆ O šp ŒŠ š ˆ Vš OšŒŠP 3.1. Preset Pulse Drive Profile ** CAMC-FS2.1 ƒ 1 ² p«m wx m Ž. 15

22 3. Hardware Chip User Manual Rev. 4.0 <CW w ˆ> command Data Comment 0xC4 0x Script1 ƒ 0xC0 0x000002AA Script1 ƒ command, dk { ˆ ˆ p wk d ˆ (1 ² wk d) 0xA0 0x Preset Pulse Drive(CWw, 2 ² ) ** ƒ m ˆ Ž m CWw m 1 ² p«. <CCW w ˆ> command Data Comment 0xC4 0x Script1 ƒ 0xC0 0x000002AA Script1 ƒ command, dk { ˆ ˆ p wk d ˆ (1 ² wk d) 0xA5 0x Preset Pulse Drive(CCW w, 2 ² ) ** ƒ m ˆ Ž m CCW w m 1 ² p« Continuous Drive s e dk {. Start command ˆ» ² l ˆ, g command ˆ dk {. command o(, ) ek m±. š ŒŒ ˆ ˆ O šp oj µ ŒŠ š ˆ Vš Š OšŒŠP 3.2. Continuous Drive Profile Signal search-1 Drive ƒ ƒ g Ž dk {. dk { start command 16

23 Hardware Chip User Manual Rev ˆ» ƒ lˆ¹ (edge)p. š ŒŒ ˆ ˆ O šp ŒŠ š ˆ Vš Š OšŒŠP 3.3. Signal search 1 Drive Profile Signal search-2 Drive s p pp d m ƒ º ˆ«e dk {. Signal search-1 Drive ƒ ˆ«p, d m ˆ dk { um k e. š ŒŒ ˆ ˆ O šp š ˆ Vš d ŒŠ OšŒŠP 3.4. Signal Search 2 Drive Profile Home Search Drive Home Search Drive dk { ˆ rl m y. CW(+), CCW(-) w m r ˆ¹ l(in0/or) edge point(rising/falling)p ƒ. p 3.5. (+) w ƒr p. (+)w Drive Start, Positive Edge ƒ ORˆ¹ Active High, Drive Start» Limit ˆ¹p r p 17

24 3. Hardware Chip User Manual Rev. 4.0 [ Y \ ] X Z OTPsptp{ ORPsptp{ vyn (+)Limit. e Sear (+)w Signal Search-1 Drive Start (-)w Signal Search-1 Drive Start OR Negative (+)w Signal Search-2 Drive Start 3.5 Hom ch Drive Profile OR Positive pv l w º ˆ active le vel ˆ¹ l r w ˆ x. Home Search Drive limit l edge Sensor Positioning Drive Sensor Positioning Drive ƒ ˆ¹(MARK) lz ² p«dk {. ƒ ˆ¹ MARK l m l r ˆ¹ Active Level ƒ x. MARK ˆ¹ l» ² ƒ x 2~4,294,967,295(0x ~0xFFFFFFFF). Sensor Positioning Drive, 0xb0(+w ), 0xb1(-w ) Sensor Positioning Drive MARK ˆ¹ edge r, ² p«dk {. Sensor Positioning Drive ƒ MARK ˆ¹ l. 18

25 Hardware Chip User Manual Rev zwllk thpt t zwllk z{hy{ w zwllk thyr kljlslyh{pvu wvpu{ {ptl 3.6. Sen sor Positioning Drive Ï(+, - ) Profile Sensor Positioning Drive, 0xb2(+w ), 0xb3(-w ) Sensor Positioning Drive MARK ˆ¹ edge r, ² p«rƒ dk {. Sensor Positioning Drive ƒ MARK ˆ¹ l Start/Stop Speed datam d. zwllk thpt t zwllk z{hy{ w zwllk thyr kljlslyh{pvu wvpu{ {ptl 3.7. Sensor Positioning Drive Ï(+, - ) Profile Sensor Positioning Drive, 0xb4(+w ), 0xb5(-w ) Sensor Positioning Drive MARK ˆ¹ edge r ² p«d r ƒ dk {. Sensor Positioning Drive ƒ m Start/Stop Speed datam d. 19

26 3. Hardware Chip User Manual Rev. 4.0 zwllk z{hy{ w zwllk {ptl thyr 3.8. Sensor Positioning Drive Ï (+, - ) Profile MP Drive z 2 ² EXPP, EXMP ˆ¹ l ek w ˆ¹, l ek ². p ² w «. l ² ƒ Object Speed l. l - 3, 4 BIT : 00 lww ORPtµ ORPtµ o s ltw OTPtµ OTPtµ o s o w szl s tµ j~ jj~ l - 3, 4 BIT : 01 lww ORPtµ ORPtµ OTPtµ OTPtµ o s ltw o s w szl o s tµ j~ jj~ l - 3, 4 BIT : 10 20

27 Hardware Chip User Manual Rev lww ORPtµ ORPtµ ORPtµ ORPtµ OTPtµ OTPtµ OTPtµ OTPtµ o s ltw o s w szl o s tµ j~ jj~ l - 3, 4 BIT : 11 lww ltw ORPtµ ORPtµ ORPtµ ORPtµ OTPtµ OTPtµ OTPtµ OTPtµ ORPtµ ORPtµ ORPtµ ORPtµ OTPtµ OTPtµ OTPtµ OTPtµ o s o s w szl o s tµ j~ jj~, l wm l Speed Object Speedy Ž. MP Preset Pulse Drive EXPP, EXMP ˆ¹ Edge ˆ¹ l r ƒ ² p«l ¹ Preset Pulse Drive. EXPP, EXMP ˆ¹ Edge ˆ¹ l r ƒ ² p«overridep. EXPP ˆ¹ Active Level r (+)w, EXMP ˆ¹ Active Level r (-) w m. lww ORPtµ o s ltw OTPtµ o s w szl o s ƒ ƒ tµ j~ jj~, m Edge ˆ¹ l r l ² l ˆ¹ tˆ ¹ Overridep. p d ² p 10 p. 21

28 3. Hardware Chip User Manual Rev. 4.0 MP Continuous Drive EXPP, EXMP ˆ¹ Active Level Ž ² p l, ¹ Continuous Drive. EXPP ˆ¹ Active Level Ž m 가감속모드설정기능 q p (+)w, EXMP ˆ¹ Active Level Ž (-)w ³tƒ sd ˆ ˆ ¹ m S-curve m± sd. SW1 ˆ S ƒ. SW1 p» m ƒ r Full-S ± m± ƒƒ. SW1 p (Object-Std)/2 y m ƒ ƒ. SW1 p 0x7FF m» dk { ƒ 0x02m r ³tƒ(S-curve) sd ƒ dk {p. S-curve ˆ ˆ /s Rate-1 m ƒ. S-curve ƒƒ ˆ Rate-1 xº ºƒ y. S-curve ˆ ˆ. T unit Rate 1 Data 16 = F clk S-curve ˆ ˆ. T up / down : ˆ ƒ (sec) ( 목표속도 시작속도 ) = T : ˆ (sec) unit 22

29 Hardware Chip User Manual Rev š ŒŒ ˆ ˆ O šp p² {œ V ž {œ V ž OšŒŠP y q p 3.9. Profile ³tƒ sd ˆ ˆ p ¹ m S-curve m± sd. dk { ƒ 0x03m ƒ r ³tƒ(S-curve) sd ƒ dk {p. S-curve ˆ ˆ /s Rate-1 m ƒ ƒ ˆ ˆ /s Rate-2 m ƒ. SW1 ˆ S SW2 ˆ S ƒ. SW1, SW2 p» m ƒ r Full-S ± m± ƒƒ. SW1, SW2 p (Obj-Std)/2 y m ƒ ƒ. dk { ˆ Rate-1 ¹ Rate-2 xº ºƒ y. S-curve ˆ ƒ ˆ T unit ( up) T up Tunit( up ) Rate 1 Data 16 F = : ˆ ƒ (sec) clk ( 목표속도 시작속도 ) = : ˆ (sec) S-curve ˆ ƒ ˆ T unit ( down ) T down Tunit( down ) Rate 2 Data 16 F = : ˆ ƒ (sec) clk ( 목표속도 시작속도 ) = : ˆ (sec) 23

30 3. Hardware Chip User Manual Rev. 4.0 š ŒŒ ˆ ˆ O šp p² {œ { ž OšŒŠP p Profile ƒ sd ˆ ˆ ¹ m ƒ m± sd. dk { ƒ 0x00 m ƒ r ƒ sd ƒ dk {p. ƒ ˆ ˆ /s Rate-1/ Rate-2/ Rate-3 m ƒ. dk { ˆ Rate-1/ Rate-2/ Rate-3 xº ºƒ y. ƒ ˆ ƒ ˆ. T unit Rate n Data 8 F = : ˆ ƒ (sec) (n=1, 2, 3) clk ƒ ˆ ˆ. T up / down ( 목표속도 시작속도 ) = T : ˆ (sec) unit š ŒŒ ˆ ˆ O šp p² {œ V ž { œ V ž OšŒŠP v Profile 24

31 Hardware Chip User Manual Rev y p ƒ sd ˆ ˆ p ¹ m ƒ m± sd. dk { ƒ 0x01m ƒ r ƒ sd ƒ dk {p. ƒ ˆ ˆ /s Rate-1 m ƒ ƒ ˆ ˆ /s Rate-2 m ƒ. dk { ˆ Rate-1 ¹ Rate-2 xº ºƒ y. ƒ ˆ ƒ ˆ T unit( up ) T up Tunit( up ) Rate 1 Data 8 F = : ˆ ƒ (sec) clk ( 목표속도 시작속 ) = 도 : ˆ (sec) ƒ ˆ ƒ ˆ unit( down ) Rate 2 Data 8 F T = : ˆ ƒ (sec) T down = Tunit( down ) clk ( 목표속도 시작속도 ) : ˆ (sec) š ŒŒ ˆ ˆ O šp p² {œ { ž OšŒŠP v Profile 25

32 3. Hardware Chip User Manual Rev 감속개시포인트검출방식선택기능 Preset Pulse Drive ˆ ˆ ˆ ³ wˆ. wˆ( y ) - ² ek CAMC-FS m ³ p» ˆ. ² wˆ - ¹ l ² ƒ ² ² ƒ ² ˆ z ˆ 서보모터인터페이스기능 CAMC-FS ƒ ƒy s ˆ¹p ƒy s ³. INP( ³ ) - v m ² l «ƒy s dk w z rl ² l dw ² l Ÿ p ³Ÿ r, Ÿ (zero) m s p. ekƒ p m s rl ² y, rl ² p k ³Ÿ ˆ k (zero) e s Ž. et ƒy s d k w s ˆ Inposition( n)ˆ¹p l. ˆ¹p IN P l ˆ¹ lˆ¹ nˆ¹m. ALM( ) - ƒy s dk w alarm ˆ¹p l. ˆ¹ On(active ˆ¹ l) r ² d k { 다축동기맞춤기능 CAMC-FS l ˆ q mƒ SYN l ˆ¹. l ˆ¹ Low level l Ž dk { ˆ command ˆ ² l Ž, BUSY ˆ¹p High levelm l. ekƒ l ² l ˆ, SYN l Lowm dk { ˆ commandp ˆ» SYN l High ˆ¹p l r. CAMC-FS2.1 w ƒ SYN l ˆ¹ zp software m ƒ. e kƒ, l CAMC-FSm ˆ Ž d ¹ ˆ d ¹. 26

33 Hardware Chip User Manual Rev 범용입출력기능 software ƒ read/write x l ˆ¹ 4 Ž. x l ˆ¹ m ˆ¹ dk { ƒ ˆ¹m, dk { ƒ ˆ¹ l m. g z z Clear lˆ¹m 기계계외부입력제어기능 mz ƒ l ˆ¹p ep. ˆ¹d active level active high(0=low, 1=high) active low(0=high, 1=low)m ƒ r, ƒ l ˆ¹ ³ ªm 1~255w T ~ T T : ªm) ƒ. 255, clk ( clk clk ± Emergency stop Limit ˆ¹(±ELM) (+)/ (-) w m limit ˆ¹ (+ELM, -ELM) over run w. ± Slowdown stop Limit ˆ¹(±SLM) (+)/ (-) w m limit ˆ¹(+SLM, -SLM) over run w. m l ˆ¹ ±ELM l ˆ¹m z p. Emergency Stop(ESTOP) p ƒ l ˆ¹. Slow down Stop(SSTOP) p ƒ l ˆ¹ 펄스출력방식전환기능 s dk w l q ² l wˆ ƒ m 8 o ² l wˆ. ² o. 1 ² wˆ 27

34 3. Hardware Chip User Manual Rev. 4.0 ª«ª«ªª «tµ «tµ d e 1 ª«ª«ªª «tµ «tµ ª e d 2 ª«ª«ª ªª «tµ «tµ d e 3 ª«ª«ª ªª «tµ «tµ ª d e 4 28

35 Hardware Chip User Manual Rev ² wˆ d e 1 ª«ª««tµ ª ªª «tµ ª d e 2 ª«ª««tµ ªª «tµ d e 3 ª«ª««tµ ª ªª «tµ ª d e 내부위치링카운터 (Internal Ring Counter) 관리기능 CAMC-FS ƒ l ² p 32-bit up/down counter m p Ž. z l ² CW(+) w e up-count(² l ep +1 ), CCW(-) w l² down-count(² l ep 1 ). ekƒ ² l n» y 29

36 3. Hardware Chip User Manual Rev. 4.0 m m ¹ p Ž. z p r, M_DATA P_DATAp ƒ 32-bit l., M_DATA < P_DATA ƒp Ž. z p k ƒ x ƒ t m. INTERNAL COUNTER M_DATAp 10, INTERNAL COUNTER P_DATAp 10 m ƒ z. (CW w ) (CCWw ) s p ¹ p. vª ² p M_DATA P_DATA ƒ r vª» z m ªp um ˆ ƒ ¹ yp z y m Ž 외부위치링카운터 (External Ring Counter) 관리기능 CAMC-FS z ² mz feedbackv up/downˆ¹,g 2 ˆ¹p 32-bit up/down counter. z ƒ feedback ² p ¹ yp Žl r, z m p. z l (2 ˆ¹ˆ w( )) m x. z p r, M_DATA P_DATAp ƒ 32-bit l., M_DATA < P_DATA ƒp Ž. z p k ƒ x ƒ t m. EXTERNAL COUNTER M_DATAp 10, EXTERNAL COUNTER P_DATAp 10 m ƒ z. (CW w ) (CCWw ) s p ¹ p. vª ² p M_DATA P_DATA ƒ r vª» z m ªp um ˆ ƒ ¹ yp z y m Ž 내부위치카운터비교기능 z p 32-bit l r, z. z p z k zpr m x. 2 y p r, p ˆ º. 30

37 Hardware Chip User Manual Rev *32-bit 2 y x p 10 m xº «r. 2 y : 0x , 0xFFFFFFF, 0x , 0x ,, 0x7FFFFFFF 10 : -2,147,483,647, -1, 0, 1,, 2,147,483, 외부위치카운터비교기능 z p 32-bit l r, z. z p z k zpr software m x. 2 y p r, p ˆ º 내부 / 외부위치 Scale 카운트기능 Scale k z/ z p ² l r scale w ª p«r z/ z 1. e Scale 8-bit r z/ z m. z Scale p 8m ƒ CW ² l ˆ. i w i «3.21. o Scale n mr 31

38 3. Hardware Chip User Manual Rev 외부위치카운터 Clear 기능 x l ˆ¹ p ƒ z p clear ˆ¹m. z clear ƒ x l ˆ¹ High Level l r z p Clear. z Clear ˆ¹ ƒ ƒ z ƒ rl m ƒ. [ z ƒ ] X j Œˆ ƒ WWaj Œˆ Ž WXav Œ{ Œj Œˆ XWa ˆ¹ l ˆ j Œˆ j Œˆ ˆ¹ ƒ WWWXa x lx WWXWa x ly WXWWa x lz XWWWa x l[ XXa ˆ¹ l» j Œˆ * Clear ƒ ƒ One Time Clear(01) Clear ˆ¹ High l r z Zero ƒ 00m x. ˆ z p Clear ƒ ˆ 01m ƒ» Ž. ˆ¹ l ˆ Clear(10) Clear ˆ¹ High l k ƒ m um Clear ˆ¹ High l ep z Zero. ˆ¹ l» Clear(11) Clear ˆ¹ High l r z Zero. ˆ z p ƒ Clear ƒ 11 m ƒ Ž 외부위치카운터방향반전기능 l ˆ¹p z w v ˆ«. ƒ m x 편차량산출기능 m ( z ) ¹ ( z ) ³Ÿ(deviation). ³Ÿk [ z z ] r 15-bit m « ³Ÿk z¹ ³Ÿk z z Ÿ 32

39 Hardware Chip User Manual Rev 속도데이터 / 편차량데이터모니터기능 ƒy dk {p y mƒ, ³Ÿk p Sign bit(z¹ ) s (13-bit) l ˆ¹p s. MONI l ˆ¹m s p, lˆ¹ z¹ s m ƒ. MONI = Low (³Ÿk s ) Sign ˆ¹ Low MD12~MD0 ³Ÿk (16-bit) 13-bit MONI = High( s ) Sign ˆ¹ w (Low : w, High : w ) MD12~MD0 ¹ (16-bit) 13-bit 인터럽트발생기능 CPU l p Žp l vƒ 32 l l p g z pd 32 l p ª. g l l Active Level x. ) Active Level High 설정데이터에러판정기능 ƒ p ˆ. ƒ dk {p ˆ z l vƒ r, dk { r dk { n l vƒ ƒ dk {p ˆ vm 탈조 (Off-Range) 검출기능 z z Ÿ ¹ s m ˆ Ÿ. CAMC-FS l Ÿ ƒ y ª r «m dk {p /. e ƒ p «k. 8- bit(1 ~ 255) r 0 «Ž 실거리이동연산기능 ² dk {p ˆ pp l² m Ž z l ˆ¹ p. ˆ p k. ˆ p ² dk {p ˆ s pp º. l l ² z Ÿ ª p ep º Ž um ˆ. 33

40 3. Hardware Chip User Manual Rev PWM 출력기능 CAMC-FS ¹ m PWM ˆ¹p l. l ±¹ PWM l (0x00~0x06) ek. PWM l ep PWM ±¹ s. F = LSHIFT(F k, 16-R ) [Hz] pwm cl pwm T = LSHIFT(R, R )*T [ns] high v pwm clk F pwm : PWM ˆ¹ ± T high : PWM ˆ¹ Highm ˆ R pwm : PWM l F clk : ªl ± R v : ¹ LSH IFT (A,B) : Ap Bp«left shift, A/2 B 외부센서필터대역폭 ( Bandwidth) 설정기능 z ƒ ˆ¹d ³ x. ƒ ³ ƒ l (BW) ek ƒ ˆ¹ ºˆ¹ ˆ. BW l 0~ 255 ƒ r, 0 ƒ ˆ¹p Ž r, r Tclk*BW ˆ º ƒ ˆ¹ l r ep. BW l RESET» y 0x 스크립트(Scri pt ) 기능 CAMC-FS ƒ v ƒ ˆ e( x vƒ e) ˆ rl p 32- bit l 16 Ž. ªp l x vƒ r rl r ªp k. e x r x p AND( x ˆ rl ˆ ), p OR( x k rl ˆ ), p XOR( x p e rl ˆ ) x. ªp ƒ 16 y m 4 m ƒ r r 12 Ÿ p. ªp r dk { ˆ m ˆ. ƒ ˆ¹» vm w m dk {p ˆ, dk { x ˆ dk { ˆ rl ˆ¹ -1 dk { p ˆ, dk {» ˆ p dk { rl l ŽŽ ª p m dk { ˆ. 34

41 Hardware Chip User Manual Rev ªp ªp ˆ ˆ ˆ¹ TX dk { dk { d n m 갈무리 (Caption) 기능 x rl ˆ ªp p, e l p. tp k. tp l x, rl ƒ 32-bit l 12 e p l 12. tp rld l d rldp r, rl ˆ» l Ÿ m. ekƒ CPUp tp l p y m p Ž. tpƒ tpˆ ˆ ˆ¹ TX dk { dk { n m 35

42 4. Address Map Hardware Chip User Manual Rev Address Map CAMC-FS address map. z 8-bit l 4 ƒ, ƒ rl ˆ p r z l 4 w² 32-bit p 8-bitŽ(16-bit data bus access sd 16-bit) z p y. A2 A1 A0 8/16SEL CS* RD* WR* Operation Data1 write (2 31 ~2 24 bit ) 8bit access Data2 write (2 23 ~2 16 bit ) Data3 write (2 15 ~2 8 bit ) Data4 write (2 7 ~2 0 bit ) Command write Ž Ž Ž Data1 read (2 31 ~2 24 bit ) Data2 read (2 23 ~2 16 bit ) Data3 read (2 15 ~2 8 bit ) Data4 read (2 7 ~2 0 bit ) Ž Ž Ž Ž Data1,Data2 write (2 31 ~2 16 bit ) Ž bit access Data1,Data2 write (2 15 ~2 0 bit ) Ž Ž Ž Ž Command write Data1,Data2 read (2 31 ~2 16 bit ) Ž 36

43 Hardware Chip User Manual Rev Address Map A2 A1 A0 8/16SEL CS* RD* WR* Operation Data1,Data2 read (2 31 ~2 16 bit ) Ž Ž Ž Ž Ž 37

44 5. Port ƒr Hardware Chip User Manual Rev Port 설명 DATA1~DATA4 port ˆ rl p write. 32-bit r, rl ˆ e m md. Read rl ˆ» DATA1~DATA4 port. p 8-bit g 16-bitŽ r p Ž DATA1 WRITE PORT ƒ DATA 2 31 ~ 2 24 Bit Data p. D BIT D BIT D BIT D BIT D BIT D BIT D BIT D BIT 5.2. DATA2 WRITE PORT ƒ DATA 2 23 ~ 2 16 Bit Datap. D BIT D BIT D BIT D BIT D BIT D BIT D BIT D BIT 38

45 Hardware Chip User Manual Rev Port ƒr 5.3. DATA3 WRITE PORT ƒ DATA 2 15 ~ 2 8 Bit Datap. D BIT D BIT D BIT D BIT D BIT D BIT D1 2 9 BIT D0 2 8 BIT 5.4. DATA4 WRITE PORT ƒ DATA 2 7 ~ 2 0 Bit Datap. D7 2 7 BIT D6 2 6 BIT D5 2 5 BIT D4 2 4 BIT D3 2 3 BIT D2 2 2 BIT D1 2 1 BIT D0 2 0 BIT 5.5. COMMAND WRITE PORT COMMANDp. D7 2 7 BIT D6 2 6 BIT D5 2 5 BIT D4 2 4 BIT D3 2 3 BIT D2 2 2 BIT D1 2 1 BIT D0 2 0 BIT 39

46 5. Port ƒr Hardware Chip User Manual Rev DATA1 READ PORT ƒ DATA 2 31 ~ 2 24 Bit Datap. D BIT D BIT D BIT D BIT D BIT D BIT D BIT D BIT 5.7. DATA2 READ PORT ƒ DATA 2 23 ~ 2 16 Bit Datap. D BIT D BIT D BIT D BIT D BIT D BIT D BIT D BIT 5.8. DATA3 READ PORT 15 8 ƒ DATA 2 ~ 2 Bit Datap. D BIT D BIT D BIT D BIT D BIT D BIT D1 2 9 BIT D0 2 8 BIT 40

47 Hardware Chip User Manual Rev Port ƒr 5.9. DATA4 READ PORT ƒ DATA 2 7 ~ 2 0 Bit Datap. D7 2 7 BIT 6 D6 2 BIT D5 2 5 BIT D4 2 4 BIT D3 2 3 BIT D2 2 2 BIT D1 2 1 BIT D0 2 0 BIT 41

48 6. COMMAND ƒr Hardware Chip User Manual Rev COMMAND 설명 COMMAND 일람표 CAMC-FS l ƒ v +/- w DRIVE d COMMAN D. DRIVE COMMANDp sd COMMAND DRIVE (BUSY = H), ¹ DRIVE (BUSY = L) ˆ ˆ DATA COMMAND ekƒ» m ˆ Ž um. ² l dk { l l,, PM(Pulse enerator Module) l l 2 wªm z. ekƒ o p 2 ± m. PM-1 n l l d y m dk {p ˆ e l d, PM-1 UP- DATE n l l PM-1 n l wx m ƒ» PM Register Change Commandp ˆ PM-1 UP-DATE n l p ² l dk {p. l ±», dk { m l ƒ x Ž dk { ˆ rlp ± m s p. CAMC-FS ˆ rl PM-1 n, PM-1 UP-DATE n, º n, ªp / tp n, BUS-1 n, BUS-2 n m z. PM-1 n PM-1 UP-DATE n COMMAND ² l l ƒ l rl d. ªp / tp n COMMAND ªp tp, rl, d ƒ rld. BUS-1 n COMMAND z/ z l ƒ, z ƒ ƒ v PM Register Change rld ³. BUS-2 n COMM AND z ƒ l rld. 42

49 Hardware Chip User Manual Rev COMMAND ƒr ƒ COMM CAMC-FS READ COMMAND AND k p ˆ. CODE(HEX) p (PM- 1 ROUP l READ) R DEFAULT 00 PM-1 RANE READ 16 0xFFFF 01 PM-1 START/STOP SPEED DATA READ 16 0x PM-1 OBJECT SPEED DATA READ 16 0x PM-1 RATE-1 DATA READ 16 0XFFFF 04 PM-1 RATE-2 DATA READ 16 0XFFFF 05 PM-1 RATE-3 DATA READ 16 0XFFFF 06 PM-1 RATE CHANE POINT 1-2 READ 16 0XFFFF 07 PM-1 RATE CHANE POINT 2 3 READ 16 0XFFFF 08 PM-1 SW-1 DATA READ 15 0X7FFF 09 PM-1 SW-2 DATA READ 15 0X7FFF l ƒ DATA READ(0~6) 0A PM-1 PWM 3 0X00 0B PM-1 SLOW DOWN / REAR PULSE READ 32 0X C PM-1 ¹ SPEED DATA READ 16 0x0000 0D PM-1 ¹ SPEED DATA READ 16 0x0000 0E PM-1 DRIVE PULSE COUNTER READ 32 0X F PM-1 PRESET PULSE DATA READ 32 0X CODE(HEX) p (PM-1 UP-DATE ROUPl READ) R DEFAULT 10 PM-1 UP-DATE RANE READ 16 0xFFFF 11 PM-1 UP-DATE START/STOP SPEED DATA READ 16 0x PM-1 UP-DATE OBJECT SPEED DATA READ 16 0x PM-1 UP-DATE RATE-1 DATA READ 16 0XFFFF 14 PM-1 UP-DATE RATE-2 DATA READ 16 0XFFFF 15 PM-1 UP-DATE RATE-3 DATA READ 16 0XFFFF 16 PM-1 UP-DATE RATE CHANE POINT 1-2 READ 16 0XFFFF 17 PM-1 UP-DATE RATE CHANE POINT 2 3 READ 16 0XFFFF 18 PM-1 UP-DATE SW-1 DATA READ 15 0X7FFF 19 PM-1 UP-DATE SW-2 DATA READ 15 0X7FFF 1A NO OPERATION 1B PM-1 UP-DATE SLOW DOWN / REAR PULSE READ 32 0X

50 6. COMMAND ƒr Hardware Chip User Manual Rev. 4.0 CODE(HEX) p (PM-1 UP-DATE ROUPl READ) R DEFAULT 1C PM-1 ¹ SPEED DATA READ 16 0x0000 1D PM-1 ¹ SPEED DATA READ 16 0x0000 1E PM-1 DRIVE PULSE COUNTER READ 32 0X F PM-1 PRESET PULSE DATA READ 32 0X CODE(HEX) p (PM-2 ROUP l READ) R DEFULT 20~2C NO OPERATION 2D dk { ƒ 2bit 0~1bit : DATA READ : ˆ p (0 : Ž, 1: ) 00 : ƒ sd 01 : ƒ sd 10 : S- ƒ sd 11 : S- ƒ sd 3 0x0 2E MP OPERATION SETTIN DATA WRITE 6bit 5bit 3~4bit : 00: 01: 1 w 10: 2 w 11: 4 w ( 0: RESET, 1 : SET) 2bit : 0 : ƒ w + Preset pulse drive 1 : ƒ w 1bit : 0 : z 2 ² w l 1 : ƒ w l 0bit : z ˆ¹ Continuous drive (0 : RESET, 1 : SET) : z ˆ¹ : z 2 ² (0 : RESET, 1 : SET) 7 0x00 2F MP PRESET PULSE DATA READ 32 0x CODE(HEX) p ( º ROUP l READ ) R DEFULT 30~35 NO OPERATION 44

51 Hardware Chip User Manual Rev COMMAND ƒr CODE(HEX) p ( º ROUP l READ ) R DEFULT 36 Soft limit ƒ READ 2 bit : Limit ƒ (0 : Internal count, 1 : External count) 1 bit : Soft limit ˆ dk {(0:, 1: ) 0 bit : Soft limit Enable/Disable(0 : Enabel, 1 : Disable) 3 0x Soft limit l ƒ READ 32 0x Soft limit l ƒ READ 32 0x7FFFFFFF 39 Trigger mode ƒ READ 31~16 bit : Trigger active level lˆ ƒ (Trigger º : 0x0000 m ƒ ) ˆ = main clock x (Decim 15~ 2 bit : Don t care al value of 31~16bit) 1 bit : Trigger count (0 : Internal, 1 : External) 0 bit : Trigger mode(0 : sd, 1 : sd) 32 0x A Trigger ƒ READ 32 0x B INTERNAL COUNTER M_DATA READ 32 0x C EXTERNAL COUNTER M_DATA READ 32 0x D~3F NO OPERATION CODE(HEX) p ( p ROUPl READ) R DEFULT 40 ªp ƒ l bit : 0 : w ˆ, 1 : ˆ 30~26bit : Don t care READ 25~24bit : x 00 : p (1w x p ) 01 : OR 10 : AND 11 : XOR 23~16bit : 2w x ƒ 15~ 8 bit : 1 w x ƒ 7~ 0 bit : x» ˆ COMMAN * x ƒ x ªp ƒ D 32 0x l -2 READ 32 0x

52 6. COMMAND ƒr Hardware Chip User Manual Rev. 4.0 CODE(HEX) p ( p ROUPl READ) R DEFULT ªp ƒ l -1 bit ªp ƒ l -3 READ ªp ƒ l -1 bit ªp ƒ l -Queue READ 31 bit : 0 : w ˆ, 1 : ˆ 30 bit : ˆ ˆ Interrupt vƒ(0:disable, 1:Enable) 29~26bit : Don t care 25~24bit : x 00 : p (1w x p ) 01 : OR 10 : AND 11 : XOR 23~16bit : 2w x ƒ 15~ 8 bit : 1 w x ƒ 7~ 0 bit : x» ˆ COMMAND ªp l -1 READ 32 0x x x ªp l -2 READ 32 0x ªp l -3 READ 32 0x ªp l -Queue READ 32 0x NO OPERATION ªp ƒ Queue R ªp Queue READ 49 EAD 4 0x0 4A 4 0x0 ªp Queue Full/Empty Flag READ 4B 3 bit : ªp ƒ l _4 Full Flag 2 bit : ªp ƒ l _4 Empty Flag 1 bit : ªp l _4 Full Flag 0 bit : ªp l _4 Em ªp Queue size ƒ (0~13) READ 15~ 12 bit : ƒ l -Queue full size pty Flag 4 0x5 4C 16 0xD0D0 11~ 8 bit : ƒ l -Queue empty size 7~ 4 bit : l -Queue full size 3~ 0 bit : l -Queue empty size 4D ªp Queue status READ 11 ~ 8 bit : ªp ƒ Queue 12 0x005 46

53 Hardware Chip User Manual Rev COMMAND ƒr CODE(HEX) p ( p ROUPl READ) R DEFULT 7 ~ 4 bit : ªp Queue 3 bit : ªp ƒ l _4 Full Flag 2 bit : ªp ƒ l _4 Empty Flag 1 bit : ªp l _4 Full Flag 0 bit : ªp l _4 Em 4E~4F NO OPERATION pty Flag CO DE(HEX) p ( tp ROUPl READ) R DEFAULT tp ƒ l -1 READ tp ƒ l -Queue READ 31 bit : 0 : w ˆ, 1 : ˆ 30 bit : ˆ ˆ Interrupt v ƒ(0:disable, 1:Enable) ~26bit : Don t care 25~24bit : x 00 : p (1w x p ) 01 : OR 10 : AND 11 : XOR 23~16bit : 2w x ƒ 15~ 8 bit : 1 w x ƒ 7~ 0 bit : x» ˆ COMMAND tp ƒ l -2 READ tp ƒ l -1 bit tp ƒ l -3 READ tp ƒ l -1 bit tp ƒ l -Queue READ 31 bit : 0 : w ˆ, 1 : ˆ 30 bit : ˆ ˆ Interrupt vƒ(0:disable, 1:Enable) 29~26bit : Don t care 25~24bit : x 00 : p (1w x p ) 01 : OR 32 0x x x x

54 6. COMMAND ƒr Hardware Chip User Manual Rev. 4.0 CODE(HEX) p ( tp ROUPl READ) R DEFAULT 10 : AND 11 : XOR 23~16bit : 2w x ƒ 15~ 8 bit : 1 w x ƒ 7~ 0 bit : x» ˆ CO MMAND 54 tp l -1 READ 32 0x tp l -2 READ 32 0x tp l -3 READ 32 0x tp l -Queue READ 32 0x NO OPERATION tp ƒ Queue RE tp Queue RE 59 AD 4 0x0 5A AD 4 0x0 tp Queue Full/Empty Flag READ 5B 6 bit : tp l _3 data update Flag 5 bit : tp l _2 data u 4 bit : tp l _1 data u 3 bit : tp ƒ l _4 Full Flag 2 bit : tp ƒ l _4 Em 1 bit : tp l _4 F 0 bit : tp l _4 E pty Flag ull Flag pdate Flag pdate Flag mpty Flag 7 0x05 5C 5D 5E~5F tp Queue size ƒ (0~13) READ 15~ 12 bit : ƒ l -Queue fu 11~ 8 bit : ƒ l -Queue em 7~ 4 bit : l 3~ 0 bit : l -Queu Queue status READ ll size pty size -Queue full size e empty size 11 ~ 8 bit : tp ƒ Queue 7 3 ~ 4 bit : tp Queue bit : tp ƒ l _4 Full Flag 2 bit : tp ƒ l _4 Empty Flag 1 bit : tp l _4 Full Flag 0 bit : tp NO OPERATION l _4 Empty Flag 16 0xD0D0 12 0x005 48

55 Hardware Chip User Manual Rev COMMAND ƒr CODE(HEX) p (BUS-1 ROUPl READ) R DEFAULT 60 INTERNAL COUNTER DATA READ(Signed) 32 0x INTERNAL COUNTER COMPARATE DATA READ (Signed) 32 0x INTERNAL COUNTER PRE-SCALE DATA READ 8 0x00 63 INTERNAL COUNTER P-DA TA READ 32 0x7FFFFFFF 64 EXTERNAL COUNTER DATA READ(Signed) 32 0x EXTERNAL COUNTER COMPARATE DATA READ (Signed) 32 0x EXTERNAL COUNTER PRE-SCALE DATA READ 8 0x00 67 EXTERNAL COUNTER P-DATA READ 32 0x7FFFFFFF 68 EXTERNAL SPEED DATA READ 32 0x EXTER NAL SPEED COMPARATE DATA READ 32 0x z ƒ ³ ƒ 6A DATA READ 8 0x05 6B OFF-RANE DATA READ 8 0x00 6C DEVIATION DATA READ 15 bit : ³Ÿk z¹ 14 ~ 0 bit : ³Ÿk 16 0x0000 6D PM REISTER CHANE DATA READ 1 0x0 6E~6F NO OPERATION CODE(HEX) p (BUS-2 ROUPl READ) R DEFAULT ƒ DATA READ 12bit: S profile ˆ z (0 : Ž, 1 : ) 70 11bit: Search drive source filter z( 0 : Ž, 1 : ) 10bit: Sync z(0 : Ž, 1: ) 9 bit : Limit (0 : Ž, 1: ) 8 bit : Inposition º sd(0: Ž, 1: ) 7 bit : «/ ƒ (0 :, 1 : ) 13 0x0C3E 6 bit : ƒ (0 : ƒ, 1 : d ) 5 bit : Limit sd(0 : Ž, 1 : ) 4 bit : Limit sd(0 : Ž, 1 : ) 3 bit : estop, sstop enable/disable(0 : disable, 1 : enable) 49

56 6. COMMAND ƒr Hardware Chip User Manual Rev. 4.0 CODE(HEX) p (BUS-2 ROUPl READ) R DEFAULT 71 2 bit : Don t care 1 bit : Alarm Stop sd(0 : Ž, 1 : ) 0 bit : Inposition (0 : Ž, 1 : ) MODE1 DATA READ 7 bit : ˆ ³ wˆ (0:, 1 : r ) 6~4 bit : ² l wˆ ƒ (* x 3~0 bit : ˆ¹ ƒ ƒ (* x { ) MODE2 DATA READ 10 bit: Trigger lˆ¹ active level ƒ 9 bit: Interrupt active level ƒ 8 bit: MARK ˆ¹ active level ƒ { ) 7~6 bit : Encoder signal count mode(ecup, ECDN signal) 00 : ˆ¹(ECU P : up l, ECDN : down l) 01 : 90 difference phase, 1 times multiplied 8 0x : 90 difference phase, 2 times multiplied 11 0x : 90 difference phase, 4 times multiplied 5 bit : INP ˆ¹ ACTIVE LEVE 4 bit : ALM ˆ¹ ACTIVE LEVEL ƒ L ƒ 3 bit : -SLM ˆ¹ ACTIVE LEVEL ƒ 2 bit : +SLM ˆ¹ ACTIVE LEVEL ƒ 1 bit : -ELM ˆ¹ ACTIVE LEVEL ƒ 0 bit : +ELM ˆ¹ ACTIVE LEVEL ƒ UNIVERSAL IN READ 73 10~8 bit : Universal output bit operation 0xx : «UOUT m l 100 : NOT (¹ UOUT v ) 101 : AND ( «¹ UOUT and 110 : OR ( «¹ UOUT or l) l) 111 : XOR ( «¹ UOUT differen ce check) 7 ~ 4 bit : Universal Input 3 ~ 0 bit : Universal output 11 0X END STATUS DATA READ 14 bit : Limit(P ELM, NELM, PSLM, PELM, soft) n 15 0x

57 Hardware Chip User Manual Rev COMMAND ƒr CODE(HEX) p (BUS-2 ROUPl READ) R DEFAULT bit : Limit n 12 bit : Sensor positioning drive n 11 bit : Preset pulse drive n 10 bit : ˆ¹ n(signal search-1/2 d 9 bit : n 8 bit : «l n 7 bit : ƒ l n 6 bit : ALARM ˆ¹ l n 5 bit : rl n 4 bit : rl n 3 bit : ˆ¹ l n 2 bit : ˆ¹ l n 1 bit : Limit(PELM, NELM, soft) n 0 bit : Limit(PSLM, NSLM, soft) n MECHANICAL SINAL DATA READ 12 bit : ESTOP ˆ¹ l Level 11 bit : SSTOP ˆ¹ l Level 10 bit : MARK# ˆ¹ l 9 bit : EXPP ˆ¹ l Level 8 bit : EXMP ˆ¹ l Level Level 7 bit : UP ˆ¹ l Level ( A ˆ¹ ) 6 bit : DOWN ˆ¹ l Level ( B ˆ¹ ) 5 bit : INPOSITION ˆ¹ active 4 bit : ALARM ˆ¹ active 3 bit : -Limit ˆ¹ active 2 bit : + Limit ˆ¹ active 1 bit : - Limit ˆ¹ active 0 bit : + Limit ˆ¹ active DRIVE STATE DATA READ rive n) 8 bit : dk { w ˆ¹(0:CW, 1:CCW) 7 bit : EC( z < z ) 6 bit : ECL( z > z ) 5 bit : IC( z < z ) 4 bit : ICL( z > z )

58 6. COMMAND ƒr Hardware Chip User Manual Rev. 4.0 CODE(HEX) p (BUS-2 ROUPl READ) R DEFAULT 3 bit : UP ( ) 2 bit : CONST ( d ) 1 bit : DOWN ( ) 0 bit : BUSY ( dk { ) EXTERNAL COUNTER ƒ DATA READ 8 bit : External count clear flag(read only) 7 bit : 0 : Not reverse count, 1: Reverse count 6 bit : Don t care 5 ~ 4 bit : 00 : CLEAR REQUEST RESET 01 : ONE TIME CLEAR REQUEST SET : FULL TIME CLEAR REQUEST SET 11 : EXTERNAL COUNTER CLEAR SET 3 ~ 0 bit : CLEAR lˆ¹ ƒ 0000 : IN : IN : IN : IN3 Others : Don t care Interrupt FLA READ (0 : Interrupt inactivated, 1 : Interrupt activated) 31 bit : Selectable Interrupt source3( FE 31~24bit) 30 bit : Selectable Interrupt source2( FE 23~16bit) 29 bit : Selectable Interrupt source1( FE 15~8bit) 9 0x bit : Selectable Interrupt source0( FE 7~0bit) 27 bit : Emergency limit ˆ¹ lˆ 26 bit : Slow down limit ˆ¹ lˆ 25 bit : queue rl ˆ(30 bit 1 e) 32 0x bit : ªp queue rl ˆ(30 bit 1 e) 23 bit : M-data count clear 22 bit : ¹ = ¹ 21 bit : ¹ = RCP12 20 bit : ¹ = RCP23 19 b it : MODE1 register ƒ ˆ¹ ˆ 18 bit : 52

59 Hardware Chip User Manual Rev COMMAND ƒr CODE(HEX) p (BUS-2 ROUPl READ) R DEFAULT 17 bit : d 16 bit : 15 bit : Interrupt command ƒƒ 14 bit : -3 command ˆ e 13 bit : -2 command ˆ e 12 bit : -1 command ˆ e 11 bit : ªp -3 command ˆ e 10 bit : ªp -2 command ˆ e 9 bit : ªp -1 command ˆ e 8 bit : ƒ queue full e 7 bit : ªp data queue empty e 6 bit : External counter < External comparator e 5 bit : External counter = External comparator e 4 bit : External counter > External comparator e 3 bit : Internal counter < Internal comparator e 2 bit : Internal counter = Internal comparator e 1 bit : Internal counter > Internal comparator e 0 bit : dk { n Interrupt MASK READ (0 : Interrupt Disable, 1 : Enable) 31 bit : Selectable Interrupt source3( FE 31~24bit) 30 bit : Selectable Interrupt source2( FE 23~16bit) 29 bit : Selectable Interrupt source1( FE 15~8bit) 7A 28 bit : Selectable Interrupt source0( FE 7~0bit) 27 bit : Emergency limit ˆ¹ lˆ 26 bit : Slow down limit ˆ¹ lˆ 25 bit : queue rl ˆ(30 bit 1 e) 24 bit : ªp queue rl ˆ(30 bit 1 e) 23 bit : P-data count clear 22 bit : ¹ = ¹ 21 bit : ¹ = RCP12 20 bit : ¹ = RCP23 19 bit : MODE1 register ƒ ˆ¹ ˆ 18 bit : 32 0x

60 6. COMMAND ƒr Hardware Chip User Manual Rev. 4.0 CODE(HEX) p (BUS-2 ROUPl READ) R DEFAULT 17 bit : d 16 bit : 15 bit : Don t care 14 bit : -3 command ˆ e 13 bit : -2 command ˆ e 12 bit : -1 command ˆ e 11 bit : ªp -3 command ˆ e 10 bit : ªp -2 command ˆ e 9 bit : ªp -1 command ˆ e 8 bit : ƒ queue full e 7 bit : ªp data queue empty e 6 bit : External counter < External comparator e 5 bit : External counter = Exte rnal comparator e 4 bit : External counter > External comparator e 3 bit : Internal counter < Internal comparator e 2 bit : Internal counter = Internal comparator e 1 bit : Internal counter > Internal comparator e 0 bit : dk { n EMODE1 DATA READ 7 bit : Extension mode enable(0 : Disable, 1 : Enable) 0 : md_out[12:8] => md_out[12:8] 1 : md_out[12:8] => EUIO 7B 7C 6~ 5 bit : Don t care 4 bit : EUO4 enable/disable(0 : disable, 1 : enable) 3 bit : EUO3 enable/disable(0 : disable, 1 : enable) 2 bit : EUO2 enable/disable(0 : disable, 1 : enable) 1 bit : EUO1 enable/disable(0 : disable, 1 : enable) 0 bit : EUIO0 direction select(0 : input, 1 : output) Extension UNIVERSAL OUT READ 12~8 bit : Extension Universal output (not Visible) 7 ~ 5 bit : Extension Universal output bit operation 0xx : «OUT m l 100 : NOT(¹ OUT v ) 101 : AND( «¹ OUT and l) 8 0x00 8 0x00 54

61 Hardware Chip User Manual Rev COMMAND ƒr CODE(HEX) p (BUS-2 ROUPl READ) R DEFAULT 110 : OR( «¹ OUT or l) 111 : XOR( «¹ OUT di fference check) 4 ~ 0 bit : Extension Universal in/output 78,7D,7F NO OPERATION USER Interrupt source selection register READ 31~24 bit : User selectable interrupt 3 source selection ªp, x p 7E 23~16 bit : User selectable interrupt 2 source selection ªp, x p 32 0x ~ 8 bit : User selectable interrupt 1 source selection ªp, x p 7 ~ 0 bit : User selectable interrupt 0 source selection ªp, x p 55

62 6. COMMAND ƒr Hardware Chip User Manual Rev. 4.0 CAMC-FS WRITE COMMAND CODE(HEX) p (PM-1 ROUP l WRITE) W DEFAULT 80 PM-1 RANE WRITE 16 0xFFFF 81 PM-1 START/STOP SPEED DATA WRITE 16 0X PM-1 OBJECT SPEED DATA WRITE 16 0X PM-1 RATE-1 DATA WRITE 16 0XFFFF 84 PM-1 RATE-2 DATA WRITE 16 0XFFFF 85 PM-1 RATE-3 DATA WRITE 16 0XFFFF 86 PM-1 RATE CHANE POINT 1-2 WRITE 16 0XFFFF 87 PM-1 RATE CHANE POINT 2 3 WRITE 16 0XFFFF 88 PM-1 SW-1 DATA WRITE 15 0X7FFF 89 PM-1 SW-2 DATA WRITE1 15 0X7FFF 8A PM-1 PWM l ƒ DATA WRITE(0~6) 3 0x00 8B PM-1 SLOW DOWN / REAR PULSE WRITE 32 0X C NO OPERATION 8D PM -1 ¹ SPEED DATA WRITE 16 0x0000 8E 8F NO OPERATION NO OPERATION CO DE(HEX) p (PM-1 UP-DATE ROUPl WRITE) W DEFAULT 90 PM-1 UP-DATE RANE WRITE 16 0xFFFF 91 PM-1 UP-DATE START/STOP SPEED DATA WRITE 16 0X PM-1 UP-DATE OBJECT SPEED DATA WRITE 16 0X PM-1 UP-DATE RATE-1 DATA WRITE 16 0XFFFF 94 PM-1 UP-DATE RATE-2 DATA WRITE 16 0XFFFF 95 PM-1 UP-DATE RATE-3 DATA WRITE 16 0XFFFF 96 PM-1 UP-DATE RATE CHANE POINT 1-2 WRITE 16 0XFFFF 97 PM-1 UP-DATE RATE CHANE POINT 2 3 WRITE 16 0XFFFF 98 PM-1 UP-DATE SW-1 DATA WRITE 15 0X7FFF 99 PM-1 UP-DATE SW-2 DATA WRITE 15 0X7FFF 9A NO OPERATION 9B PM-1 UP-DATE SLOW DOWN / REAR PULSE WRITE 32 0X

63 Hardware Chip User Manual Rev COMMAND ƒr CODE(HEX) p (PM-1 UP-DATE ROUPl WRITE) W DEFAULT 9C NO OPERATION 9D PM-1 ¹ SPEED DATA WRITE 16 0x0000 9E NO OPERATION 9F NO OPERATION CODE(HEX) p (PM-2 ROUPl WRITE) W DEFAULT A0 + PRESET PULSE DRIVE 32 A1 A2 A3 + CONTINUOUS DRIVE + SINAL SEARCH 1 DRIVE + SINAL SEARCH 2 DRIVE A4 + ORIIN ( ) SEARCH DRIVE 1 A5 - PRESET PULSE DRIVE 32 A6 A7 A8 - CONTINUOUS DRIVE - SINAL SEARCH 1 DRIVE - SINAL SEARCH 2 DRIVE A9 - ORIIN ( ) SEARCH DRIVE 1 AA PRESET PULSE DATA OVERRIDE(ON_ BUSY) 32 AB AC AD AE SLOW DOWN STOP EMERENCY STOP DRIVE MODE SETTIN DATA WRITE 2bit : ˆ p (0 : Ž, 1: ) 1~0bit : 00 : ƒ sd 01 : ƒ sd 10 : S- ƒ sd 11 : S- ƒ sd MP OPERATION SETTIN DATA WRITE 6bit : z ˆ¹ Continuous drive 5bit 4~3bit (0 : RESET, 1 : SET) : z ˆ¹ Preset pulse drive (0 : RESET, 1 : SET) : z l ˆ¹ w sd (00 :, 01 2bit : 0 : ƒ w + : 1 w, 10 : 2 w, 11 : 4 w) 3 0x0 7 0X00 57

64 6. COMMAND ƒr Hardware Chip User Manual Rev. 4.0 CODE(HEX) p (PM-2 ROUPl WRITE) W DEFAULT 1 : ƒ w 1bit : 0 : z 2 ² w l 1 : ƒ w l 0bit : z 2 ² (0 : RESET, 1 : SET) AF MP PRESET PULSE DATA WRITE 32 0X CODE(HEX) p (º ROUPl WRITE) W DEFAULT B0 + Sensor positioning drive I 32 B1 - Sensor positioning drive I 32 B2 + Sensor positioning drive II 32 B3 - Sensor positioning drive II 32 B4 + Sensor positioning drive III 32 B5 - Sensor positioning drive III 32 Soft limit ƒ B6 2 bit : Limit ƒ (0 : Internal count, 1 : External count) 1 bit : Soft limit ˆ dk { (0 :, 1 : ) 0 bit : Soft limit Enable/Disable (0 : Enabel, 1 : Disable) 3 0x0 B7 32 0x Soft limit l ƒ + Soft limit l ƒ Trigger mode ƒ 31~16 bit : Trigger active level ƒ B8 32 0x7FFFFFFF B9 1 bit : Trigger count ƒ (0:Inte 0 bit : Trigger mode (0 : sd, 1 : sd Trigger ƒ rnal, 1 : External) ) 32 0x BA 32 0x BB Internal M-data ƒ 32 0x BC External M-data ƒ 32 0x BD ~ BF NO OPERATION CODE(HEX) p ( p ROUPl WRITE) W DEFAULT 58

65 Hardware Chip User Manual Rev COMMAND ƒr CODE(HEX) p ( p ROUPl WRITE) W DEFAULT C0 C1 C2 ªp ƒ l bit : 0 : w ˆ, 1 : ˆ WRITE 30~26bit : Don t care 25~24bit : x 00 : p (1w x p ) 01 : OR 10 : AND 11 : XOR 23~16bit : 2w x ƒ 15~ 8 bit : 1 w x ƒ 7~ 0 bit : x» ˆ COMMAND * x ƒ x ªp ƒ l -2 WRITE ªp ƒ l -1 bit ªp ƒ l -3 WRITE ªp ƒ l -1 bit ªp ƒ l -Queue WRITE 31 bit : 0 : w ˆ, 1 : ˆ 30 bit : ˆ ˆ Interrupt vƒ(0:disable, 1:Enable) 32 0x x x C3 29~26bit : Don t care 25~24bit : x 00 : p (1w x p ) 01 : OR 10 : AND 11 : XOR 23~16bit : 2w x ƒ 15~ 8 bit : 1 w x ƒ 7~ 0 bit : x» ˆ COMM AND 32 0x C4 ªp l -1 WRITE 32 0x C5 ªp l -2 WRITE 32 0x C6 ªp l -3 WRITE 32 0x C7 ªp l -Queue WRITE 32 0x C8 ªp Queue clear CC ªp Queue size ƒ (0~13) 16 0xD0D0 59

66 6. COMMAND ƒr Hardware Chip User Manual Rev. 4.0 CODE(HEX) p ( p ROUPl WRITE) W DEFAULT C9~CB CD~ CF 15~ 12bit : ƒ l -Queue full size 11~ 8 bit : ƒ l -Queue empty siz 7~ 4 bit : l -Queue full size 3~ 0 bit : l -Queue empty siz NO OPERATION e e CODE(HEX) p ( tp ROUPl WRITE) W DEFAULT D0 D1 D2 D3 tp ƒ l -1 WRITE tp ƒ l -Queue WRITE 31 bit : 0 : w ˆ, 1 : ˆ 30~26bit : Don t care 25~24bit : x 00 : p (1w x p ) 01 : OR 10 : AND 11 : XOR 23~16bit : 2w x ƒ 15~ 8 bit : 1 w x ƒ 7~ 0 bit : x» ˆ COMMAND tp ƒ l -2 WRITE tp ƒ l -1 bit tp ƒ l -3 WRITE tp ƒ l -1 bit tp ƒ l -Queue WRITE 31 bit : 0 : w ˆ, 1 : ˆ 30 bit : ˆ ˆ Interrupt vƒ(0:disable, 1:Enable) 29~26bit : Don t care 25~24bit : x 00 : p (1w x p ) 01 : OR 10 : AND 11 : XOR 32 0x x x x

67 Hardware Chip User Manual Rev COMMAND ƒr CODE(HEX) p ( tp ROUPl WRITE) W DEFAULT D8 DC D4~D7 23~16bit : 2w x ƒ 15~ 8 bit : 1 w x ƒ 7~ 0 bit : x» ˆ COMMAND tp Queue clear tp Queue size ƒ (0~13) 15~ 12bit : ƒ l -Queue fu 11~ 8 bit : ƒ l -Queue em ll size 7~ 4 bit : l -Queue full s 3~ 0 bit : l -Queue em pty size ize pty size 16 0xD0D0 D9~DB NO OPERATION DD~DF CODE(HEX) p (BUS-1 ROUPl WRITE) W DEFAULT E0 INTERNAL COUNTER DATA WRITE 32 0x E1 INTERNAL COUNTER COMPARATE DATA WRITE (Signed) 32 0x E2 INTERNAL COUNTER PRE-SCALE DATA WRITE 8 0x00 E3 INTERNAL COUNTER P- DATA WRITE 32 0x7FFFFFFF E4 EXTERNAL COUNTER DATA WRITE 32 0x E5 EXTERNAL COUNTER COMPARATE (Signed) DATA WRITE 32 0x E6 EXTERNAL COUNTER PRE-SCALE DATA WRITE 8 0x00 E7 EXTERNAL COUNTER P- DATA WRITE 32 0x7FFFFFFF E8 EXTERNAL SPEED DATA WRITE 32 0x E9 EXTERNAL SPEED COMPARATE DATA WRITE 32 0x EA z ƒ ³ ƒ DATA WRITE 8 0x05 EB OFF-RANE DATA WRITE 8 0x00 EC NO OPERATION ED PM REISTER CHANE DATA WRITE 1 0x0 EE COMPARE REISTER INPUT CHANE 2 0X00 61

68 6. COMMAND ƒr Hardware Chip User Manual Rev. 4.0 CODE(HEX) p (BUS-1 ROUPl WRITE) W DEFAULT 1~0 bit : 00 : 1 st : Internal count, 2 nd : External count 01 : 1 st : Internal count, 2 nd : Internal count 10 : 1 st : External count, 2 nd : External count EF NO OPERATION CODE(HEX) p (BUS-2 ROUPl WRITE) W DEFAULT F0 ƒ DATA WRITE 12bit : S profile ˆ z (0 : Ž, 1 : ) 11bit : Search source filter z( 0 : Ž, 1 : ) 10bit : Sync z(0 : Ž, 1: ) 9 bit : Limit (0 : Ž, ) 8 bit : Inposition º sd(0: Ž, 1: ) 7 bit : «/ ƒ (0 :, 1 : ) 6 bit : 5 bit : Limit ƒ (0 : ƒ, 1 : d ) sd(0 : Ž, 1 : ) 4 bit : Limit sd(0 : Ž, 1 : ) 3 bit : estop, sstop enable/disable(0 : disable, 1 : enable) 13 0x0C3E 2 bit : Don t care 1 bit : Alarm Stop sd(0 : Ž, 1 : ) 0 bit : Inposition (0 : Ž, 1 : ) MODE1 DATA WRITE 7 bit : ˆ ³ wˆ F1 8 0x00 F2 (0 :, 1 : r ) 6~4 bit : ² l wˆ ƒ (* x { ) 3~0 bit : ˆ¹ ƒ ƒ (* x { ) MODE2 DATA WRITE 10 bit: Trigger ˆ¹ active level ƒ 9 bit: Interrupt active level ƒ 8 bit: MARK ˆ¹ active level ƒ 7~6 bit : Encoder signal count mode(ecup, ECDN signal) 11 0x200 62

69 Hardware Chip User Manual Rev COMMAND ƒr CODE(HEX) p (BUS-2 ROUPl WRITE) W DEFAULT 00 : ˆ¹(ECUP : up l, ECDN : down l) 01 : 90 difference phase, 1 times multiplied 10 : 90 difference phase, 2 times multiplied F3 F4~F6 F7 F8 11 : 90 difference phase, 4 times multiplied 5 bit : INP ˆ¹ ACTIVE LEVEL ƒ 4 bit : ALM ˆ¹ ACTIVE LEVEL ƒ 3 bit : -SLM ˆ¹ ACTIVE LEVEL ƒ 2 bit : +SLM ˆ¹ ACTIVE LEVEL ƒ 1 bit : -ELM ˆ¹ ACTIVE LEVEL ƒ 0 bit : +ELM ˆ¹ ACTIVE LEVEL ƒ UNIVERSAL OUT WRITE 10~8 bit : Universal output bit operation 0xx : «UOUT m l 100 : NOT(¹ UOUT v ) 101 : AND( «¹ UOUT and l) 110 : OR( «¹ UOUT or l) 111 : XOR( «¹ UOUT difference check) 7 ~ 4 bit : Don t care 3 ~ 0 b it : Universal output(uout3~0) NO OPERATION EXTERNAL COUNTER ƒ DATA WRITE 7 bit : 0 : Not reverse count, 1: Reverse count 6 bit : Don t care 5 ~ 4 bit : 00 : CLEAR REQUEST RESET 01 : ONE TIME CLEAR REQUEST SET 10 : FULL TIME CLEAR REQUEST SET 11 : EXTERNAL COUNTER CLEAR SET 3 ~ 0 bit : CLEAR lˆ¹ ƒ 0001 : IN : IN : IN : IN3 Others : Don t care REISTER CLEAR (INITIALIZATION) 11 0x x00 63

70 6. COMMAND ƒr Hardware Chip User Manual Rev. 4.0 CODE(HEX) p (BUS-2 ROUPl WRITE) W DEFAULT F9 Interrupt vƒ Command FA Interrupt MASK(0 : Interrupt Disable, 1 : Enable) 31 bit : Selectable Interrupt source3( FE 31~24bit) 30 bit : Selectable Interrupt source2( FE 23~16bit) 29 bit : Selectable Interrupt source1( FE 15~8bit) 28 bit : Selectable Interrupt source0( FE 7~0bit) 27 bit : Emergency limit ˆ¹ lˆ 26 bit : Slow down limit ˆ¹ lˆ 25 bit : queue rl 17 bit : d 16 bit : 15 bit : Don t care ˆ(30 bit 1 e) 24 bit : ªp queue rl ˆ(30 bit 1 e) 23 bit : M-data count clear 22 bit : ¹ = ¹ 21 bit : ¹ = RCP12 20 bit : ¹ = RCP23 19 bit : MODE1 register ƒ ˆ¹ ˆ 18 bit : 14 bit : -3 command ˆ e 13 bit : -2 command ˆ e 12 bit : -1 command ˆ e 11 bit : ªp -3 command ˆ e 10 bit : ªp -2 command ˆ e 9 bit : ªp -1 command ˆ e 8 bit : ƒ queue full e 7 bit : ªp data queue empty e 6 bit : External counter < External comparator e 5 bit : External counter = External comparator e 4 bit : External counter > External comparator e 3 bit : Internal counter < Internal comparator e 2 bit : Internal counter = Internal comparator e 1 bit : Internal counter > Internal comparator e 0 bit : dk { n 32 0x

71 Hardware Chip User Manual Rev COMMAND ƒr CODE(HEX) p (BUS-2 ROUPl WRITE) W DEFAULT EMODE1 DATA WRITE 7 bit : Extension mode enable(0 : Disable, 1 : Enable) 0 : md_out[12:8] => md_out[12:8] 1 : md_out[12:8] => EUIO FB 6~ 5 bit : Don t care 4 bit : EUO4 enable/disable(0 : disable, 1 : enable) 3 bit : EUO3 enable/disable(0 : disable, 1 : enable) 2 bit : EUO2 enable/disable(0 : disable, 1 : enable) 1 bit : EUO1 enable/disable(0 : disable, 1 : enable) 0 bit : EUIO0 direction select(0 : input, 1 : output) Extension UNIVERSAL OUT WRITE 8 0X00 FC 7 ~ 5 bit : Extension Universal output bit operation 0xx : «OUT m l 100 : NOT (¹ OUT v ) 101 : AND ( «¹ UOUT and l) 110 : OR ( «¹ UOUT or l) 111 : XOR ( «¹ UOUT difference check) 4 ~ 0 bit : Extension Universal output (input tˆ) FD Limit 8 0x00 FE FF USER Interrupt source selection register WRITE 31~24 bit : User selectable interrupt 3 source selection ªp, x p 23~16 bit : User selectable interrupt 2 source selection ªp, x p 15~ 8 bit : User selectable interrupt 1 source selection ªp, x p 7 ~ 0 bit : User selectable interrupt 0 source selection ªp, x p No operation 32 0x

72 6. COMMAND ƒr Hardware Chip User Manual Rev COMMAND 기능설명 ² l l d 2 n m. l rld y m PM-1 l WRITE/READm. l d o p PM-1 UPDATE l WRITE/READ. rld o ± um o ± m dk { ³ º. PM-2 n rld dk { ˆ, p wk d d rldm ƒ. BUS-1 n rld z/ z l rld. BUS-2 n rld ƒ l rld. ªp / tp n rld ªp tp ƒ l rld. d rld ƒ ƒr. PM-1 RANE DATA READ COMMAND ( CODE = 0x00 ) ¹ ƒ PM-1 RANE DATAp COMMAND. DATA3, 15 0 DATA4 port 2 ~2 bit m 16-bit ª m. 16-bit DATA3, DATA4 Address p º r. PM-1 RANE DATA WRITE COMMAND ( CODE = 0x80 ) 15 0 PM-1 RANE DATAp ƒ COMMAND. DATA3, DATA4 port 2 ~2 bit p RANE m. ƒ x 1~65,535(0x0001~0xFFFF) r RESET» y 65,535(0xFFFF). COMMAND ˆ p dk { (BUSY = High) ˆ l ² x et s um. PM-1 START/STOP SPEED DATA READ COMMAND ( CODE = 0x01 ) ¹ ƒ PM-1 START/STOP SPEED DATAp COMMAND DATA3, DATA4 port 2 ~2 bit m 16-bit ª m. 16-bit DATA3, DATA4 Addressp º r. PM-1 START/STOP SPEED DATA WRITE COMMAND ( CODE = 0x81 ) PM-1 START/STOP SPEED DATAp ƒ COMMAND. DATA3, DATA4 port 2 15 ~2 0 bit p START/STOP SPEED m. ƒ x 1~65,535(0x0001~0xFFFF) r RESET» y 1(0x0001). COMMAND ˆ p dk { (BUSY = High) ˆ v/ x um. PM-1 OBJECT SPEED DATA READ COMMAND ( CODE = 0x02 ) ¹ ƒ PM-1 OBJECT SPEED DATAp COMMAND. DATA3, 66

73 Hardware Chip User Manual Rev COMMAND ƒr DATA4 port 2 15 ~2 0 bit m 16-bit ª m. 16-bit DATA3, DATA4 Address p º r. PM-1 OBJECT SPEED DATA WRITE COMMAND ( CODE = 0x82 ) PM-1 OBJECT SPEED DATAp ƒ COMMAND. DATA3, DATA4 port 2 15 ~2 0 bit p OBJECT SPEED m. ƒ x 1~65,535(0x0001~0xFFFF) r RESET» y 1(0x0001). COMMAND ˆ p dk { (BUSY = High) ˆ s x um. PM-1 RATE-n (n=1, 2, 3) DATA READ COMMAND ( CODE = 0x03, 0x04, 0x05 ) ¹ ƒ PM-1 RATE-n (n=1, 2, 3) DATAp COMMAND. DATA3, DATA4 port 2 15 ~2 0 DATA4 Addressp º r. bit m 16-bit ª m. 16-bit DATA3, PM-1 RATE-n (n=1, 2, 3) DATA WRITE COMMAND ( CODE = 0x83, 0x84, 0x85 ) PM-1 RATE-n (n=1, 2, 3) DATAp ƒ COMMAND. DATA3, DATA4 port 2 15 ~2 0 bit p RATE-n (n=1, 2, 3) m. ƒ x 1~65,535(0x0001~0xFFFF) r RESET» y 65,535(0xFFFF). COMMAND ˆ p dk { (BUSY = High) ˆ l ² xº. lum ² ƒ dk { RATE-n (n=1, 2, 3) p x. PM-1 RATE CHANE POINT n(n=1-2, 2-3) READ COMMAND ( CODE = 0x06, 0x07) ¹ ƒ PM-1 Rate Change Point n(n=1 2, 2 3) DATAp COMMAND DATA3, DATA4 port 2 ~2 bit m 16-bit ª m. 16-bit DATA3, DATA4 Addressp º r. Command ˆ. PM-1 RATE CHANE POINT n(n=1-2, 2-3) WRITE COMMAND ( CODE = 0x86, 0x87) Command. Data 3, 4 Portp PM-1 Rate Change Point n(n=1 2, 2 3) Datap ƒ ƒ x 1~65,535(0x0001~0xFFFF) r RESET» y 65,535(0xFFFF). Command ˆ ˆ p Drive (BUSY = High) ˆ m ƒ PM- 1 Rata Change Point n(n=1-2, 2-3) Data ek x ( ) v. ekƒ ² ˆ ˆ Ž um. 67

74 6. COMMAND ƒr Hardware Chip User Manual Rev. 4.0 PM-1 S W-n (n=1, 2) DAT A READ COMMAND ( CODE = 0x08, 0x09 ) ¹ ƒ PM-1 SW-n (n=1, 2) (S-curve Width) DATAp COMMAND. 14 ~2 0 bit m 15-bit ª m. 15-bit DATA3, DATA3, DATA4 port 2 D ATA4 Addressp º r. PM-1 SW-n (n=1, 2) DATA WRITE COMMAND ( CODE = 0x88, 0x89 ) PM-1 SW-n (n=1, 2) (S-curve Width) DATAp ƒ COMMAND. ƒ m ƒ g S ƒ ƒ rl. PM-1 SW-n (n=1, 2) 0x7FFFm ƒ r S ƒ, 0x0000m ƒ r ƒ. RESET» y 0x7FFF. d k { x vƒ. PM-1 PWM l ƒ DATA READ COMMAND ( CODE = 0x0A ) ¹ ƒ PM-1 PWM l ƒ DATAp COMMAND. DATA4 port. DATA4 Addressp º r. PM-1 PWM l ƒ DATA WRITE COMMAND ( CODE = 0x8A ) PM-1 PWM l ƒ DATAp ƒ COMMAND. COMMAND ƒ DATAm PWM l ±¹ ƒ. 0x0 r 0~6(0x00~0x06) ƒ. PM-1 SLOW DOWN/REAR PULSE READ COMMAND ( CODE = 0x0B ) ¹ ƒ PM-1 SLOW DOWN/READ PULSE DATAp COMMAND. DATA1, DATA2, DATA3, DATA4 port 2 31 ~2 0 bit m 32-bit ª m. 32-bit DATA1, DATA2, DATA3, DATA4 Addressp º r. PM-1 SLOW DOWN/REAR PULSE WRITE COMMAND ( CODE = 0x8B ) PM-1 SLOW DOWN/REAR PULSE DATAp ƒ COMMAND. DATA1, DATA2, DATA3, DATA4 port 2 31 ~2 0 bit 32-bit p PM-1 SLOW DOWN/READ PULSE m ƒ. RESET» y 0 (0x ) r ƒ x 0 ~ 4,294,967,295(0x ~ 0xFFFFFFFF). SLOW DOWN / REAR PULSE DATA ² dk { ƒ ˆ «v um ƒ ek dk { ¹ k. 1) wˆ» ˆ / m l ² ( p zz)p., zz ² ² dk { ƒ ² p ³. 68

75 Hardware Chip User Manual Rev COMMAND ƒr SPEED ô øä TIME 6.1. q e 2) PULSE wˆ ˆ «v ² ( p zz)p., ² ƒ ˆ / Ž, ˆ / ƒz ˆ m e ˆ. SPEED SPEED ô ô øä øä TIME TIME 6.2. p PULSE vr e p PULSE vr e 2 COMMAND ˆ ˆ p, DRIVE (BUSY = H ) ˆ ¹ DRIVE v Ž DRIVE ez v. PM-1 ¹ SPEED DATA READ COMMAND ( CODE = 0x0C ) ¹ l p l COMMAND. DATA DATA3, DATA4 port 2 15 ~2 0 bit m 16-bit ª m. COMMAND ˆ p, dk { (BUSY = Low) COMMANDp ˆ 0(0x0000) ¹. 69

76 6. COMMAND ƒr Hardware Chip User Manual Rev. 4.0 PM-1 ¹ SPEED DATA READ COMMAND ( CODE = 0x0D ) ¹ l ¹ SPEED DATAp l COMMAND. DATA DATA3, DATA4 port 2 15 ~2 0 bit m 16-bit ª m. PM-1 ¹ SPEED DATA WRITE COMMAND ( CODE = 0x8D ) ² l dk { l ¹ PM-1 ¹ SPEED DATAp ƒ COMMAND. RESET» ¹ SPEED DATA y 0(0x0000) r, ƒ x 0~65,535(0x0000~0xFFFF) r DATA3, DATA4 port 2 15 ~2 0 bit 16-bit ¹ SPEED DATAm. PM-1 DRIVE PULSE COUNTER READ COMMAND ( CODE = 0x0E ) dk { l ² COMMAND. x 0~4,294,967,295(0x ~0xFFFFFFFF) r, ¹ dk { ƒ l ² l. ekƒ dk { n» 0(0x ). PM-1 PRESET PULSE DATA READ COMMAND ( CODE = 0x0F ) PM-1 ƒ m PRESET PULSE dk {( ² dk {) l ² p COMMAND. DATA DATA1, DATA2, DATA3, DATA4 port 2 31 ~2 0 bit m 32-bit ª m. PM-1 UP-DATE RANE READ COMMAND ( CODE = 0x10 ) ¹ ƒ PM-1 UP-DATE RANE DATAp COMMAND. DATA3, DATA4 port 2 15 ~2 0 DATA4 Addressp º r. bit m 16-bit ª m. 16-bit DATA3, PM-1 UP-DATE RANE WRITE COMMAND ( CODE = 0x90 ) PM-1 UP-DATE RANE DATAp ƒ COMMAND. DATA3, DATA4 port 2 15 ~2 0 bit p RANE m. ƒ x 1~65,535(0x0001~0xFFFF) r RESET» y 65,535(0xFFFF). COMMAND ˆ p dk { (BUSY = High) ˆ l ² x et s um. PM-1 UP-DATE START/STOP SPEED DATA READ COMMAND ( CODE = 0x11 ) ¹ ƒ PM-1 UP-DATE START/STOP SPEED DATAp COMMAND. DATA3, DATA4 port 2 15 ~2 0 bit m 16-bit ª m. 16-bit DATA4 Addressp º r. DATA3, 70

77 Hardware Chip User Manual Rev COMMAND ƒr PM-1 UP-DATE START/STOP SPEED DATA WRITE COMMAND ( CODE = 0x91 ) PM-1 UP-DATE START/STOP SPEED DATAp ƒ COMMAND. DATA3, DATA4 port 2 15 ~2 0 bit p START/STOP SPEED m. ƒ x 1~65,535(0x0001~0xFFFF) r RESET» y 1(0x0001). COMMAND ˆ p dk { (BUSY = High) ˆ v/ x um. PM-1 UP-DATE OBJECT SPEED DATA READ COMMAND ( CODE = 0x12 ) ¹ ƒ PM-1 UP-DATE OBJECT SPEED DATAp COMMAND. DATA3, DATA4 port 2 15 ~2 0 bit m 16-bit ª m. 16-bit DATA3, DATA4 Addressp º r. PM-1 UP-DATE OBJECT SPEED DATA WRITE COMMAND ( CODE = 0x92 ) PM-1 UP-DATE OBJECT SPEED DATAp ƒ COMMAND. DATA3, DATA4 port 2 15 ~2 0 bit p OBJECT SPEED m. ƒ x 1~65,535(0x0001~0xFFFF) r RESET» y 1(0x0001). COMMAND ˆ p dk { (BUSY = High) ˆ s x um. S sdm dk { ˆ OBJECT SPEED DATAp x S rl 2w ˆ Ž. PRESET PULSE DRIVE OBJECT SPEED DATAp x ˆ SLOW DOWM/REAR PULSE WRITE COMMANDp Ž. ƒ ˆ zm. PM-1 UP-DATE RATE-n (n=1, 2, 3) DATA READ COMMAND ( CODE = 0x13, 0x14, 0x15 ) ¹ ƒ PM-1 UP-DATE RATE-n (n=1, 2, 3) DATAp COMMAND. DATA3, DATA4 port 2 15 ~2 0 bit m 16-bit ª m. 16-bit DATA3, DATA4 Addressp º r. PM-1 UP-DATE RATE-n (n=1, 2, 3) DATA WRITE COMMAND ( CODE = 0x93, 0x94, 0x95 ) P M-1 UP-DATE RATE-n (n=1, 2, 3) DATAp ƒ COMMAND. DATA3, DATA4 port 2 15 ~2 0 bit p PM-1 UP-DATE RATE-n (n=1, 2, 3) m. ƒ x 1~65,535(0x0001~0xFFFF) r RESET» y 65,535(0xFFFF). COMMAND ˆ p dk { (BUSY = High) ˆ l ² xº. lum ² ƒ dk { PM-1 UP-DATE RATE-n (n=1, 2, 3) p x. PM-1 UP-DATA RATE CHANE POINT n(n=1-2, 2-3) READ COMMAND ( CODE = 0x16, 0x17) ¹ ƒ PM-1 UP-DATA Rate Change Point n(n=1 2, 2 3) DATAp COMMAND DATA3, DATA4 port 2 15 ~2 0 bit m 16-bit ª m. 16-bit. 71

78 6. COMMAND ƒr Hardware Chip User Manual Rev. 4.0 DATA3, DATA4 Addressp º r. Command ˆ. PM-1 UP-DATA RATE CHANE POINT n(n=1-2, 2-3) WRITE COMMAND ( CODE = 0x96, 0x97) Data 3, 4 Portp PM-1 UP-DATA Rate Change Point n(n=1 2, 2 3) Datap ƒ Command. ƒ x 1~65,535(0x0001~0xFFFF) r RESET» y 65,535(0xFFFF). Command ˆ ˆ p Drive (BUSY = High) ˆ m ƒ PM- 1 Rata Change Point n(n=1-2, 2-3) Data ek x ( ) v. ekƒ ² ˆ ˆ Ž um. PM-1 UP-DATE SW-n (n=1, 2) DATA READ COMMAND ( CODE = 0x18, 0x19 ) ¹ ƒ PM-1 UP-DATE SW-n (n=1, 2) DATAp COMMAND. DATA3, DATA4 port 2 14 ~2 0 DATA4 Addressp º r. bit m 15-bit ª m. 15-bit DATA3, PM-1 UP-DATE SW-n (n=1, 2) DATA WRITE COMMAND ( CODE = 0x98, 0x99 ) PM-1 UP-DATE SW-n (n=1, 2) (S-curve Width) DATAp ƒ COMMA ND. ƒ m ƒ g S ƒ ƒ rl. PM-1 UP-DATE SW-n (n=1, 2) 0x7FFFm ƒ r S ƒ, 0x0000m ƒ r ƒ. RESET» y 0x7FFF. dk { x vƒ. PM-1 CURRENT SPEED CHANE DATA READ COMMAND (0x1A) ¹ ƒ PM-1 CURRENT SPEED CHANE DATAp COMMAND. DATA3, DATA4 port 2 15 ~2 0 bit m 16-bit ª m. 16-bit DATA3, DATA4 Addressp º r. PM-1 CURRENT SPEED CHANE DATA WRITE COMMAND (0x9A) ¹ l SPEED DATA x COMMAND. RESET» PM-1 CURRENT SPEED CHANE DATA y 0(0x0000) r, ƒ x 0~65,535(0x0000~0xFF DATA4 port 2 15 ~2 0 bit 16-bit PM-1 CURRENT SPEED CHANE DATAm., Preset Drive S ˆ vp Ž. FF) rdata3, PM-1 UP-DATE SLOW DOWN/REAR PULSE READ COMMAND ( CODE = 0x1B ) ¹ ƒ PM-1 UP-DATE SLOW DOWN/READ PULSE DATAp COMMAND. DATA1, DATA2, DATA3, DATA4 port 2 31 ~2 0 bit m 32-bit ª m. 32-bit DATA1, DATA2, DATA3, DATA4 Addressp º r. 72

79 Hardware Chip User Manual Rev COMMAND ƒr PM-1 UP-DATE SLOW DOWN/REAR PULSE WRITE COMMAND ( CODE = 0x9B ) PM-1 UP-DATE SLOW DOWN/REAR PULSE DATAp ƒ COMMAND. DATA1, DATA2, DATA3, DATA4 port 2 31 ~2 0 bit 32-bit p PM-1 UP-DATE SLOW DOWN/READ PULSE m ƒ. RESET» y 0 (0x ) r ƒ x 0 ~ 4,294,967,295(0x ~ 0xFFFFFFFF). SLOW DOWN / REAR PULSE DATA ² dk { ƒ ˆ «v um ƒ ek dk { ¹ k. 1) wˆ» ˆ / m l ² ( p zz)p., zz ² ² dk { ƒ ² p ³. SPEED ô øä TIME 6.4. q e 2) PULSE wˆ ˆ «v ² ( p zz)p., ² ƒ ˆ / Ž, ˆ / ƒz ˆ m e ˆ. SPEED SPEED ô ô øä øä TIME TIME 73

80 6. COMMAND ƒr Hardware Chip User Manual Rev p PULSE vr e p PULSE vr e 2 COMMAND ˆ ˆ p, DRIVE (BUSY = H ) ˆ ¹ DRIVE v Ž DRIVE ez v. PM-1 UP-DATE ¹ SPEED DATA READ COMMAND ( CODE = 0x1C ) PM-1 UP-DATE ¹ l p l COMMAND. DATA 15 0 DATA3, DATA4 port 2 ~2 bit m 16-bit ª m. COMMAND ˆ p, dk { (BUSY = Low) COMMANDp ˆ 0(0x0000) ¹. PM-1 UP-DATE ¹ SPEED DATA READ COMMAND ( CODE = 0x1D ) PM-1 UP-DATE ¹ l ¹ SPEED DATAp l COMMAND. DATA DATA3, DATA4 port 2 15 ~2 0 bit m 16-bit ª m. PM-1 UP-DATE ¹ SPEED DATA WRITE COMMAND ( CODE = 0x9D ) ² l dk { l ¹ PM-1 UP-DATE ¹ SPEED DATAp ƒ COMMAND. RESET» ¹ SPEED DATA y 0(0x0000) r, ƒ x 0~65,535(0x0000~0xFFFF) r DATA3, DATA4 port 2 15 ~2 0 bit 16-bit ¹ SPEED DATAm. PM-1 UP-DATE DRIVE PULSE COUNTER READ COMMAND ( CODE = 0x1E ) PM-1 UP-DATE dk { l ² COMMAND. x 0~4,294,967,295(0x ~0xFFFFFFFF) r, ¹ dk { ƒ l ² l. ekƒ dk { n» 0(0x ). PM-1 UP-DATE PRESET PULSE DATA READ COMMAND ( CODE = 0x1F ) PM-1 UP-DATE ƒ m PRESET PULSE dk {( ² dk {) l ² p COMMAND. DATA DATA1, DATA2, DATA3, DATA4 port 2 31 ~2 0 bit m 32-bit ª m. +/- PRESET PULSE DRIVE WRITE COMMAND( CODE = 0xA0, 0xA5 ) CW(+) g CCW(-) w m ² dk {p ˆ COMMAND. DATA1, DATA2, DATA3, DATA4 port ² (dk { l ² ) p» +/- PRESET PULSE DRIVE COMMANDp ˆ. ² ƒ x 0~4,294,967,295(0x ~0xFFFFFFFF), DATA1, DATA2, DATA3, 31 0 DATA4 port 2 ~2 bit m 32-bit ª m ² p ƒ r ². dk { ˆ» ² p«² p l» dk {p n. dk { ƒ r 74

81 Hardware Chip User Manual Rev COMMAND ƒr l l 2bit setting ekƒ l ² ƒ l ² p, z ² ( z )p. PRESET PULSE DRIVE COMMAND n» END STATUS l 0x000. rl ˆ p dk { (BUSY = High) rl ˆ tº. +/- CONTINUOUS DRIVE WRITE COMMAND ( CODE = 0xA1, 0xA6 ) CW(+) g CCW(-) w m dk {p ˆ COMMAND. dk { ˆ» d k { n rl g dk { n ˆ¹ l e s ² p l. rl ˆ p dk { (BUSY = High) rl ˆ tº. +/- SINAL SEARCH 1 DRIVE WRITE COMMAND ( CODE = 0xA2, 0xA7 ) CW(+) g CCW(-) w m ˆ¹ dk {p ˆ COMMAND. SINAL SEARCH 1 DRIVE dk { ˆ» ˆ ƒ s rƒ ƒ ˆ¹. ˆ¹ ƒ v, ƒ MODE1(0xF1) ƒ. ˆ¹ ˆ END STATUS l 0x400. ˆ¹ l +/- ELM/SLM (Emergency/Slow Down Limit) ˆ¹p ƒ rl ƒ Emergency Limit Disable/Slow Down Limit Disablem ƒ» Ž. Emergency/Slow Down Limit Enablem ƒ» +/- ELM/SLMp ˆ¹ ˆ¹m Limit ˆ¹ / ƒ ˆ¹ vp Ž. rl ˆ p dk { (BUSY = High) rl ˆ tº. +/- SINAL SEARCH 2 DRIVE WRITE COMMAND ( CODE = 0xA3, 0xA8 ) CW(+) g CCW(-) w m ˆ¹ dk {p ˆ COMMAND. SINAL SEARCH 2 DRIVE ˆ m d dk {p r dk { ˆ¹ r ² l. ˆ¹ ƒ v, ƒ MODE1(0xF1) ƒ. ˆ¹ ˆ END STATUS l 0x400. ˆ¹ l +/- ELM/SLM (Emergency/Slow Down Limit) ˆ¹p ƒ rl ƒ Emergency Limit Disable/Slow Down Limit Disablem ƒ» Ž. Emergency/Slow Down Limit Enablem ƒ» +/- ELM/SLMp ˆ¹ ˆ¹m Limit ˆ¹ / ƒ ˆ¹ vp Ž. rl ˆ p dk { (BUSY = High) rl ˆ tº. +/- HOME ( ) SEARCH DRIVE (CODE =0xA4, H 0xA9) ome Search Drive dk { ˆ rl m y. 75

82 6. COMMAND ƒr Hardware Chip User Manual Rev. 4.0 CW(+) g CCW(-) w m r ˆ¹ lˆ edge point (rising/falling)p ƒ. ˆ END STATUS l 9bit HIHm ˆ. rl ˆ p dk { (BUSY = High) rl ˆ tº. PRESET/MP PULSE DATA OVERRIDE WRITE COMMAND ( CODE = 0xAA ) PRESET/MP PULSE DATAp x COMMAND. ² ƒ x 0~4,294,967,295(0X ~0XFFFFFFFF), DATA1, DATA2, DATA3, DATA4 port 2 31 ~2 0 bit m 32-bit ª m ² p ƒ r ². ² dk { ² p x rl r. rl ² p x rl um ² dk { ˆ v. rl x ² ek ƒ ƒr ƒ vƒ um Ž. OVERRIDE rl ˆ vƒ um. OVERRIDE rl ˆ vƒ um. 1) CASE 1 m ƒ ² v l p ² ² p ƒ m et COMMAND ˆ m. SPEED ô øä COMMAND µ TIME 6.7. n PULSE vrp p rv q 2) CASE 2 m ƒ ² ˆ ƒz z, rl ˆ m ˆ p ² p r. 76

83 Hardware Chip User Manual Rev COMMAND ƒr SPEED ô øä COMMAND µ TIME 6.8. n PULSE vrp p rv q SLOW DOWN STOP WRITE COMMAND ( CODE = 0xAB ) dk {p ˆ«COMMAND. rl ˆ ˆ p dk { (BUSY = Low) ˆ ˆ«Žtl v. g rl ² l END STATUS l SSCED Bit(Slowdown Stop Command END Bit, 4 bit) 1(High)m. EMERENCY STOP WRITE COMMAND ( CODE = 0xAC ) dk {p ˆ«COMMAND. rl ˆ ˆ p dk { (BUSY = Low) ˆ ˆ«Žtl v. g rl ² l END STATUS l ESCED Bit(Emergency Stop Command END Bit, 5 bit) 1(High)m. DRIVE MODE SETTIN DATA WRITE COMMAND ( CODE = 0xAD ) dk { ƒ p ƒ COMMAND. RESET» 0x0. DATA4 port 2 2 ~2 0 bit m 3-bit ª p dk { ƒ m. COMMANDm ƒ p / sdp ƒ. dk { ƒ. 77

84 6. COMMAND ƒr Hardware Chip User Manual Rev. 4.0 ˆ p Ž 00 : ƒ sd 01 : ƒ sd 10 : S- ƒ sd 11 «ƒ sd ˆ p (2 bit) ² dk { ƒ. l ² p z m. ekƒ ƒ l ² ² k z s º ( z m º yp ) ² e ² dk { Ž. 1 ~0 bit dk { ¹ sdp ƒ Bit. MP OPERATION SETTIN DATA WRITE COMMAND (CODE =0xAE) MP OPERATION SETTIN DATAp ƒ COMMAND. 7BIT l r BIT. z ˆ¹ Continuous drive (0 : RESET, 1 : SET) z ˆ¹ Preset pulse drive (0 : RESET, 1 : SET) 00: 01: 1 w 10: 2 w 11: 4 w 0 : ƒ w +, 1 : ƒ w - 0 : z 2 ² w l Xa ƒ w l zy ² OWaylzl{SXazl{P MP PRESET PULSE DATA WRITE (CODE=0xAF) M P Preset Pulse Drive ƒ l ² p ƒ COMMAND.. RESET» MP PRESET PULSE DATA y 0(0x ). +/- Sensor Positioning Drive (CODE=0xB0, 0xB1) CW(+) g CCW(-) w m MARK ˆ¹ edge r, ² p«dk {p ˆ COMMAND. DATA1, DATA2, DATA3, DATA4 port ² (d k { l ² )p» +/- Sensor Positioning Drive COMMANDp ˆ. ² ƒ x 0~4,294,967,295(0x ~0xFFFFFFFF), DATA1, DATA2, DATA3, DATA4 port 2 31 ~2 0 bit m 32-bit ª m ² p ƒ r ². dk { ˆ» ² p«² p l» dk {p n. dk { ƒ r l(0xad) l 2bit setting ekƒ l ² ƒ l ² p, z ² ( z )p. S ENSOR POSITIONIN DRIVE COMMAND n» END STATUS l 0x

85 Hardware Chip User Manual Rev COMMAND ƒr rl ˆ p dk { (BUSY = High) rl ˆ tº. Sensor Positioning Drive ƒ MARK ˆ¹ l. +/- Sensor Positioning Drive (CODE= 0xB2, 0xB3) CW(+) g CCW(-) w m MARK ˆ¹ edge r, ² p«dk {p ˆ COMMAND. DATA1, DATA2, DATA3, DATA4 port ² (d k { l ² )p» +/- Sensor Positioning Drive COMMANDp ˆ. ² ƒ x 0~4,294,967,295(0x ~0xFFFFFFFF), DATA1, DATA2, DATA3, DATA4 port 2 31 ~2 0 bit m 32-bit ª m ² p ƒ r ². dk { ˆ» ² p«² p l» dk {p n. dk { ƒ r l(0xad) l 2bit setting ekƒ l ² ƒ l ² p, z ² ( z )p. SENSOR POSITIONIN DRIVE COMMAND n» END STATUS l 0x1000. rl ˆ p dk { (BUSY = High) rl ˆ tº. Sensor Positioning Drive ƒ MARK ˆ¹ l Start/Stop Speed datam d. +/- Sensor Positioning Drive (CODE=0xB4, 0xB5) CW(+) g CCW(-) w m MARK ˆ¹ edge r, ² p«dk {p ˆ COMMAND. DATA1, DATA2, DATA3, DATA4 port ² (d k { l ² )p» +/- Sensor Positioning Drive COMMANDp ˆ. ² ƒ x 0~4,294,967,295(0x ~0xFFFFFFFF), DATA1, DATA2, DATA3, DATA4 port 2 31 ~2 0 bit m 32-bit ª m ² p ƒ r ². dk { ˆ» ² p«² p l» dk {p n. dk { ƒ r l l 2bit setting ekƒ l ² ƒ l ² p, z ² ( z )p. SENSOR POSITIONIN DRIVE COMMAND n» END STATUS l 0x000. rl ˆ p dk { (BUSY = High) rl ˆ tº. S ensor Positioning Drive ƒ m Start/Stop Speed datam d. Soft limit ƒ READ (CODE = 0x36) soft limit z v soft limit e drive o, p soft limit p ƒ Soft limit ƒ WRITE (CODE = 0xB6)p y rl. Soft limit ƒ WRITE (CODE = 0xB6) soft limit z v soft limit e drive o, p soft limit p ƒ rl. 79

86 6. COMMAND ƒr Hardware Chip User Manual Rev. 4.0 DATA4 port 2 2 ~2 0 bit m 3-bit ª m ƒ r bit ƒ. Limit ƒ (0 : Internal count, 1 : External count) Soft limit ˆ dk {(0:, 1: ) Soft limit Enable/Disable(1 : Enabel, 0 : Disable) RVT Soft limit l ƒ READ (CODE = 0x37, 0x38) +/- soft limit p rl. RVT Soft limit l ƒ WRITE (CODE = 0xB7, 0xB8) +/- soft limit p ƒ rl. Trigger mode ƒ READ (CODE = 0x39) CAMC-FS ƒ p v ek ƒ Active Level ˆ¹p z trigger pin m l. commandp l trigger ˆ¹ ² ³ v trigger ˆ¹p vƒ ˆ«ˆ ( «), p l sd y. Trigger l sdp m ƒ trigger ƒ (internal ¹ external ) trigger ˆ ¹ l r, sd trigger (0xBA) p«(internal ¹ External ) ¹ trigger ˆ¹ l.(. trigger ˆ¹ acrive level mode2 l 10bit ƒ ƒ.) l trigger ˆ¹ vision application ƒ area scan( sd) v line scan CCD( sd) s. ½ line scan CCD q v p v p CAPTURE Ž um vdˆ r, x ydp ŽŽ. bit ƒ Trigger mode ƒ WRITE (CODE = 0xB9). Trigger mode ƒ WRITE (CODE = 0xB9) l trigger ˆ¹ ² ³ v trigger ˆ¹p vƒˆ«ˆ ( «), p l sd ƒ rl. Trigger º v disable trigger active level lˆ 0x0000m r. bit ƒ. Trigger active level lˆ ƒ ˆ = main clock x (Decimal value of 31~16bit) { ŽŽŒ Š œ OWap Œ ˆ SXalŸ Œ ˆ P { ŽŽŒ ŒOWa sdsxa sdp Trigger ƒ READ (CODE = 0x3A) 80

87 Hardware Chip User Manual Rev COMMAND ƒr Trigger ƒ y rl. Trigger ƒ WRITE (CODE = 0xBA) Trigger ƒ rl. INTERNAL COUNTER M_DATA READ (CODE = 0x3B) ¹ ƒ z (M_DATA)p COMMAND. DATA1, DATA2, DATA3, DATA4 port 2 31 ~2 0 bit m 32-bit ª m. DATA INTERNAL COUNTER M_DATA WRITE (CODE = 0xBB) z (M_DATA)p ƒ COMMAND. DATA1, DATA2, DATA3, DATA4 port ƒ 32-bit ª m ƒ. RESET» 0x EXTERNAL COUNTER M_DATA READ (CODE = 0x3C) ¹ ƒ z (M_DATA)p COMMAND. DATA DATA1, DATA2, DATA3, DATA4 port 2 31 ~2 0 bit m 32-bit ª m. EXTERNAL COUNTER M_DATA WRITE (CODE = 0xBC) z (M_DATA)p ƒ COMMAND. DATA1, DATA2, DATA3, DATA4 port ƒ 32-bit ª m ƒ. RESET» 0x ªp ƒ l -n (n=1, 2, 3) READ COMMAND ( CODE = 0x40, 0x41, 0x42 ) ¹ ƒ ªp ƒ l -n (n=1, 2, 3) p COMMAND. DATA DATA1, DA TA2, DATA3, DATA4 port 2 31 ~2 0 bit m 32-bit ª m r, 32-bit. x ƒ x w ˆ ˆ x p w x p ªª ª «ªª w x ƒ w x ƒ x» ˆ ªªª ª 81

88 6. COMMAND ƒr Hardware Chip User Manual Rev. 4.0 ªp ƒ l -n (n=1, 2, 3) WRITE COMMAND ( CODE = 0xC0, 0xC1, 0xC2 ) ªp ƒ l -n (n=1, 2, 3) ƒ COMMAND. RESET» 0x x» ˆ COMMAND l -n (n=1, 2, 3) (CODE = 0x C4, 0xC5, 0xC6) ƒ. DATA1, DATA2, DATA3, DATA4 port 2 31 ~2 0 bit m 32-bit ª m ƒ r bit ƒ. w ˆ ˆ x p w x p ªª ª «ªª w x ƒ w x ƒ x» ˆ ªªª ª ) ªp ƒ l ªp l ƒ» l Ž. l Ž ªp ªp rl ˆ o v ƒ. x ƒ x ªp ƒ l -Queue READ COMMAND ( CODE = 0x43 ) ¹ ƒ ªp ƒ l - Queue p COMMAND. DATA DATA1, DATA2, DATA3, DATA4 port 2 31 ~2 0 bit m 32-bit ª m r, 32-bit. ªp ƒ l -Queue Depth 13 Queuem ƒ. COMMAND ƒ READ 0, r x. w ˆ ˆ x ƒ x ˆ ˆ ª vƒ x p w x p ªª ª «ªª w x ƒ w x ƒ x» ˆ ªªª ª 82

89 Hardware Chip User Manual Rev COMMAND ƒr ªp ƒ l -Queue WRITE COMMAND ( CODE = 0xC3 ) ªp ƒ l -Queue ƒ COMMAND. RESET» 0x m ƒ. DATA1, DATA2, DATA3, DATA4 port 2 31 ~2 0 bit m 32-bit ª m ƒ r bit ƒ. w ˆ ˆ ˆ ˆ ª vƒ x p w x p ªª ª «ªª w x ƒ w x ƒ x» ˆ ªªª ª ) ªp ƒ l ªp l ƒ» l Ž. l Ž ªp ªp rl ˆ o v ƒ. x ƒ x ªp ƒ l -Queue Depth 13 Queue(FIFO)m ƒ., 13 COMMANDp l ƒ m ˆ., r l DATA x p COMMANDp ˆ r l x COMMANDp ˆ. x» ˆ COMMAND DATA ªp l - Queue (CODE = 0xC3) ƒ ƒ r ƒ l l º p ˆ Queue m ƒ Ž. ˆ COMMAND 0x l l ƒ l Queue l Queue ƒm m ƒ Ž vp. COMMAND ˆ» ƒ l 31bit 0 r m Clear. ƒ Queue ƒ Queue READ rl (CODE = 0x49) ˆ Ž r, ƒ Queue v Queue Full/Empty Queue Full/Empty Flag l READ (CODE = 4B) º. p dr w s p d e x, ˆ ˆ p x ƒ. e ªp l -4 x s -1, s -2, ˆ p ƒ Žƒ l Ž. ƒ : d ˆ x s -1 l(code=0xc7) 0x00000D82 : d ˆ s x -1 (CODE = 0xC3) 83

90 6. COMMAND ƒr Hardware Chip User Manual Rev. 4.0 ƒ : d ˆ x s -2 l(code=0xc7) 0x00000D82 : d ˆ s x -2 (CODE = 0xC3) ƒ : ˆ x ˆ l(code=0xc7) 0x00000E81 : ˆ ˆ x (CODE = 0xC3) ªp l -n (n=1, 2, 3) READ COMMAND ( CODE = 0x44, 0x45, 0x46 ) ¹ ƒ ªp l -n (n=1, 2, 3) p COMMAND. DATA DATA1, DATA2, DATA3, DATA4 port 2 31 ~2 0 bit m 32-bit ª m r, 32-bit ªp ƒ l -n (n=1, 2, 3) ƒ rl ˆ. ªp l -n (n=1, 2, 3) WRITE COMMAND ( CODE = 0xC4, 0xC5, 0xC6 ) ªp l -n (n=1, 2, 3) ƒ COMMAND. RESET» 0x m ƒ. DATA1, DATA2, DATA3, DATA4 port 2 31 ~2 0 bit m 32-bit ª m ªp ƒ l -n (n=1, 2, 3) ƒ rl ˆ. ªp l -Queue READ COMMAND ( CODE = 0x47 ) ¹ ƒ ªp l -Queue p COMMAND. DATA DATA1, DATA2, DATA3, DATA4 port 2 31 ~2 0 bit m 32-bit ª m r, ªp ƒ l -Queue ƒ rl ˆ. ªp l -Queue ªp ƒ l -Queue Depth 13 Queuem ƒ r 0 READ. ªp l -Queue WRITE COMMAND ( CODE = 0xC7 ) ª p ƒ l -Queue ƒ COMMAND. RESET» 0x m ƒ. DATA1, DATA2, DATA3, DATA4 port 2 31 ~2 0 bit m 32-bit ª m ƒ r ªp ƒ l -4 ƒ rl ˆ p l e COMMAND. ªp ƒ / l -Queue CLEAR COMMAND ( CODE = 0xC8 ) ªp ƒ / l -Queue sd p º COMMAND. ˆ» Queue Clear 0 m º. ªp ƒ Queue READ COMMAND ( CODE = 0x49 ) ¹ ªp ƒ l -Queue ( ) COMMAND. DATA DATA4 prot 2 3 ~2 0 bitm 4-bit ª m. 84

91 Hardware Chip User Manual Rev COMMAND ƒr, ªp ƒ r r p Ž. ªp Queue READ COMMAND ( CODE = 0x4A ) ¹ ªp l -Queue ( ) COMMAND. DATA DATA4 prot 2 3 ~2 0 bitm 4-bit ª m. ªp Queue Full/Empty Flag READ COMMAND ( CODE = 0x4B ) ªp ƒ / l -Queue Full/Empty Flag l C OMMAND. 4 BIT l r BIT. ªp ƒ l -Queue Full Flag ªp ƒ l -Queue Empty Flag ªp l -Queue Full Flag ªp l -Queue Empty Flag ªp Queue size ƒ (1~13) READ COMMAND (0x4C) ªp ƒ / l -Queue Full/Empty size l COMMAND. 16BIT l r BIT. ªp ƒ l -Queue Full size ªp ƒ l -Queue Empty size ªp l -Queue Full size ªp l -Queue Empty size ªp Queue size ƒ (1~13) WRITE COMMAND (0xCC) ªp ƒ / l -Queue Full/Empty size l ƒ COMMAND. RESET» 0xD0D0 m ƒ. DATA3, DATA4 port 2 15 ~2 0 bit m 16-bit ª m ƒ. 15~12 bit ªp ƒ Queue full size l ƒ ƒ y ª r ªp ƒ l -Queue Full Flag vƒ. 11~8 bit ªp ƒ Queue empty size l ƒ ƒ y r ªp ƒ l -Queue Empty Flag vƒ. 7~4 bit ªp Queue full size l ƒ ƒ y ª r ªp l -Queue Full Flag vƒ. 3~0 bit ªp Queue empty size l ƒ ƒ y r ªp l -Queue Empty Flag vƒ. 85

92 6. COMMAND ƒr Hardware Chip User Manual Rev. 4.0 tp ƒ l -n (n=1, 2, 3) READ COMMAND ( CODE = 0x50, 0x51, 0x52 ) ¹ ƒ tp ƒ l -n (n= 1, 2, 3) p COMMAND. DATA DATA 1, DATA2, DATA3, DATA4 port 2 31 ~2 0 bit m 32-bit ª m r, 32-bit. w ˆ ˆ x ƒ x ˆ ˆ ª vƒ x p w x p ªª ª «ªª w x ƒ w x ƒ x» ˆ ªªª ª tp ƒ l -n (n=1, 2, 3) WRITE COMMAND ( CODE = 0xD0, 0xD1, 0xD2 ) t p ƒ l -n (n=1, 2, 3) ƒ COMMAND. RESET» 0x m ƒ. tp ƒ COMMA ND READ COMMANDp. x» REA D tp l -n (n =1, 2, 3) r, x» 31bit 0 r ƒ m Clear. x» READ COMMAND ˆ tp l -n (n=1, 2, 3) tp l -n (n=1, 2, 3) READ COMMANDp ˆ r m Clear. DATA1, DATA2, DATA3, DATA4 port 2 31 ~2 0 bit m 32-bit ª m r bit ƒ. w ˆ ˆ x ƒ x ˆ ˆ ª vƒ x p w x p ªª ª «ªª w x ƒ w x ƒ x» ˆ ª ªª ª 86

93 Hardware Chip User Manual Rev COMMAND ƒr tp ƒ l -Queue READ COMMAND ( CODE = 0x53 ) ¹ ƒ tp ƒ l -Queu e p COMMAND. RESET» 0x m ƒ. tp ƒ l -4 Depth 13 Queuem ƒ. tp ƒ l - Qu eue READ COMMAND ˆ ˆ 0 ( r l ). DATA DATA1, DATA2, DATA3, DATA4 port 2 31 ~2 0 bit m 32-bit ª m r, 32-bit. w ˆ ˆ ˆ ˆ ª vƒ x p w x p ª ª ª «ªª w x ƒ w x ƒ x» ˆ ªªª ª x ƒ x tp ƒ l -Queue WRITE COMMAND ( CODE = 0xD3 ) tp ƒ l - Queue ƒ COMMAND. RESET» 0x m ƒ. DATA1, DATA 2, DATA3, DATA4 port 2 31 ~2 0 bit m 32-bit ª m ƒ r bit ƒ. w ˆ ˆ x p w x p ª ª ª «ªª w x ƒ w x ƒ x» ˆ ªªª ª x ƒ x tp ƒ l -Queue Depth 13 Queue(FIFO)m ƒ. 13 Ÿ tp ˆ. x» READ COMMAND tp l -Que ue. tp l -Queue READ 87

94 6. COMMAND ƒr Hardware Chip User Manual Rev. 4.0 e Ž ƒ m Queue Clear. tp l n (n=1, 2, 3) READ COMMAND ( CODE = 0x54, 0x55, 0x56 ) t p l n (n=1, 2, 3) p COMMAND. tp l n ( n=1, 2, 3) tp ƒ l n (n=1, 2, 3) ƒ ƒ CO MMAND(READ COMMAND) ˆ ˆ READ l. e m ˆ y caption data flag(0x5b, 6~4 bit)p º. DATA DATA1, DATA2, D ATA3, DATA4 port 2 31 ~2 0 bit m 32-bit ª m r, tp ƒ rl ˆ». l r, w Read r caption data flag m 0. tp l -Queue READ COMMAND ( CODE = 0x57 ) ƒ tp eue ¹ l -Qu p COMMAND. t p l -Queue tp ƒ l -Queue ƒ ƒ COMMAND (READ COMMAND) ˆ ˆ READ l. DATA DATA1, DA TA2, DATA3, DATA4 port 2 31 ~2 0 bit m 32-bit ª m r, tp ƒ rl ˆ». l r, w Read r queue 0 m r 1. tp ƒ / l -Queue CLEAR COMMAND ( CODE = 0xD8 ) tp ƒ / l -Queue sd p º COMMAND. ˆ» Queu e Clear 0 m º. tp ƒ Queue READ COMMAND ( CODE = 0x59 ) ¹ tp ƒ l -Queue ( ) 3 0 COMMAND. DATA DATA4 prot 2~2 bitm 4-bit ª m. tp Queue READ COMMAND ( CODE = 0x5A ) ¹ tp l -Queue ( ) 3 0 COMMA ND. DATA DATA4 prot 2~2 bitm 4-bit ª m. tp Queue Full/Empty Flag READ COMMAND ( CODE = 0x5B ) tp ƒ / l -Queue Full/Empty Flag l v tp ƒ l -1,2,3 rl m tp l l e vƒ flagp COMMAND. 7 BIT l r BIT. 88

95 Hardware Chip User Manual Rev COMMAND ƒr tp l TZkh {hm ˆŽ tp l TYkh{h m ˆŽ tp l TXkh{h m ˆŽ tp ƒ l TxœŒœŒmœ m ˆŽ tp ƒ l TxœŒœŒl m ˆŽ tp l TxœŒœŒmœ m ˆŽ tp l TxœŒœŒl m ˆŽ tp Queue size ƒ (1~13) READ COMMAND (0x5C) tp ƒ / l -Queue Full/Empty size l COMMAND. 16BIT l r BIT. tp ƒ l -Queue Full size tp ƒ l -Queue Empty size tp l -Queue Full size tp l -Queue Empty size tp Queue size ƒ (1~13) WRITE COMMAND (0xDC) tp ƒ / l -Queue Full/Empty size l ƒ COMMAND. RESET» 0xD0D0 m ƒ. DATA3, DATA4 port 2 15 ~2 0 bit m 16-bit ª m ƒ. 15~12 bit tp ƒ Queue full size l ƒ ƒ y ª r tp ƒ l -Queue Full Flag vƒ. 11~8 bit tp ƒ Queue empty size l ƒ ƒ y r tp ƒ l -Queue Empty Flag vƒ. 7~4 bit tp Queue full size l ƒ ƒ y ª r tp l -Queue Full Flag vƒ. 3~0 bit tp Queue empty size l ƒ ƒ y r tp l -Queue Empty Flag vƒ. * ªp v tp x x x ƒ 0x00 dk { n 0x01 ² dk { ˆ 0x02 ² dk { n 0x03 dk { ˆ 0x04 89

96 6. COMMAND ƒr Hardware Chip User Manual Rev. 4.0 x x ƒ dk { n 0x05 ˆ¹ -1 dk { ˆ 0x06 ˆ¹ -1 dk { n 0x07 ˆ¹ -2 dk { ˆ 0x08 ˆ¹ -2 dk { n 0x09 dk { ˆ 0x0A dk { n 0x0B 0x0C d 0x0D 0x0E z > z 0x0F z = z 0x10 z < z 0x11 z > z 0x12 z = z 0x13 z < z 0x14 z² > z² 0x15 z² = z² 0x16 z² < z² 0x17 ¹ > ¹ 0x18 ¹ = ¹ 0x19 ¹ < ¹ 0x1A ¹ > Rate Change Point 1-2 0x1B ¹ = Rate Change Point 1-2 ¹ < Rate Change Point 1-2 ¹ > Rate Change Point 2-3 ¹ = Rate Change Point 2-3 ¹ < Rate Change Point 2-3 0x1C 0x1D 0x1E 0x1F 0x20 ¹ = s 0x21 ¹ = ˆ 0x22 0x23 0x24 + Emergency Limit ˆ¹ l 0x25 - Emergency Limit ˆ¹ l 0x26 90

97 Hardware Chip User Manual Rev COMMAND ƒr x + Slow Down Limit ˆ¹ l 0x27 - Slow Down Limit ˆ¹ l 0x28 «l vƒ 0x29 ƒ l vƒ 0x2A Alarm ˆ¹ l 0x2B rl ˆ 0x2C rl ˆ 0x2D ˆ¹ l 0x2E ˆ¹ l 0x2F Emergency Limit ˆ¹ l 0x30 Slow Down Limit ˆ¹ l 0x31 Inposition ˆ¹ l 0x32 IN0 High ˆ¹ l 0x33 IN0 Low ˆ¹ l 0x34 IN1 High ˆ¹ l 0x35 IN1 Low ˆ¹ l 0x36 IN2 High ˆ¹ l 0x37 IN2 Low ˆ¹ l 0x38 IN3 High ˆ¹ l 0x39 IN3 Low ˆ¹ l 0x3A OUT 0 High ˆ¹ l 0x3B OUT 0 Low ˆ¹ l 0x3C OUT1 High ˆ¹ l 0x3D OUT1 Low ˆ¹ l 0x3E OUT2 High ˆ¹ l 0x3F OUT2 Low ˆ¹ l 0x40 OUT3 High ˆ¹ l 0x41 OUT3 Low ˆ¹ l 0x42 Sensor Positioning drive I ˆ Sensor Positioning drive I n Sensor Positioning drive II ˆ 0x43 0x44 0x45 Sensor Positioning driv e II n 0x46 Sensor Positioning drive III ˆ 0x47 Sensor Positioning drive III n 0x48 x ƒ 91

98 6. COMMAND ƒr Hardware Chip User Manual Rev. 4.0 x 1 st counter N-data count clear 2 nd counter N-data count clear Mark# signal high 0x49 0x4A 0x4B x ƒ Mark# signal low 0x4C EUIO0 High ˆ¹ l/ l EUIO0 Low ˆ¹ l/ l EUO1 High ˆ¹ l EUO1 Low ˆ¹ l EUO2 High ˆ¹ l EUO2 Low ˆ¹ l EUO3 High ˆ¹ l EUO3 Low ˆ¹ l EUO4 High ˆ¹ l EUO4 Low ˆ¹ l 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 + Software LIMIT 0X57 - Software LIMIT 0X58 Software LIMIT TRIER ENABLE INTERRUPT ENERATED BY ANY SOURCE 0X59 0X5A 0X5B INTERRUPT ENERATED BY COMMAND F9 0X5C PRES ET ˆ 0X5D dk { busy High dk { busy Low t (QUEUE COMMAND ) 0x5E 0x5F 0XFF INTERNAL COUNTER DATA READ COMMAND ( CODE = 0x60 ) ¹ ƒ z p COMMAND DATA DATA1, DATA2, DATA3, DATA4 port 2 ~2 bit m 32-bit ª m. p mz ¹ ² g pp. 2 y ¹ˆ. INTERNAL COUNTER DATA WRITE COMMAND ( CODE = 0xE0 ) z ƒ COMMAND. DATA1, DATA2, DATA3, DATA4 port ƒ 32- bit ª m z ƒ. ƒ ˆ m z ² l ˆ /. RESET» 0x

99 Hardware Chip User Manual Rev COMMAND ƒr 2 y ¹ˆ mƒ ƒ x 2,147,483,648 ~ 2,147,483,647 ( 0x ~ 0x7FFFFFFF ). s p º ˆ«² l ˆ ( CW w m dk { ˆ ) ( + ) m, º ˆ«² l ˆ ( CCW w m dk { ˆ ) ( - ) m. INTERNAL COUNTER COMPARATE DATA READ COMMAND ( CODE = 0x61 ) ¹ ƒ z COMMAND. DATA DATA1, DATA2, DATA3, DATA4 port 2 31 ~2 0 bit m 32-bit ª m. z e. z ( ICL, ICE, IC ) v drive status l read(0x76)p Ž. 2 y ¹ˆ. INTERNAL COUNTER COMPARATE DATA WRITE COMMAND ( CODE = 0xE1 ) z ˆ z ƒ COMMAND. DATA1, DATA2, DATA3, DATA4 port ƒ 32-bit ª m ƒ. RESET» 0x y ¹ˆ mƒ ƒ x 2,147,483,648 ~ 2,147,483,647 ( 0x ~ 0x7FFFFFFF ). ¹ ƒ z Scale p C INTERNAL COUNTER PRE-SCALE DATA READ COMMAND ( CODE = 0x62 ) DATA4 port 2 7 ~2 0 bit m 8-bit ª m. OMMAND. DATA INTERNAL COUNTER PRE-SCALE DATA WRITE COMMAND ( CODE = 0xE2 ) z Scale ƒ p COMMAND. DA TA4 port ƒ 8- bit ª m ƒ. RESET» 0x00. CW w m ƒ w p«² l ˆ z +1. v w 1. ƒ z w p p x z z m. p d s 10,000² 1vª l ˆ¹m v z 10,000 e, z 2,500. m k ƒ z *4 Ž. z Scale p 4m ƒ ˆ«z 10,000 e z m 10,000 et m k ƒ f m r. INTERNAL COUNTER P-DATA READ COMMAND ( CODE = 0x63 ) 93

100 6. COMMAND ƒr Hardware Chip User Manual Rev. 4.0 ¹ ƒ z (P_DATA)p COMMAND. DATA DATA1, DATA2, DATA3, DATA4 port 2 31 ~2 0 bit m 32-bit ª m. INTERNAL COUNTER P-DATA WRITE COMMAND ( CODE = 0xE3 ) z (P_DATA)p ƒ COMMAND. DATA1, DATA2, DATA3, DATA4 port ƒ 32-bit ª m ƒ. RESET» 0x7FFFFFFF. EXTERNAL COUNTER DATA READ COMMAND ( CODE = 0x64 ) ¹ ƒ z p COMMAND. DATA DATA1, DATA2, DATA3, DA TA4 port 2 31 ~2 0 bit m 32-bit ª m. p mz ¹ ² g pp. 2 y ¹ˆ. EXTERNAL COUNTER DATA WRITE COMMAND ( CODE = 0xE4 ) z ƒ COMMAND. DATA1, DATA2, DATA3, DATA4 port ƒ 32- bit ª m z ƒ. RESET» 0x MODE 2 l z l x ˆ z x MODE 2 l 7, 6 BIT ( z l ) x ˆ z ˆ ƒ. ƒ ˆ m z ² l ˆ /. 2 y ¹ˆ mƒ ƒ x 2,147,483,648 ~ 2,147,483,647 ( 0x ~ 0x7FFFFFFF ). s p º ˆ«² l ˆ ( CW w m dk { ˆ ) ( + ) m, º ˆ«² l ˆ ( CCW w m dk { ˆ ) ( - ) m. EXTERNAL COUNTER COMPARATE DATA READ COMMAND ( CODE = 0x65 ) ¹ ƒ z COMMAND. DATA DATA1, DATA2, DATA3, DA TA4 port 2 31 ~2 0 bit m 32-bit ª m. z e. z ( ECL, ECE, EC )v drive status l read(0x73)p Ž. 2 y ¹ˆ. EXTERNAL COUNTER COMPARATE DATA WRITE COMMAND ( CODE = 0xE5 ) z ˆ z ƒ COMMAND. DA TA1, DATA 2, DATA3, DATA4 port ƒ 32-bit ª m ƒ. RESET» 0x r 2 y ¹ˆ mƒ ƒ x 2,147,483, 648 ~ 2,147,483,647 ( 0 x ~ 0x7FFFFFFF ). 94

101 Hardware Chip User Manual Rev COMMAND ƒr EXTERNAL COUNTER PRE-SCALE DATA READ COMMAND ( CODE = 0x66 ) ¹ ƒ z Scale p COMMAND. DATA DATA1, DATA2, DATA3, DATA4 port 2 31 ~2 0 bit m 32-bit ª m. EXTERNAL COUNTER PRE-SCALE DATA WRITE COMMAND ( CODE = 0xE6 ) z Scale ƒ p COMMAND. DATA4 port ƒ 8- bit ª m ƒ r RESET» 0x00. CW w m ƒ w p«² l ˆ z +1. v w 1. ƒ z w p p x z z m. p d s 2,500² 1vª l 4 w ˆ¹m v z e, z 10,000. m k ƒ z *4 Ž. z Scale p 4m ƒ ˆ«z 10,000 e z m 10,000 et m k ƒ f m r. EXTERNAL COUNTER P-DATA READ COMMAND ( CODE = 0x67 ) ¹ ƒ z (P_DATA)p COMMAND. DATA DATA1, DATA 2, DATA3, DATA4 port 2 31 ~2 0 bit m 32-bit ª m. EXTERNAL COUNTER N-COUNT DATA WRITE COMMAND ( CODE = 0xE7 ) z (P_DATA)p ƒ COMMAND. DATA1, DATA2, DATA3, DATA4 port ƒ 32-bit ª m ƒ. RESET» 0x7FFFFFFF. EXTERNAL SPEED DATA READ COMMAND ( CODE = 0x68 ) ¹ l ƒ l ² p COMMAND. DATA DATA1, DATA2, DATA3, DATA4 port 2 31 ~2 0 bit m 32-bit ª m r }k l ² ( 50 % duty ² l ) V*T clk sec. T clk CAMC-FS l ªl ˆ. [pps] p r. ˆ¹ dk { l ˆ¹. dk { n ˆ overflow vƒ dk { ˆ l. ƒ ˆ, wsd ekƒ ˆ Ž. EXTERNAL SPEED COMPARATE DATA READ COMMAND ( CODE = 0x69 ) 95

102 6. COMMAND ƒr Hardware Chip User Manual Rev. 4.0 ¹ ƒ z ² p COMMAND. DATA DATA1, DATA2, DATA3, DATA4 port 2 31 ~2 0 bit m 32-bit ª m. EXTERNAL SPEED COMPARATE DATA WRITE COMMAND ( CODE = 0xE9 ) z l ² p ƒ COMMAND. DATA1, DATA2, DATA3, DATA4 port ƒ 32-b it ª m ƒ. RESET» 0x z ƒ ³ ƒ DATA READ COMMAND ( CODE = 0x6A ) ƒ z ƒ ³ p COMMAND. DATA DATA4 port 2 7 ~2 0 bit m 8-bit ª m. z ƒ ˆ¹ ˆ¹ Active Level [ƒ * T clk ( l ªl )] e z m ƒ ˆ¹ xºp ˆ. 0 z ƒˆ¹ z ƒ delay ˆ v r, T clk ( l ªl ) v. z ƒ ³ ƒ DATA WRITE COMMAND ( CODE = 0xEA ) z ƒ ³ ƒ COMMAND. DATA4 port 2 7 ~2 0 bit m 8-bit ª m ƒ. ( ƒ * T clk ) ˆ Active Level ƒ ˆ¹ º. ekƒ ƒ ˆ¹ ekƒ l ˆ¹ p Software m. RESET» 0x05m ƒ. ƒ ³ v z ˆ¹. (ESTOP, SSTOP, PELM, NELM, PSLM, NSLM, ALM, INP, SYNC, MONI, MARK, 8_16SEL, IN0, IN1, IN2, I N3, EUIO0) ) Signal sea rch driv e I, II v Sensor positioning drive I, II, III ƒ ˆ¹d MARK lˆ¹ t ƒ l ƒ rl(0xf0, 11 bit) m ƒ. OFF-RANE DATA READ COMMAND ( CODE = 0x6B ) «DATAp COMMAND. DATA DATA4 port 2 7 ~2 0 bit m 8-bit ª m. OFF-RANE DATA WRITE COMMAND ( CODE = 0xEB ) «DATAp ƒ COMMAND. DATA4 port 2 7 ~2 0 bit m 8-bit ª m ƒ r, RESET» 0x00. «DATA z z Ÿ v r z z Ÿ ƒ «DATAy ª dk {, g p, z z Ÿ ƒ «DATAy 96

103 Hardware Chip User Manual Rev COMMAND ƒr m ˆ ƒ Ž dk {p. z/ z «dk { END STATUS l 8bit 1(high). ƒ 0x00 m ƒ r «Ž. ) «/ ƒ : ƒ l 7bit( 0 :, 1 : ) DEVIATION DA TA READ COMMAND ( CODE = 0x6C ) ( z z ) ³Ÿk p 15 COMMAND. DATA DATA3, DATA4 port 2 ~2 0 bit m 16-bit ª m. ( z z ) 15-bit ª ³Ÿk ( 14 bit ~ 0 bit ) z¹(15 bit)m ƒ., ³Ÿk ª 32,767 ˆnƒ um. PM REISTER CHANE DATA READ COMMAND ( CODE = 0x6D ) ¹ ² ƒ ±kv l wª COMMAND. DATA DATA4 port 2 0 bitm 1-bit ª m. 0 PM-1 Register ƒ ±kv p ² l ˆ, 1 PM-Update Register ƒ ±kv p ² l ˆ. PM REISTER CHANE DATA WRITE COMMAND ( CODE = 0xED ) ² l ±kv p l wª ƒ COMMAND. RESET» 0x0p. l wª 0 m ƒ PM-1 Register ƒ ±k v p ² l r, 1m ƒ PM-Update Register ƒ ±kv p ² l. dk { Register ƒ x ² l l x vƒ um. COMPARE REISTER INPUT CHANE READ COMMAND ( CODE = 0x6E ) CAMC-FS y z/ z 2. z p 1 st, z p 2 ndk e ld x. p d r, COMPARE REISTER INPUT CHANE 0x1m ƒ r z y p. rl 0x6Ep Comparator register l ƒ p. ƒ 2-bit ª r, ƒ. 00 : 1 st : Internal count, 2 nd : External count( y ) 01 : 1 st : Internal count, 2 nd : Internal count( z ƒ ) 10 : 1 st : External count, 2 nd : External count( z ƒ ) 97

104 6. COMMAND ƒr Hardware Chip User Manual Rev. 4.0 COMPARE REISTER INPUT CHANE WRITE COMMAND ( CODE = 0xEE ) Comparator register l ƒ e r, ƒ. 00 : 1 st : Internal count, 2 nd : External count 01 : 1 st : Internal count, 2 nd : Internal count 10 : 1 st : External count, 2 nd : External count COMMAND. ƒ 2-bit ª ƒ DATA READ COMMAND ( CODE = 0x70 ) CAMC -FS ˆ ƒ p COMMAND. 13- bit ª p r bit ƒ ƒ DATA WRITE COMMAND ( CODE = 0xF0 ). ƒ DATA WRITE COMMAND ( CODE = 0xF0 ) CAMC -FS ˆ ƒ COMMAND. ƒ ª 13-bit r r l m Inpositi on sd, Alarm z, ² l n ˆ l ˆ¹ l z, Limit / z ˆ ƒ d. RESET» 0x0C3 Em ƒ r, ƒ. 12bit 11bit 10bit S profile ƒ (0: Ž, 1 : ) (0) Search source filter ƒ (0: Ž, 1 : ) (1) Sync ƒ (0: Ž, 1 : ) (1) 9bit Limit (0: Ž, 1 : ) (0) 8bit Inposition º sd(0: Ž, 1 : ) (0) 7bit «/ ƒ (0:, 1 : ) (0) 6bit ƒ (0 : ƒ, 1: ƒ d ) (0) 5bit +-Slowdown limit sensor ƒ (0: Ž, 1 : ) (1) 4bit +-Emergency limit sensor ƒ (0: Ž, 1 : ) (1) 3bit ESTOP, SSTOP signal ƒ (0: Ž, 1 : ) (1) 2bit Don t care (1) 1bit Alarm stop ƒ (0: Ž, 1 : ) (1) 0bit Inpositoin ƒ (0: Ž, 1 : ) (0) MODE 1 DATA READ COMMAND ( CODE = 0x71 ) ƒ MODE 1 l COMMAND. 8-bit ª r, ƒ. 7 bit ˆ ³ wˆ 98

105 Hardware Chip User Manual Rev COMMAND ƒr 0 : wˆ 1 : r wˆ 6 bit ~ 4 bit ² l wˆ ( 6.2. ) 3 bit ~ 0 bit ˆ¹ ƒ ( 6.3. ) * ² lwˆ MODE1 Register ƒ ep CAMC-FS ² l wˆ Žk d e w ˆ¹(DIR) D6 D5 D4 CW CCW ² ˆ¹ ( PULSE ) w ˆ L H Active H Pulse H L L H Active L Pulse H L Active H Active H CW Pulse CCW Pulse Active L Active L Active H Active H CCW Pulse CW Pulse Active L Active L 1 Pulse wˆ 2 Pulse wˆ * ˆ¹ ƒ MODE1 Register ƒ ƒ ˆ¹ dk { ˆ ˆ¹ Žk e r D3 D2 D1 D0 ˆ¹ v Edge ELM ˆ¹ Negative Edge ELM ˆ¹ Negative Edge SLM ˆ¹ Negative Edge SLM ˆ¹ Negative Edge IN0 ˆ¹ Edge IN1 ˆ¹ Edge IN2 ˆ¹ Edge IN3 ˆ¹ Edge ELM ˆ¹ Positive Edge ELM ˆ¹ Positive Edge SLM ˆ¹ Positive Edge SLM ˆ¹ Positive Edge IN0 ˆ¹ Edge 99

106 6. COMMAND ƒr Hardware Chip User Manual Rev. 4.0 D3 D2 D1 D0 ˆ¹ v Edge IN1 ˆ¹ Edge IN2 ˆ¹ Edge IN3 ˆ¹ Edge ) ˆ¹ +-ELM/SLM ˆ¹ edge active level m. +ELMˆ¹ active level 0 ˆ¹ +ELM ˆ¹ Positive Edge r ˆ¹ dk { z ˆ¹ PELM 1 ƒ 0 m ep. MO DE 1 DATA WRITE COMMAND ( CODE = 0xF1 ) MODE 1 ƒ ª 8-bit r rl m ² dk { ƒ ˆ ³ wˆ, ² l wˆ, ˆ¹ dk { ˆ¹ ƒ. RESET» y 0x00 m ƒ r, ƒ. 7 bit ˆ ³ wˆ 0 : wˆ 1 : r wˆ 6 bit ~ 4 bit ² l wˆ ( 6.2. ) 3 bit ~ 0 bit ˆ¹ ƒ ( 6.3. ) ) ˆ¹ +-E edge active level m. +ELMˆ¹ active level LOW ˆ¹ ƒ +ELM ˆ¹ Positive Edge r ˆ¹ dk { z ˆ¹ PELM 1 ƒ 0 m ep n. LM/SLM ˆ¹ MODE 2 DATA READ COMMAND ( CODE = 0x72 ) ƒ MODE 2 l COMMAND. 11-bit ª r, ƒ MODE 2 DATA WRITE COMMAND ( CODE = 0xF2 ). MODE 2 DATA WRITE COMMAND ( CODE = 0xF2 ) ƒ MODE 2 l ƒ COMMAND. ƒ 11-bit ª r, RESET» 0x000 m ƒ r, ƒ. 100

107 Hardware Chip User Manual Rev COMMAND ƒr «ˆ¹ ƒ ª l ƒ ª ªª ˆ¹ ƒ «ª ª ˆ¹ «ª l ª l ªªª ˆ¹ «ª«ª «ª ƒ ªª ˆ¹ «ª«ª «ª ƒ «ªª ˆ¹ «ª«ª «ª ƒ «ªª ˆ¹ «ª«ª «ª ƒ ªª ˆ¹ «ª«ª «ª ƒ ªª ˆ¹ «ª«ª «ª ƒ 0 Active Level High ˆ¹ ƒ, 1 Active Level Low ˆ¹ ƒ. z l ( Mode2 l ƒ ƒ ) 7 bi t 6 bit l ECUP ˆ¹ ECDN ˆ¹ 0 0 UP/DOWN ˆ¹ l UP l DOWN l ˆ¹ 1 w l φ A l φ B l ˆ¹ 2 w l φ A l φ B l ˆ¹ 4 w l φ A l φ B l UNIVERSAL SINAL READ COMMAND ( CODE = 0x73 ) ¹ ƒ x l ˆ¹ Level COMMAND. 11-bit ª r, 4~7 bit x l Level «r, r x l Level «. ƒ. «««ª««m l ªª«¹ «ª««v ª «¹ «ª««l ªª «¹ «ª««l «ªª «¹ «ª««««UNIVERSAL SINAL WRITE COMMAND ( CODE = 0xF3 ) x l ˆ¹ Level ƒ COMMAND. 11-bit ª r RESET» 0x000 m ƒ r 4~7 bit x l Level «r, r x l Level «. 4~7 bit z l ˆ¹ um rl m ˆ z ˆ¹ m x. 101

108 6. COMMAND ƒr Hardware Chip User Manual Rev. 4.0 «««ª««m l ªª«¹ «ª««v ª «¹ «ª««l ªª «¹ «ª««l «ªª «¹ «ª«««COMMAND ƒ 3bitm sdp ƒ r output register write. byte write 1byte(4bit)p universal. NOT universal output register ƒ 1 m ƒ bit NOT 0 m ƒ bit m. p d 0x6p universal output register NOT sdm 0x2p r 0x9. AND universal output r egister l m data bitx AND. p d, 0x7 universal output register NOT sdm 0x2p r 0x4. OR universal output register l m data bitx OR. p d, 0x 2 universal output register OR sdm 0x5p r 0x7. XOR universal output regist er l m data bitx XOR. p d, 0x02 universal output register XOR sdm 0x7p r 0x5. END STATUS READ COMMAND ( CODE = 0x74 ) END STATUS l dk { n ˆ n READ 14-bit l. rl ˆ END STATUS l p m n ±Ž. ƒ n» ( BUSY = Low ) dk { ˆ. 14bit Limit( PELM, N ELM, PS LM, NSLM, Software limit) n 13bit Limit n 12bit Sensor position ing dk { n 11bit Preset pulse dk { n 10bit ˆ¹ (Signal search-1/2) dp { n 9bit (Original search) dp { n 8bit «dk { n 7bit ƒ l dk { n 6bit Ala rm ˆ¹ dk { n 5bit rl(0xac) dk { n 102

109 Hardware Chip User Manual Rev COMMAND ƒr 4bit rl(0xab) dk { n 3bit ESTOP ˆ¹ dk { n 2bit SSTOP ˆ¹ dk { n 1bit Emergency limit(pelm, NELM, Software emergency limit) dk { n 0bit Slowdown limit(pslm, NSLM, Software slowdown limit) dk { n MECHANICAL SINAL READ COMMAND ( CODE = 0x75 ) ¹ l z l ˆ¹, s dk w l ˆ¹, Limit l ˆ¹ Level READ COMMAND. 13-bit r. ««ªª ˆ¹ l «««ªª ˆ¹ l ª ªª ˆ¹ l «ªª ˆ¹ l «ªª ˆ¹ l «ª ˆ¹ l ª ˆ¹ ª«ª ˆ¹ l ª ˆ¹ ªªªª«ª«ªªª ˆ¹ l ª ªª ˆ¹ l ª ˆ¹ l ª ˆ¹ l ª ˆ¹ l ª ˆ¹ l DRIVE STATUS DATA READ COMMAND ( CODE = 0x76 ) ¹ z z v p Ž COMMAND. 9-bit m r ƒ Žk. dk { w ˆ¹ ««z z ª z z ª z z ª ª z z «ª ªª««d ª«ª «««dk { 103

110 6. COMMAND ƒr Hardware Chip User Manual Rev. 4.0 EXTERNAL COUNTER ƒ DATA READ COMMAND ( CODE = 0x77 ) z ƒ READ COMMAND. 8-bit m r ƒ. ½ 8bit read m z ƒ l clear r set, 0xF7 command p ˆ ˆ r reset. 8bit External count clear flag 7bit 0 : Not reverse count, 1: Reverse count 6bit Don t care 5~4bit 3~0bit 00 : Clear request reset 01 : One time clear request set 10 : Full time clear request set 11 : External count clear set Clear signal input selection 0000 : IN : IN : IN : IN3 Others : Don t care EXTERNAL COUNTER ƒ DATA WRITE COMMAND ( CODE = 0xF7 ) z ƒ WRITE COMMAND. R ESET» 0x00 r, ƒ. 7bit 0 : Not reverse count, 1: Reverse count 6bit Don t care 5~4bit 00 : Clear request reset 01 : One time clear request set 10 : Full time clear request set 11 : External count clear set 3~0bit Clear signal input selection 0000 : IN : IN : IN : IN3 Others : Don t care 104

111 Hardware Chip User Manual Rev COMMAND ƒr 7 bit 1m ƒ z w m. 5~4 bit ƒ ƒ s One Time Clear Request Set m ƒ CLEAR ˆ¹ l r w z Clear Clear Request Reset m x. Full Time Clear Request Set m ƒ z Clear l ˆ¹ High l e p z Clear. External Counter Clear Set ƒ z 0 m ƒ. 4-bit ƒ ƒ Clear ˆ¹ l ƒ s. REISTER CLEAR(INITIALIZATION) COMMAND ( CODE = 0xF8 ) z sd l º COMMAND. Software reset r z RESET º. COMMAND ˆ» 32*T clk ˆ» z l º. * T clk : l ± Interrupt FLA READ COMMAND (CODE =0x79) l k p READ COMMAND. 32BIT l r BIT r READˆ l k ªp. INTERRUPT FLA READ COMMAND OWap Œ œ ˆŠ ˆ Œ SXap Œ œ ˆŠ ˆ Œ P 31bit Selectable Interrupt source3( FE 31~24bit) 30bit Selectable Interrupt source2( FE 23~16bit) 29bit Selectable Interrupt source1( FE 15~8bit) 28bit Selectable Interrupt source0( FE 7~0bit) 27bit Emergency limit ˆ¹ lˆ 26bit Slow down limit ˆ¹ lˆ 25bit queue rl ˆ(30 bit 1 e) 24bit ªp queue rl ˆ(30 bit 1 e) 23bit 1 st counter M_DATA e 22bit ¹ = ¹ 21bit ¹ = RCP12 20bit ¹ = RCP23 19bit MODE1 register ƒ ˆ¹ ˆ 18bit 17bit d 16bit 105

112 6. COMMAND ƒr Hardware Chip User Manual Rev bit Interrupt command ƒƒ 14bit -3 command ˆ e 13bit -2 command ˆ e 12bit -1 command ˆ e 11bit ªp -3 command ˆ e 10bit ªp -2 command ˆ e 9bit ªp -1 command ˆ e 8bit ƒ queue full e 7bit ªp data queue empty e 6bit External counter < External comparator e 5bit External counter = External comparator e 4bit External counter > External comparator e 3bit Internal counter < Internal comparator e 2bit Internal counter = Internal comparator e 1bit Internal counter > Internal comparator e 0bit dk { n P jhtjtmz Œ œ ˆŽ ZY vƒ Œ œ ˆ S» ˆŽ Œˆ Š ˆ U dk { n Œ œ ˆŽ WŸWWWWWWWX r» p Œ œ vƒ p k Œ œ ˆŽ Œˆ Š ˆ WŸWWWWWWWXm U Interrupt vƒ WRITE COMMAND (CODE =0xF9) Interrupt vƒ ƒ COMMAND. Interrupt MASK READ COMMAND (CODE =0x7A) l p ªp READ COMMAND. RESET» y 1(0x ). 32BIT l r BIT Interrupt MASK WRITE COMMAND (CODE =0xFA). Interrupt MASK WRITE COMMAND (CODE =0xFA) l p ªp ƒ COMMAND. dk { n ƒ l p p ª Ž. 32 BIT l r BIT. Interrupt MASK(0 : Interrupt Disable, 1 : Enable) 31bit Selectable Interrupt source3( FE 31~24bit) 30bit Selectable Interrupt source2( FE 23~16bit) 29bit Selectable Interrupt source1( FE 15~8bit) 106

113 Hardware Chip User Manual Rev COMMAND ƒr 28bit Selectable Interrupt source0( FE 7~0bit) 27bit Emergency limit ˆ¹ lˆ 26bit Slow down limit ˆ¹ lˆ 25bit queue rl ˆ(30 bit 1 e) 24bit ªp queue rl ˆ(30 bit 1 e) 23bit 1 st counter M_DATA e 22bit ¹ = ¹ 21bit ¹ = RCP12 20bit ¹ = RCP23 19bit MODE1 register ƒ ˆ¹ ˆ 18bit 17bit d 16bit 15bit Don t care 14bit -3 command ˆ e 13bit -2 command ˆ e 12bit -1 command ˆ e 11bit ªp -3 command ˆ e 10bit ªp -2 command ˆ e 9bit ªp -1 command ˆ e 8bit ƒ queue full e 7bit ªp data queue empty e 6bit External counter < External comparator e 5bit External counter = External comparator e 4bit External counter > External comparator e 3bit Internal counter < Internal comparator e 2bit Internal counter = Internal comparator e 1bit Internal counter > Internal comparator e 0bit dk { n EMODE1 DATA READ COMMAND (CODE =0x7B) º Universal I/O, Monitorˆ¹ z v l COMMAND. DATA DATA4 port 2 7 ~2 0 bit m 8-bit ª m. 107

114 6. COMMAND ƒr Hardware Chip User Manual Rev. 4.0 ««««ª «ªª «ª «ª «ª «ª «ªª EMODE1 DATA WRITE COMMAND (CODE =0xFB) º Universal I/O, Monitorˆ¹ z v l ƒ COMMAND. RESET» 0x00 r, DATA4 port ƒ 8-bit ª m ƒ. ««««ª «ªª «ª «ª «ª «ª «ªª EXTENSION UNIVERSAL OUT READ COMMAND (CODE =0x7C) ¹ ƒ º l ˆ¹ Level COMMAND. 8-bit ª r, 0~4 bit º l ˆ¹ Level «r, 5~7 bit lˆ¹ «. «««ª««m l ªª«¹ «ª««v ª «¹ «ª««l ªª «¹ «ª««l «ªª «¹ «ª«««tˆ EXTENSION UNIVERSAL OUT WRITE COMMAND (CODE =0xFC) º l ˆ¹ Level ƒ COMMAND. EMODE1 ƒ direction input, zp disablem ƒ bit ƒ v. RESET» 0x000 m ƒ r, 8-bit ª r 0~4 bit º lˆ¹ Level «r, 5~7 bit sdp ƒ.. sd EMODE1 0x9Fm ƒ e. 108

115 Hardware Chip User Manual Rev COMMAND ƒr NOT ¹ universal output register v. p d 0x06p universal output register NOT sdp r 0x19. AND universal output register l m data bitx AND. p d, 0x17 universal output register AND sdm 0x2p r 0x02. OR universal output register l m data bitx OR. p d, 0x02 universal output register OR sdm 0x15p r 0x17. XOR universal output register l m data bitx XOR. p d, 0x12 universal output register XOR sdm 0x07p r 0x15. «««ª««m l ªª«¹ «ª««v ª «¹ «ª««l ªª «¹ «ª««l «ªª «¹ «ª«««tˆ USER INTERRUPT SOURCE SELECTION REISTER READ COMMAND (CODE =0x7E) Interrupt sourcep ƒ p COMMAND. ƒ Interrupt source ªp / x p. «ªp tp x p «ªp tp x p «ªp tp x p «ªp tp x p USER INTERRUPT SOURCE SELECTION REISTER WRITE COMMAND (CODE =0xFE) Interrupt sourcep ƒ COMMAND. RESET» 0x m ƒ r, ƒ Interrupt source ªp / x p. «ªp tp x p «ªp tp x p «ªp tp x p «ªp tp x p 109

116 6. COMMAND ƒr Hardware Chip User Manual Rev COMMAND 실행방법 CAMC-FS COM MAND ˆ p y. COMMAND DATA COMMAND, DATA COMMAND, DAT A / p v COMMAND, DATA / p v Ž COMMAND ƒ COM AND WRITE PORT COMMAND CODE p. 2-BYTE DATA COMMA ND ˆ wx ˆ m Ÿ 2 BYTE DATA COMMAND ˆ wx ƒr. r 2-byte p write»( rl ˆ ) ˆ rl write 2-byte r l ˆ. Data3 Write QX \ _ ˆ ˆž Œ Data4 Write Q^ W ˆ ˆž Œ QQ ˆ ˆž Œƒ Œ COMMAND (0Xnn) write QW µ jvtthuk 3-BYTE DATA COMMAND ˆ wx ˆ m Ÿ 3 BYTE DATA COMMAND ˆ wx ƒr. r 3-byte p write»( rl ˆ ) ˆ rl write 3-byte r l ˆ. Data2 Write QYZ X] ˆ ˆ ž Œ Data3 Write QX\ _ ˆ ˆž Œ Data4 Write Q^ W ˆ ˆž Œ QQ ˆ ˆž Œƒ Œ COMMAND (0Xnn) write QW µ jvtthuk 110

117 Hardware Chip User Manual Rev COMMAND ƒr 4-BYTE DATA COMMAND ˆ wx ˆ m Ÿ 4 BYTE DATA COMMAND ˆ wx ƒr. r 4-byte p write»( rl ˆ ) ˆ rl write 4-byte r l ˆ. Data1 Write QZX Y[ ˆ ˆž Œ Data2 Write QYZ X] ˆ ˆž Œ Data3 Write QX\ _ ˆ ˆž Œ Data4 Write Q^ W ˆ ˆž Œ QQ ˆ ˆž Œƒ Œ COMMAND (0Xnn) write QW µ jvtthuk 2-BYTE DATA COMMAND ˆ wx 2-BYTE DATA COMAND ˆ wx ˆ. Read command ˆ wx ƒ Read p Read COMMANDp ˆ.» Data port p 8-bitŽ. COMMAND (0Xnn) write QW µ jvtthuk OyŒˆ jvtthukp Data4 Read Q^ W ˆ ˆ Œˆ QQ ˆ ˆ Œˆ ƒ Œ Data3 Read QX\ _ ˆ ˆ Œˆ 111

118 6. COMMAND ƒr Hardware Chip User Manual Rev BYTE DATA COMMAND ˆ wx 3-BYTE DATA COMMAND ˆ wx ˆ. COMMAND (0Xnn) write QW µ jvtthuk OyŒˆ jvtthukp Data4 Read Q^ W ˆ ˆ Œˆ QQ ˆ ˆ Œˆ ƒ Œ Data3 Read QX\ _ ˆ ˆ Œˆ Data2 Read QYZ X] ˆ ˆ Œˆ 4-BY 4 TE DATA COMMAND ˆ wx BYTE DATA COMMAND ˆ wx ˆ COMMAND (0Xnn) write QW µ jvtthuk OyŒˆ jvtthukp Data4 Read Q^ W ˆ ˆ Œˆ QQ ˆ ˆ Œˆ ƒ Œ Data3 Read QX\ _ ˆ ˆ Œˆ Data2 Read QYZ X] ˆ ˆ Œˆ Data1 Read QZX Y[ ˆ ˆ Œˆ 112

119 Hardware Chip User Manual Rev TIMIN 7. TIMIN 7.1. DATA BUS TIMIN ƒ DATA BUS READ / WRITE TIMIN «. READ TIMIN A2 ~ A0 CS* RD* D7 ~ D0 Tcr Trd Trc Tar Trr Tra Tdf WRITE TIMIN A2 ~ A0 CS* WR* D7 ~ D0 Tcw Tdw Twc Taw Tww Twa Twd 113

120 7. TIMIN Hardware Chip User Manual Rev. 4.0 DATA BUS TIMIN s ¹ MIN MAX CS* Ž ˆ ( R* ) Tcr 0 RD* Data l ˆ Trd 30 CS* ˆ ( R* ) Trc 0 Address Ž ˆ ( R* ) Tar 0 RD* Pulse ³ Trr 30 Address ˆ ( R* ) Tra 0 RD* Data Float ˆ Tdf 30 CS* Ž ˆ ( W* ) Tcw 0 Data ƒ ˆ ( W* ) Tdw 20 CS* ˆ ( W* ) Twc 0 Address Ž ˆ ( W* ) Taw 0 WR* Pulse ³ Tww 30 Address ˆ ( W* ) Twa 0 Data ˆ ( W* ) Twd 0 nsec 114

121 Hardware Chip User Manual Rev TIMIN 7.2. 입력신호 TIMIN ƒ l ˆ¹ ƒ l ³ v l p «. ICLK l TIMIN ICLK Tch Tcl Tcyc RESET* l TIMIN RESET* Trsw ESTOP, SSTOP l ESTOP, SSTOP TIMIN Tstpw +ELM, -ELM, +SLM, -SLM l TIMIN +ELM, -ELM +SLM, -SLM (ACTIVE High ) Tlmtw +ELM, -ELM +SLM, -SLM (ACTIVE Low ) Tlmtw ALM, INP l TIMIN ALM, INP (ACTIVE High ) Tdstw ALM, INP (ACTIVE Low ) Tdstw 115

122 7. TIMIN Hardware Chip User Manual Rev. 4.0 SYNC l SYNC TIMIN Tsynw ECUP, ECDN l TIMIN (2 l ˆ) ECUP ECDN Ta b Tba Ta b Tba Tab Tba Tab Tba ECUP ECDN Taa Taa Taa Tbb Tbb Tbb IN3 ~ IN0 l TIMIN (SINAL SEARCH - 1, - 2 DRIVEm ) IN3, IN2, IN1, IN0 Tinhw Tinlw 116

123 Hardware Chip User Manual Rev TIMIN l ˆ¹ TIMIN s ¹ MIN MAX ICLK l High Level ³ Tch 30 ICLK l Low Level ³ Tcl 30 ICLK l Tcyc 61 Reset l ³ Trsw 8* Tcyc ESTOP, SSTOP l ³ Tstpw Tcyc * BW(*1) +ELM, -ELM, +SLM, -SLM l ³ Tlmtw Tcyc * BW(*1) ALM, INP l ³ Tdstw Tcyc * BW(*1) SYNC l ³ Tsynw Tcyc * 5 ECUP --> ECDN HOLD ˆ (*2) Tab Tcyc * ECDN --> ECUP HOLD ˆ (*2) Tba Tcyc * ECUP --> ECUP HOLD ˆ (*3) Taa Tcyc * ECDN --> ECDN HOLD ˆ (*3) Tbb Tcyc * IN3 ~ IN0 l H LEVEL ³ Tinhw 30 IN3 ~ IN0 l L LEVEL ³ Tinlw 30 nsec * 1 : BW = ƒ ˆ¹ l ³ ƒ * 2 : 2 ˆ¹ l ˆ * 3 : 2 ˆ¹ l ˆ. 2 ˆ¹ CHATTERIN vƒ ƒ "2 ˆ¹ CHATTERIN" 출력신호 TIMIN 1 ƒ ICLK l l ˆ¹ ƒ, ICLK ƒz l ˆ «. OCLK l TIMIN ICLK OCLK Toch PULSE, PPPS l TIMIN Tocl 117

124 7. TIMIN Hardware Chip User Manual Rev. 4.0 ICLK OCLK PULSE (*4) PULSE (*5) PPPS T pon T pof Tpof Tppw *4. ACTIVE High *5. ACTIVE Low BUSY, DIR l TIMIN ICLK OCLK BUSY DIR(*6) Tdic h Tbu on Tbuof *6. 2 PULSE wˆ ˆ DIR ˆ¹ TIMIN ƒ PULSEˆ¹ TIMIN. 118

125 Hardware Chip User Manual Rev TIMIN UP, CONST, DOWN l TIMIN ICLK OCLK UP, CONST, DOWN Tds on Tdsc h Tdsof INT l TIMIN ICLK OCLK BUSY INT Tit on Titof SIN, MD12 ~ MD00 l TIMIN (MONI = H : SPEED DATA MONITOR ˆ) ICLK OCLK MD12 ~ MD00 SIN Tsich T mdon Tmdch Tdmof 119

126 7. TIMIN Hardware Chip User Manual Rev. 4.0 SIN, MD12 ~ MD00 l TIMIN (MONI = L : ³Ÿk DATA MONITOR ˆ) ICLK OCLK MD12 ~ MD00 Tmd ch Tmd ch IC, ICL, EC, ECL l TIMIN ICLK OCLK IC, ICL, EC, ECL Tcmch Tcmch 120

127 Hardware Chip User Manual Rev TIMIN ICLK l ˆ¹ TIMIN s ¹ MIN MAX ICLK ~ OCLK H l ˆ Toch 5 13 ICLK ~ OCLK L l ˆ Tocl 5 13 ICLK ~ PULSE, PPLS ON l ˆ Tpon 6 26 ICLK ~ PULSE, PPLS OFF l ˆ Tpof 6 26 PPLS l PULSE ³ Tppw Tcyc* 2-20 Tcyc*2+10 ICLK ~ DIR º ˆ Tdich ICLK ~ BUSY ON l ˆ Tbuon ICLK ~ BUSY OFF l ˆ Tbuof 8 35 ICLK ~ UP, CONST, DOWN ON l ˆ Tdson 9 20 ICLK ~ UP, CONST, DOWN OFF º ˆ Tdsch 6 20 ICLK ~ UP, CONST, DOWN OFF l ˆ Tdso 9 30 ICLK ~ INT ON l ˆ Titon ICLK ~ INT OFF l ˆ Titof 7 30 ICLK ~ SIN º ˆ Tsich ICLK ~ MD12 ~ MD00 ON l ˆ Tmdon ICLK ~ MD12 ~ MD00 º ˆ Tmdch 8 25 ICLK ~ MD12 ~ MD00 OFF l ˆ Tmdof ICLK ~ IC, ICL, EC, ECL º ˆ Tcmch 5 20 nsec 7.4. 출력신호 TIMIN 2 ƒ ˆ ƒ l ˆ¹ v l ˆ¹ p «. DRIVE ˆ TIMIN (SYNC l q Ž ˆ) W*(*7) DIR BUSY UP, CONST, DOWN PULSE PPLS *7. COMMAND WRITE PORT ˆ. SYNC l q ˆ TIMIN T1 T2 T3 T4 121

128 7. TIMIN Hardware Chip User Manual Rev. 4.0 BUSY SYNC UP, CONST, DOWN PULSE PPLS T5 T4 DRIVE n TIMIN (INP ˆ¹ º Ž ) PULSE UP, CONST, DOWN BUSY DRIVE n TIMIN (INP ˆ¹ º ) T6 T7 PULSE UP, CONST, DOWN INP(*8) BUSY *8. ACTIVE High T6 T8 122

129 Hardware Chip User Manual Rev TIMIN IC, ICL l TIMIN PULSE IC, ICL T9 T9 EC, ECL l TIMIN (2 ˆ¹ l ˆ) ECUP, ECDN (*9) EC, ECL *9. 2 ˆ¹ l ˆp «. T10 T10 MONI º TIMIN MONI SIN MD12~MD00 T11 T11 OUT3 ~ OUT0 l TIMIN W*(*10) OUT3 ~ OUT0 T12 T12 *10. UNIVERSAL SINAL WRITE PORT ˆ. 123

130 7. TIMIN Hardware Chip User Manual Rev. 4.0 ³Ÿk DATA v TIMIN (MONI = L ˆ) PPLS ECUP, ECDN (*11) MD12~MD00 T13 T14 *11. 2T ˆ¹ l ˆp «. INT l ON TIMIN BUSY INT T15 INT l OFF TIMIN W*(*13) R*(*14) INT T16 T17 *13. COMMAND WRITE PORT ƒ m DRIVE COMMANDp ˆ. *14. END STATUS READ PORTmz ˆ. 124

131 Hardware Chip User Manual Rev TIMIN RESET TIMIN RESET sd l T18 ˆ l ˆ¹ TIMIN s ¹ MIN MAX COMMAND WRITE PORT ~ DIR l ˆ T1 Tcyc Tcyc* DIR l ~ BUSY ON l ˆ T2 Tcyc - 30 Tcyc + 10 BUSY ON l ~ UP, CONST, DOWN ON l ˆ T3 Tcyc * 2-20 Tcyc* UP, CONST, DOWN ON l ~ PULSE, PPLS ON l ˆ T4 Tcyc * 4-20 SYNC ON l ~ UP, CONST, DOWN ON l ˆ T5 Tcyc - 5 Tcyc* PULSE OFF l ~ UP, CONST, DOWN OFF l ˆ T6 Tcyc - 20 Tcyc + 30 UP, CONST, DOWN OFF l ~ BUSY OFF l ˆ T7 Tcyc - 5 Tcyc* INP ON l ~ BUSY OFF l ˆ T8 Tcyc - 10 Tcyc* PPLS OFF l --> IC, ICL l ˆ T9 Tcyc - 25 Tcyc + 20 ECUP, ECDN l --> EC, ECL l ˆ (*9) T10 Tcyc*3 10 Tcyc* MONI l º ~ SIN, MD12 ~ MD00 l ˆ T UNIVERSAL SINAL WRITE PORT ~ OUT3 ~ OUT0 l ˆ T PPLS OFF l ~ SIN, MD12 ~ MD00 l ˆ T13 Tcyc * 3-25 Tcyc* ECUP, ECDN l ~ SIN, MD12 ~ MD00 l ˆ T14 Tcyc * 5-10 Tcyc* (*10) BUSY OFF l ~ INT ON l ˆ T COMMAND WRITE PORT ~ INT OFF l ˆ T16 Tcyc - 5 Tcyc* END STATUS READ PORT ~ INT OFF l ˆ T17 Tcyc - 10 Tcyc*5-45 RESET* l ~ sd l OFF l ˆ T18 1,049 nsec 125

132 8. y Hardware Chip User Manual Rev 보충사항 8.1. ICLK 입력주파수의선택 CAMC-FS SPEED ICLK l ±, ½ Žk 4 s ƒ ª v. 1) l ± ƒ, l ± v ˆ ƒ, ˆ ˆ. ( FCLK = ICLK l ± ) F FCLK = RANE DATA 4 65,536 UNIT --- l ± ƒ (Pulse/Sec) FOUT = FUNIT SPEED DATA --- l ± (Pulse/Sec) T T UNIT UNIT RATE n DATA 8 F = ` --- ˆ ƒ ( ƒ) (Sec) CLK RATE n DATA 16 F = ` --- ˆ ƒ (S-curve) (Sec) CLK T UD = T UNIT ( SPEED DATA A SPEED DATA B) --- ˆ (Sec) 2) y q ˆ Tcyc ICLK l ±. 3) DATA COMMAND ƒ, COMMAND WRITEmz DATA zm LOAD Tcyc * 8 ˆ. ekƒ COMMAND WRITE» Tcyc * 8 ˆ Ž COMMAND PORTv DATA1, 2, 3, 4 PORTm Ž 4) DATAp COMMAND ƒ, COMMAND WRITEmz DATA l BUFFER LATCH e Tcyc * 8 ˆ, ekƒ COMMAND WRITE» DATA1, 2, 3, 4 PORTp Tcyc * 8 TIME DELAY. 4 s SOFTWARE ƒ v 3), 4), z Žlr, CPU 1 rl ˆ ˆ > Tcyc * 8 FCLK ƒ. ek 3) 4) l z, PRORAM SEQUENCEm. g, y Ž ( JITTER ¹ ) PULSE, PPLS±¹ ƒ RANE DATA ª ƒ, RANE DATA ª ƒ, z ƒ ¼q 126

133 Hardware Chip User Manual Rev y ± p ƒ FCLK ª ƒ. g, l ² ± l d º ƒ MHz, 8.192MHz d 2 ± p 각종 PARAMETER 의변경 CAMC-FS DRIVE sd PARAMETERp USER PRORAM m ƒ m ƒ. zz PARAMETER ˆ ƒ /x p, DRIVE PARAMETER x ƒ p ˆz ˆ. DRIVE x PARAMETERxm «. RANE DATA ± ƒ ½ xº r, PULSE MOTOR / SERVO MOTORp pm s ƒ. ½, PRESET PULSE DRIVE p. ( * ) START/STOP SPEED DATA ˆ SPEED DATA x. PRESET PULSE DRIVE ˆ m START / STOP SPEED Ž, START / STOP SPEED», ˆ ˆ p. ( * ) RATE DATA x. PRESET PULSE DRIVE ˆ ˆ Ž. ( * ) *PRESET PULSE DRIVE ƒ, ˆ POINT wˆ " wˆ" m, DRIVE¹ " n " ˆ POINT ˆ. ek ƒ PARAMETER x " ƒ" p DATA 의 ERROR 판정 CAMC-FS ƒ DATA ƒ CKECK ƒ, k ƒp DATA ERRORm ±. - RANE DATA = 0 - START/STOP SPEED DATA = 0 127

134 8. y Hardware Chip User Manual Rev OBJECT SPEED DATA = 0 - START/STOP SPEED DATA > OBJECT SPEED DATA - RATE DATA = 0 g, DATA ERRORm ±. 1) DATA ERROR p m DRIVEp ˆ DRIVE COMMAND ˆ» BUSY = Hm p, PULSE l ˆ Ž DRIVE n. e END STATUS READ PORT DTEED BIT 1m. (, l p p SYNCˆ¹, INPˆ¹ º ˆ.) BUSY = Lm r, 2) DRIVE DATA ERROR vƒ DRIVE (BUSY = H ) DATA x, DATA ERROR vƒ, ¹ l PULSE NOT ACTIVEm, ƒ BUSY = Lm r, DRIVE n. e END STATUS READ PORT DTEED BIT 1m. (, l p p INPˆ¹ º ˆ.) ) DRIVE START/STOP SPEED DATA = 0, g OBJECT SPEED DATA = 0m, ¹ l PULSE NOT ACTIVEm v. l l PULSE ACTIVE ƒ NOT ACTIVE m, BUSY BIT = 1 m xº um. 128

135 Hardware Chip User Manual Rev y 8.4.S 字가감속시주의사항 S v l PULSE ƒ, pv m p 8.2. s DRIVEm r, m v» Ž ƒ um. š ŒŒ ˆ ˆ O šp p² ztšœ Œ {œ { ž OšŒŠP 8.1. Sq Preset pulse drive e v š ŒŒ ˆ ˆ O šp p² ztšœ Œ {œ { ž 8.2. S curve OšŒŠP 129

136 8. y Hardware Chip User Manual Rev. 4.0 š ŒŒ ˆ ˆ O šp p² uh OšŒŠP 8.3. e m p š ŒŒ ˆ ˆ O šp p² Y uh p² X OšŒŠP 8.4. S-curve e m p p 8.4. dk { wk d OBJECT SPEED DATA WRITE COMMAND( CODE = 0X82, 0X92)p ˆ. ˆ OBJECT SPEED DATA WRITE COMMAND x r. 8.5.UP, CONST, DOWN 신호 CAMC-FS PULSE l p ±, UP, CONST, DOWN l ˆ¹ r, d DRIVE STATUS READ PORTmz ˆ MONITORIN. d ˆ¹ ± Žk. UP CONST DOWN PULSE l ¹ 130

137 Hardware Chip User Manual Rev y PULSE l ¹ PULSE l ¹ PULSE l Ž * ƒr m * m ˆ p m Ž m. l, Žk TIMIN CHART ˆ m, THRESHOLD LEVEL p, l ˆ p 0 1 xº v 1 0 xº ˆ n. ekƒ, ƒz ˆ m 1m ±, g 0 m ± ˆ ( 20 ns ) ƒ. UP ± LEVEL CONST ± LEVEL DOWN ± LEVEL 131

138 8. y Hardware Chip User Manual Rev 가감속 PULSE 의산출 v z ƒ PULSE, Žk ˆ m. P UD ( 주파수 A + 주파수 B ) 가감속시간 / 2 = P UD PULSE ± A p «ˆ / ˆ ± (Pulse / Sec) ± B p «± (Pulse / Sec) ˆ g ˆ (Sec) SPE ED ± B ± A ˆ ˆ TIME ˆ ƒ g ˆ ² / ± ˆ r. ) CAMC-FS DIITAL LSI. ekƒ ˆ ƒ ( ) ƒ r PULSEz Ÿp vƒ 미사용 ( 未使用 ) 입력단자의처리 CAMC-FS l 50KΩ ( 18.5KΩ / 125KΩ ) m z PULL_UP. ekƒ, H LEVEL z ºp «Ž v ƒ OPEN m tw LIMIT 신호의검출 CAMC-FS ( ) OVERRUN LIMIT ˆ¹mƒ / w, / LIMIT ˆ¹ l ƒ, DRIVE l m g. CAMC-FS ˆ¹ DRIVE (+/- SINAL SEARCH - 1, - 2 DRIVE) ƒ, ˆ¹mƒ Žƒ q LIMIT ˆ¹p. LIMIT ˆ¹p ˆ¹m, +/- SINAL SEARCH - 1 DRIVEp ˆ ƒ ˆ. LIMIT ˆ¹ yk LIMIT ˆ ˆ¹ v. l LIMIT ˆ¹ f " " m y Žtl 132

139 Hardware Chip User Manual Rev y t p, l LIMIT ˆ¹ LIMIT ˆ¹ LIMIT " " ƒ m. ekƒ ˆ¹» p ¼q k ¼q p. ƒ COMMAND ( CODE = 0XF0 ) ƒ LIMIT / ƒ BITp 0 m ƒ LIMIT ˆ. m LIMIT ˆ¹ / s m ƒ ˆ¹ ˆ l ƒ ƒ 엔코더 2 相신호의 CHATTERIN CAMC-FS l m 2 ˆ¹p l COUNT EXTERNAL COUNTERp. 2 ˆ¹ ROTARY ENCODER LINEAR SCALEd mz q, v CHATTERIN vƒ q. 2 ˆ¹p COUNT CHATTERIN f p POINTm. 2 ˆ¹ CHATTERIN m m UP / DOWN vy, m MISS COUNTp «Ž. l z ºm d CHATTERIN ¼ l ³ p ½ COUNTER z. ˆ m 2 ˆ¹p COUNT rr t ºm. l CAMC-FS l t TIMIN p COUNT ºˆ½ y DIITAL FILTER. CAMC-FS 2 ˆ¹p l ˆ«CHATTERIN em Ž NOISE p ¹ r l ºm d ³ ˆ«. ECUP(A ) ECDN(B ) T T T T T T T T Tcyc * (nsec) Tcyc ICLK l 133

140 8. y Hardware Chip User Manual Rev 엔코더 2 相신호 COUNT POINT 1 w ˆ( ) ECUP(A ) UP DOWN ECDN(B ) 2 w ˆ( ) UP UP DOWN DOWN ECUP(A ) ECDN(B ) 4 w ˆ( ) UP UP DOWN DOWN ECUP(A ) UP UP DOWN DOWN ECDN(B ) COUNT UP COUNT DOWN 134

141 Hardware Chip User Manual Rev ¹ 9. 외형치수 135

142 Hardware User Manual 부록 10.1.Address Map A2 A1 A0 8/16SEL CS* RD* WR* Operation Data1 write (2 31 ~2 24 bit ) 8bit access Data2 write (2 23 ~2 16 bit ) Data3 write (2 15 ~2 8 bit ) Data4 write (2 7 ~2 0 bit ) Command write Ž Ž Ž Data1 read (2 31 ~2 24 bit ) Data2 read (2 23 ~2 16 bit ) Data3 read (2 15 ~2 8 bit ) Data4 read (2 7 ~2 0 bit ) Ž Ž Ž Ž Data1,Data2 write (2 31 ~2 16 bit ) 16bit access Ž Data1,Data2 write (2 15 ~2 0 bit ) Ž Command write Ž Ž Ž Data1,Data2 read (2 31 ~2 16 bit ) Ž Data1,Data2 read (2 31 ~2 16 bit ) Ž Ž Ž Ž Ž 136

143 Hardware User Manual PORT 설명 DATA1 WRITE PORT ƒ DATA 2 31 ~ 2 24 Bit Datap. D BIT D BIT D BIT D BIT D BIT D BIT D BIT D BIT DATA2 WRITE PORT ƒ DATA 2 23 ~ 2 16 Bit Datap. D BIT D BIT D BIT D BIT D BIT D BIT D BIT D BIT DATA3 WRITE PORT ƒ DATA 2 15 ~ 2 8 Bit Datap. D BIT D BIT D BIT D BIT D BIT D BIT D1 2 9 BIT D0 2 8 BIT 137

144 Hardware User Manual 4.0 DATA4 WRITE PORT ƒ DATA 2 7 ~ 2 0 Bit Datap. D7 2 7 BIT D6 2 6 BIT D5 2 5 BIT D4 2 4 BIT D3 2 3 BIT D2 2 2 BIT D1 2 1 BIT D0 2 0 BIT COMMAND WRITE PORT COMMANDp. D7 2 7 BIT D6 2 6 BIT D5 2 5 BIT D4 2 4 BIT D3 2 3 BIT D2 2 2 BIT D1 2 1 BIT D0 2 0 BIT DATA1 READ PORT ƒ DATA 2 31 ~ 2 24 Bit Datap. D BIT D BIT D BIT D BIT D BIT D BIT D BIT D BIT DATA2 READ PORT 138

145 Hardware User Manual 4.0 ƒ DATA 2 23 ~ 2 16 Bit Datap. D BIT D BIT D BIT D BIT D BIT D BIT D BIT D BIT DATA3 READ PORT ƒ DATA 2 15 ~ 2 8 Bit Datap. D BIT D BIT D BIT D BIT D BIT D BIT D1 2 9 BIT D0 2 8 BIT DATA4 READ PORT ƒ DATA 2 7 ~ 2 0 Bit Datap. D7 2 7 BIT D6 2 6 BIT D5 2 5 BIT D4 2 4 BIT D3 2 3 BIT D2 2 2 BIT D1 2 1 BIT D0 2 0 BIT 139

146 Hardware User Manual COMMAND 일람표 (Compact, register map) CAMC-FS READ COMMAND CODE(HEX) p (PM-1 ROUP l READ) W DEFAULT 00 PM-1 Range data[rane] 16 0xFFFF 01 PM-1 Start/Stop speed data[std] 16 0x PM-1 Object speed data[obj] 16 0x PM-1 Rate-1 data[rate1] 16 0xFFFF 04 PM-1 Rate-2 data[rate2] 16 0xFFFF 05 PM-1 Rate-3 data[rate3] 16 0xFFFF 06 PM-1 Rate change point(rate1 RATE2)[RCP1] 16 0xFFFF 07 PM-1 Rate change point(rate2 RATE3)[RCP2] 16 0xFFFF 08 PM-1 S profile region width-1 data[sw1] 15 0x7FFF 09 PM-1 S profile region width-2 data[sw2] 15 0x7FFF 0A PM-1 PWM output confiture data[pwm] 3 0x00 0B PM-1 Slowdown/rear pulse amount data[rear] 32 0x C PM-1 Current speed data[spd] 16 0x0000 0D PM-1 Current speed compare data[spdcmp] 16 0x0000 0E PM-1 Drive pulse amount data[drvpulse] 32 0x F PM-1 Preset pulse amount data[presetpulse] 32 0x CODE(HEX) p (PM-1 UP-DATE ROUPl READ) W DEFAULT 10 PM-1 up-date Range data[urane] 16 0xFFFF 11 PM-1 up-date Start/Stop speed data[ustd] 16 0x PM-1 up-date Object speed data[uobj] 16 0x PM-1 up-date Rate-1 data[urate1] 16 0xFFFF 14 PM-1 up-date Rate-2 data[urate2] 16 0xFFFF 15 PM-1 up-date Rate-3 data[urate3] 16 0xFFFF 16 PM-1 up-date Rate change point (URATE1 URATE2)[URCP1] 17 PM-1 up-date Rate change point (URATE2 URATE3)[URCP2] 16 0xFFFF 16 0xFFFF 18 PM-1 up-date S profile region width-1 data[usw1] 15 0x7FFF 19 PM-1 up-date S profile region width-2 data[usw2] 15 0x7FFF 1A No operation[nop] 140

147 Hardware User Manual 4.0 CODE(HEX) p (PM-1 UP-DATE ROUPl READ) W DEFAULT 1B PM-1 up-date Slowdown/rear pulse amount data[urear] 32 0X C PM-1 Current speed data(same with 0x0C)[SPD] 16 0x0000 1D PM-1 Current speed compare data(same with 0x0D) [SPDCMP] 16 0x0000 1E PM-1 Drive pulse amount data(same with 0x0E) [DRVPULSE] 32 0X F PM-1 Preset pulse amount data (same with 0x0F) [PRESETPULSE] 32 0X CODE(HEX) p (PM-2 ROUP l READ) W DEFULT 20~2C No operation[nop] Drive mode configure data[drivemode] 2bit : Source selectioin for deceleration point search 0 (Use internal count), 1 (Use external count) 2D 2E 01~01 bit : Profile selection 00 : Symetric Trapezoid 01 : Unsymetric Trapezoid 10 : Symetric S curve 11 : Unsymetric S curve Mpg operation configure data[mpcon] 6bit : Continuouse drive start by EXPP, EXMP; 0 (Reset), 1 (Set) 5bit : Preset drive start by EXPP, EXMP; 0 (Reset), 1 (Set) 03~04 bit : Quadrature EXPP, EXMP signal mode 00 : 1 phase pulse mode 01 : 2 phase pulse mode(one time) 10 : 2 phase pulse mode(two times) 11 : 2 phase pulse mode(four times) 2 bit : Mpg drive direction use configure 0 (Plus direction), 1 (Minus direction) 1 bit : Mpg drive direction source configure 0 (EXPP, EXMP signal dir.), 1 (User configure dir.) 0bit : Slave mpg drive start by EXPP, EXMP 0 (Reset), 1 (Set) 3 0x0 7 0x00 2F Mpg preset drive pulse amount[pulsemp] 32 0x CODE(HEX) p ( º ROUP l READ ) W DEFULT 30~35 No operation[nop] 141

148 Hardware User Manual 4.0 CODE(HEX) p ( º ROUP l READ ) W DEFULT Software limit configure data[swlmtcon] 2 bit : Software limit compare source selection 0 (Internal count), 1 (External count) 36 1 bit : Software limit execution mode 0 (Emergency stop), 1 (Slow down stop) 0 bit : Soft limit Enable/Disable 0 (Disable), 1 (Enable) 3 0x0 37 Minus software limit compare data[mswlmtcomp] 32 0x Plus software limit compare data[pswlmtcomp] 32 0x7FFFFFFF Trigger configure data[trcon] 31~16 bit : Trigger active pulse width(unsigned) Width = T clk x (Decimal value of trigger active pulse width) If Width = 0 then Initialize Trigger function ~ 02 bit : Don t care. 1 bit : Trigger compare source selection 0 (Internal), 1 (External) 0 bit : Trigger mode 0 (Absolute), 1 (Periodic) 32 0x A Trigger compare data[trcomp] 32 0x B Internal count minus limit data[icm] 32 0x C External count minus limit data[ecm] 32 0x D~3F No operation[nop] CODE(HEX) p ( p ROUPl READ) W DEFULT Script control register-1[scrcon1] 31 bit : 0 (One time execution, 1 : Always) 30~26bit : Don t care 25~24bit : Event operation between first and second event 00 : None, Use first event source only : OR operation 10 : AND operation 11 : XOR operation 23~16bit : Second event assign 15~ 8 bit : First event assign 7~ 0 bit : Execution command (write command only) 32 0x

149 Hardware User Manual 4.0 CODE(HEX) p ( p ROUPl READ) W DEFULT *See event list table for event assign Script control register-2[scrcon2] (Same with script control register-1) Script control register-3[scrcon3] (Same with script control register-1) Script control queue[scrconq] (Queue bottom contents) 31 bit : 0 (One time execution, 1 : Always) 30 bit : Interrupt generation when executed 0 (Disable), 1 (Enable) 29~26bit: Don t care 25~24bit : Event operation between first and second event 00 : None, Use first event source only 01 : OR operation 10 : AND operation 11 : XOR operation 23~ 16 bit : Second event assign 15~ 8 bit : First event assign * When 0xFF, No check event, just execute command 7~ 0 bit : Execution command (write command only) 32 0x x x Script data register-1[scrdata1] 32 0x Script data register-2[scrdata1] 32 0x Script data register-3[scrdata1] 32 0x Script data queue (Queue bottom contents) [SCRDATAQ] 32 0x No operation[nop] 49 Script control queue index(max to 0xD)[SCRCQSIZE] 4 0x0 4A Script data queue index(max to 0xD) [SCRDQSIZE] 4 0x0 Script queue Full/Empty flag[scrqsla] 3 bit : Script control queue full flag 0 (False), 1 (True) 4B 4C 2 bit : Script control queue empty flag 0 (False), 1 (True) 1 bit : Script data queue full flag 0 (False), 1 (True) 0 bit : Script data queue empty flag 0 (False), 1 (True) Script queue size configure data (1~13) [SCRQSIZECON] 15~ 12 bit : Script control queue full size 11~ 08 bit : Script control queue empty size 4 0x5 16 0xD0D0 143

150 Hardware User Manual 4.0 CODE(HEX) p ( p ROUPl READ) W DEFULT 07~ 04 bit : Script data queue full size 03~ 00 bit : Script data queue empty size Script queue status[scrqstatus] 11~ 08 bit : Script control queue index(same with 0x49) 07~ 04 bit : Script data queue index(same with 0x4A) 4D 4E~4F 3 bit : Script control queue full flag 0 (False), 1 (True) 2 bit : Script control queue empty flag 0 (False), 1 (True) 1 bit : Script data queue full flag 0 (False), 1 (True) 0 bit : Script data queue empty flag 0 (False), 1 (True) No operation[nop] 12 0x005 CODE(HEX) p ( tp ROUPl READ) R DEFAULT Caption control register-1[capcon1] 31 bit : 0 (One time execution, 1 : Always) 30~26bit: Don t care 25~24bit : Event operation between first and second event 00 : None, Use first event source only : OR operation 10 : AND operation 11 : XOR operation 23~16bit : Second event assign 15~ 8 bit : First event assign 7~ 0 bit : Execution command (read command only) *See event list table for event assign Caption control register-2[capcon2] (Same with script control register-1) Caption control register-3[capcon3] (Same with script control register-1) Caption control queue[capconq] 31 bit : 0 (One time execution, 1 : Always) 30 bit : Interrupt generation when executed 0 (Disable), 1 (Enable) 29~26bit: Don t care 25~24bit : Event operation between first and second event 00 : None, Use first event source only 32 0x x x x

151 Hardware User Manual 4.0 CODE(HEX) p ( tp ROUPl READ) R DEFAULT 01 : OR operation 10 : AND operation 11 : XOR operation 23~16bit : Second event assign 15~ 8 bit : First event assign * When 0xFF, No check event, just execute command 7~ 0 bit : Execution command (read command only) *See event list table for event assign 54 Caption control register-1 execution result [CAPDATA1] 32 0x Caption control register-2 execution result [CAPDATA2] 32 0x Caption control register-3 execution result [CAPDATA3] 32 0x Caption control queue execution result data queue [CAPDATAQ] 32 0x No operation[nop] 59 Caption control queue index(max to 0xD) [CAPCQSIZE] 4 0x0 5A Caption result data queue index(max to 0xD) [CAPDQSIZE] 4 0x0 Caption queue Full/Empty flag[capqsla] 6 bit : Caption control resiger-1 result data updated 0 (False), 1 (True) 5 bit : Caption control resiger-2 result data updated 0 (False), 1 (True) 5B 5C 5D 4 bit : Caption control resiger-3 result data updated 0 (False), 1 (True) 3 bit : Caption control queue full flag 0 (False), 1 (True) 2 bit : Caption control queue empty flag 0 (False), 1 (True) 1 bit : Caption result data queue full flag 0 (False), 1 (True) 0 bit : Caption result data queue empty flag 0 (False), 1 (True) Caption queue size configure data (0~13) [CAPQSIZECON] 15~ 12 bit : Caption control queue full size 11~ 08 bit : Caption control queue empty size 07~ 04 bit : Caption result data queue full size 03~ 00 bit : Caption result data queue empty size Caption queue status[capqstatus] 11~ 08 bit : Caption control queue index(same with 0x59) 07~ 04 bit : Caption data queue index(same with 0x5A) 3 bit : Caption control queue full flag 0 (False), 1 (True) 7 0x5 16 0xD0D0 12 0x

152 Hardware User Manual 4.0 CODE(HEX) p ( tp ROUPl READ) R DEFAULT 2 bit : Caption control queue empty flag 0 (False), 1 (True) 1 bit : Caption result data queue full flag 0 (False), 1 (True) 0 bit : Caption result data queue empty flag 0 (False), 1 (True) 5E~5F No operation[nop] CODE(HEX) p (BUS-1 ROUPl READ) W DEFAULT 60 Internal count data(signed)[incnt] 32 0x Internal count compare data(signed)[incntcmp] 32 0x Internal count scale data(unsigned) [INCNTSCALE] 8 0x00 63 Internal count plus limit data[icp](use 0x3B for minus limit) 32 0x7FFFFFFF 64 External count data(signed)[excnt] 32 0x External cont compare data(signed)[excntcmp] 32 0x External count scale data(unsigned)[excntscale] 8 0x00 67 External count plus limit data[ecp](use 0x3C for minus limit) 32 0x7FFFFFFF 68 External speed data[exspd] 32 0x External speed compare data[exspdcmp] 32 0x A External signal filter depth data[exfilterd] 7~00 bit : Digital Filter for input signals 8 0x05 6B Off region(over run or under run) decision data[offreion] 8 0x00 Deviation data(incnt EXCNT)[DEVIATION] 6C 6D 6E 6F 15 bit : Result sign 0 (Plus), 1 (Minus) 14~00 bit : Absolute value of deviation PM register bank selection configure data[pmch] 0 (PM-1 bank use), 1 (PM-1 update bank use) Comparator source selection configure[compcon] 00 : 1 st : Internal count, 2 nd : External count 01 : 1 st : Internal count, 2 nd : Internal count 10 : 1 st : External count, 2 nd : External count No operation[nop] 16 0x x0 2 0x0 CODE(HEX) p (BUS-2 ROUPl READ) W DEFAULT Function configure data [FUNCON] 70 Each bit : 0 (Reset, Disable), 1 (Set, Enable) 12bit : S profile triangle drive configure 11bit : Search drive source filter configure 13 0x0C3E 146

153 Hardware User Manual 4.0 CODE(HEX) p (BUS-2 ROUPl READ) W DEFAULT 10bit : SYNC input signal function configure 9 bit : Limit complete stop configure 8 bit : INPOS input signal expanded function configure 7bit : Off region stop mode '0 (Emergency stop), 1 (Slowdown stop) 6 bit : Drive at start/stop speed '0 (Stop at STD speed), 1 (Continuous drive at STD speed) 5 bit : NSLM/PSLM input signal function configure 4 bit : NELM/PELM input signal function configure 3 bit : ESTOP/SSTOP signal function configure 2 bit : Don t care 1 bit : ALARM input signal function configure 0 bit : INPOS input signal basic function configure Mode1 data [MODE1] 7 bit : Preset drive slowdown point decision method (Auto), 1 (Manual) 06~04 bit : PULSE/DIR output signal configure(* See table) 03~00 bit : Signal search drive source configure(* See table) Mode2 data[mode2] Active level : 0 (Active low), 1 (Active high) 10 bit : TRI output signal active level 9 bit : INT output signal active level 8 bit : MARK input signal active level 07~06 bit : Encoder signal count mode(ecup/ecdn input signal) 00 : Single phase, (ECUP : up count, ECDN : down count) 01 : Two phases, 1 times multiplied 10 : Two phases,, 2 times multiplied 11 : Two phases,, 4 times multiplied 5 bit : INPOS input signal active level 4 bit : ALARM input signal active level 3 bit : NSLM input signal active level 2 bit : PSLM input signal active level 1 bit : NELM input signal active level 0 bit : PELM input signal active level 8 0x x Universal In/Out signal data[uiodata] 11 0x

154 Hardware User Manual 4.0 CODE(HEX) p (BUS-2 ROUPl READ) W DEFAULT 10~08 bit : Universal output bit operation 0xx : Operand bypass 100 : NOT Current output 101 : Output operand AND Current output 110 : Output operand OR Current output 111 : Output operand XOR Current output 07~04 bit : Universal Input signal 03~00 bit : Universal Output signal End status[endstatus] 14 bit : Drive end by limit 13 bit : Drive end by limit complete stop 12 bit : Sensor positioning drive end 11 bit : Preset pulse drive end 10 bit : Signal search drive end 9 bit : Original search drive end bit : Drive end by off region error 7 bit : Drive end by data error 6 bit : Drive end by ALARM signal function 5 bit : Drive end by emergency stop command(0xac) 4 bit : Drive end by slowdown stop command(0xab) 3 bit : Drive end by ESTOP signal function 2 bit : Drive end by SSTOP signal function 1 bit : Drive end by PELM/NELM, software emergency limit 0 bit : Drive end by PSLM/NSLM, software slowdown limit Mechanical data[mech] 12 bit : ESTOP input signal level 11 bit : SSTOP input signal level 10 bit : MARK input signal is level 9 bit: EXPP input signal level 8 bit: EXMP input signal level 7 bit : ECUP input signal level 6 bit : ECDN input signal level 5 bit : INPOS input signal active status 4 bit : ALARM input signal active status 3 bit : NSLM input signal active status 15 0x

155 Hardware User Manual 4.0 CODE(HEX) p (BUS-2 ROUPl READ) W DEFAULT 2 bit : PSLM input signal active status 1 bit : NELM input signal active status 0 bit : PELM input signal active status Drive status[drvstatus] 8 bit: Drive direction 0 (CW), 1 (CCW) 7 bit : EC(EXCNTCMP less than EXCNT) 6 bit : ECL(EXCNTCMP greater than EXCNT) bit : IC(INCNTCMP less than INCNT) 4 bit : ICL(INCNTCMP greater than INCNT) 3 bit : UP (In acceleration drive) 2 bit : CONST (In constant speed drive) 1 bit : DOWN (In deceleration drive) 0 bit : BUSY (On driving) External count clear configure data[excntclr] 8 bit : External count clear flag(clear when write 0xF7) 7 bit : External count mode 0 : Normal count, 1 : Reverse count 6 bit : Don t care 05~04 bit : Clear operation mode 00 : Clear request reset 01 : One time clear request set 10 : Full time clear request set 11 : Clear external count and LOCK to zero at clear input signal activated 03~00 bit : Clear input signal assign 0001 : IN : IN : IN : IN3 Others : Don t care(no clear) 9 9 0x No operation[nop] Interrupt flag data[intfal] 79 Each bit : 0 (Interrupt inactivated), 1 ( Interrupt activated) 31 bit : Selectable Interrupt source3(refer 0xFE command) 30 bit : Selectable Interrupt source2(refer 0xFE command) 32 0x

156 Hardware User Manual 4.0 CODE(HEX) p (BUS-2 ROUPl READ) W DEFAULT 29 bit : Selectable Interrupt source1(refer 0xFE command) 28 bit : Selectable Interrupt source0(refer 0xFE command) 27 bit : NELM/PELM input signal activated 26 bit : NSLM/PSLM input signal activated 25 bit : Caption queue command executed when CAPCONQ s 30 bit is 1 24 bit : Script queue command executed when SCRCONQ s 30 bit is 1 23 bit : 1 st counter value is equal with minus limit data 22 bit : Current speed is equal with current speed compare data 21 bit : Current speed is equal with rate change point RCP12 20 bit : Current speed is equal with rate change point RCP23 19 bit : Search signal assigned in MODE1 is detected 18 bit : Acceleration drive started 17 bit : Constant speed drive started 16 bit : Deceleration drive started 15 bit : Interrupt generated by command 0xFF 14 bit : Caption control register-3 command is executed 13 bit : Caption control register-2 command is executed 12 bit : Caption control register-1 command is executed 11 bit : Script control register-3 command is executed 10 bit : Script control register-2 command is executed 9 bit : Script control register-1 command is executed 8 bit : Caption result queue is FULL 7 bit : Script control queue is EMPTY 6 bit : ECL(EXCNTCMP is greater than EXCNT) 5 bit : ECE(EXCNTCMP is equal with EXCNT) 4 bit : EC(EXCNTCMP is less with EXCNT) 3 bit : ICL(INCNTCMP is greater than INCNT) 2 bit : ICE(INCNTCMP is equal with INCNT) 1 bit : IC(INCNTCMP is less than INCNT) 0 bit : Drive end 7A Interrupt mask data[intmask] Each bit : 0 (Interrupt inactivated), 1 ( Interrupt activated) 32 0x B EMODE1 data [EMODE1] 8 0x00 150

157 Hardware User Manual 4.0 CODE(HEX) p (BUS-2 ROUPl READ) W DEFAULT 7 bit : Extension mode enable(0 : Disable, 1 : Enable) 0 : md_out[12:8] => md_out[12:8] 1 : md_out[12:8] => EUIO 6~ 5 bit : Don t care 4 bit : EUO4 enable/disable(0 : disable, 1 : enable) 3 bit : EUO3 enable/disable(0 : disable, 1 : enable) 2 bit : EUO2 enable/disable(0 : disable, 1 : enable) 1 bit : EUO1 enable/disable(0 : disable, 1 : enable) 0 bit : EUIO0 direction select(0 : input, 1 : output) Extension universal in/out[euiodata] 07~05 bit : Extension Universal output bit operation 0xx : Operand bypass 7C 7D 7E 7F 100 : NOT Current output 101 : Output operand AND Current output 110 : Output operand OR Current output 111 : Output operand XOR Current output 4 ~ 0 bit : Extension Universal in/output No operation[nop] User Interrupt source configure data[intusercon] Same with Script/Caption event list(except 0xFF event) 31~24 bit : User selectable interrupt 3 source selection 23~16 bit : User selectable interrupt 2 source selection 15~ 08 bit : User selectable interrupt 1 source selection 07 ~00 bit : User selectable interrupt 0 source selection No operation[nop] 8 0x x

158 Hardware User Manual 4.0 CAMC-FS WRITE COMMAND CODE(HEX) p (PM-1 ROUP l WRITE) W DEFAULT 80 PM-1 Range data[rane] 16 0xFFFF 81 PM-1 Start/Stop speed data[std] 16 0x PM-1 Object speed data[obj] 16 0x PM-1 Rate-1 data[rate1] 16 0xFFFF 84 PM-1 Rate-2 data[rate2] 16 0xFFFF 85 PM-1 Rate-3 data[rate3] 16 0xFFFF 86 PM-1 Rate change point(rate1 RATE2)[RCP1] 16 0xFFFF 87 PM-1 Rate change point(rate2 RATE3)[RCP2] 16 0xFFFF 88 PM-1 S profile region width-1 data[sw1] 15 0x7FFF 89 PM-1 S profile region width-2 data[sw2] 15 0x7FFF 8A PM-1 PWM output confiture data[pwm] 3 0x00 8B PM-1 Slowdown/rear pulse amount data[rear] 32 0x C No operation[nop] 16 0x0000 8D PM-1 Current speed compare data[spdcmp] 16 0x0000 8E No operation[nop] 32 0x F No operation[nop] 32 0x CODE(HEX) p (PM-1 UP-DATE ROUPl WRITE) W DEFAULT 90 PM-1 up-date Range data[urane] 16 0xFFFF 91 PM-1 up-date Start/Stop speed data[ustd] 16 0x PM-1 up-date Object speed data[uobj] 16 0x PM-1 up-date Rate-1 data[urate1] 16 0xFFFF 94 PM-1 up-date Rate-2 data[urate2] 16 0xFFFF 95 PM-1 up-date Rate-3 data[urate3] 16 0xFFFF 96 PM-1 up-date Rate change point (URATE1 URATE2)[URCP1] 97 PM-1 up-date Rate change point (URATE2 URATE3)[URCP2] 16 0xFFFF 16 0xFFFF 98 PM-1 up-date S profile region width-1 data[usw1] 15 0x7FFF 99 PM-1 up-date S profile region width-2 data[usw2] 15 0x7FFF 9A No operation[nop] 9B PM-1 up-date Slowdown/rear pulse amount data[urear] 32 0X

159 Hardware User Manual 4.0 CODE(HEX) p (PM-1 UP-DATE ROUPl WRITE) W DEFAULT 9C No operation[nop] 16 0x0000 9D PM-1 Current speed compare data(same with 0x0D) [SPDCMP] 16 0x0000 9E No operation[nop] 32 0X F No operation[nop] 32 0X CODE(HEX) p (PM-2 ROUP l WRITE) W DEFULT A0 Plus preset pulse drive[ppresetdrv] 32 A1 A2 A3 Plus continuous drive[pcontdrv] Plus signal search-1 drive[psch1drv] Plus signal search-2 drive[psch2drv] A4 Plus original search drive[pordrv] 0 bit : OR signal detection edge configure 0 (Falling edge detect), 1 (Rising edge detect) 1 A5 Minus preset pulse drive[mpresetdrv] 32 A6 A7 A8 Minus continuous drive[mcontdrv] Minus signal search-1 drive[msch1drv] Minus signal search-2 drive[msch2drv] A9 Minus original search drive[mordrv] 0 bit : OR signal detection edge configure 0 (Falling edge detect), 1 (Rising edge detect) 1 AA Preset/Mpg drive pulse amount override[pulseover] 32 AB AC Slow down stop[sstopcmd] Emergency stop[estopcmd] AD AE Drive mode configure data[drivemode] 2bit : Source selectioin for deceleration point search 0 (Use internal count), 1 (Use external count) 01~01 bit : Profile selection 00 : Symetric Trapezoid 01 : Unsymetric Trapezoid 10 : Symetric S curve 11 : Unsymetric S curve Mpg operation configure data[mpcon] 6bit : Continuouse drive start by EXPP, EXMP; 0 (Reset), 1 (Set) 5bit : Preset drive start by EXPP, EXMP; 0 (Reset), 1 (Set) 03~04 bit : Quadrature EXPP, EXMP signal mode 3 0x0 7 0x00 153

160 Hardware User Manual 4.0 CODE(HEX) p (PM-2 ROUP l WRITE) W DEFULT 00 : 1 phase pulse mode 01 : 2 phase pulse mode(one time) 10 : 2 phase pulse mode(two times) 11 : 2 phase pulse mode(four times) 2 bit : Mpg drive direction use configure 0 (Plus direction), 1 (Minus direction) 1 bit : Mpg drive direction source configure 0 (EXPP, EXMP signal dir.), 1 (User configure dir.) 0bit : Slave mpg drive start by EXPP, EXMP 0 (Reset), 1 (Set) AF Mpg preset drive pulse amount[pulsemp] 32 0x CODE(HEX) p ( º ROUP l WHITE ) W DEFULT B0 Plus sensor positioning drive I [PSPO1DRV] 32 B1 Minus sensor positioning drive I[MSPO1DRV] 32 B2 Plus sensor positioning drive II [PSPO2DRV] 32 B3 Minus sensor positioning drive II [MSPO2DRV] 32 B4 Plus sensor positioning drive III [PSPO3DRV] 32 B5 Minus sensor positioning drive III [MSPO3DRV] 32 Software limit configure data[swlmtcon] 2 bit : Software limit compare source selection 0 (Internal count), 1 (External count) B6 1 bit : Software limit execution mode 0 (Emergency stop), 1 (Slow down stop) 0 bit : Soft limit Enable/Disable 0 (Disable), 1 (Enable) 3 0x0 B7 Minus software limit compare data[mswlmtcomp] 32 0x B8 Plus software limit compare data[pswlmtcomp] 32 0x7FFFFFFF Trigger configure data[trcon] 31~16 bit : Trigger active pulse width(unsigned) Width = T clk x (Decimal value of trigger active pulse width) B9 If Width = 0 then Initialize Trigger function. 15~ 02 bit : Don t care. 1 bit : Trigger compare source selection 0 (Internal), 1 (External) 32 0x

161 Hardware User Manual 4.0 CODE(HEX) p ( º ROUP l WHITE ) W DEFULT 0 bit : Trigger mode 0 (Absolute), 1 (Periodic) BA Trigger compare data[trcomp] 32 0x BB Internal count minus limit data[icm] 32 0x BC External count minus limit data[ecm] 32 0x BD~BF No operation[nop] CODE(HEX) p ( p ROUPl WRITE) W DEFULT Script control register-1[scrcon1] 31 bit : 0 (One time execution, 1 : Always) 30~26bit : Don t care 25~24bit : Event operation between first and second event 00 : None, Use first event source only C0 C1 C2 C3 01 : OR operation 10 : AND operation 11 : XOR operation 23~16bit : Second event assign 15~ 8 bit : First event assign 7~ 0 bit : Execution command (write command only) *See event list table for event assign Script control register-2[scrcon2] (Same with script control register-1) Script control register-3[scrcon3] (Same with script control register-1) Script control queue[scrconq] (Queue bottom contents) 31 bit : 0 (One time execution, 1 : Always) 30 bit : Interrupt generation when executed 0 (Disable), 1 (Enable) 29~26bit: Don t care 25~24bit : Event operation between first and second event 00 : None, Use first event source only 01 : OR operation 10 : AND operation 11 : XOR operation 32 0x x x x

162 Hardware User Manual 4.0 CODE(HEX) p ( p ROUPl WRITE) W DEFULT 23~ 16 bit : Second event assign 15~ 8 bit : First event assign * When 0xFF, No check event, just execute command 7~ 0 bit : Execution command (write command only) C4 Script data register-1[scrdata1] 32 0x C5 Script data register-2[scrdata1] 32 0x C6 Script data register-3[scrdata1] 32 0x C7 Script data queue (Queue bottom contents) [SCRDATAQ] 32 0x C8 C9~CB Script control/data queue clear[scrqclr] No operation[nop] CC CD~CF Script queue size configure data (1~13) [SCRQSIZECON] 15~ 12 bit : Script control queue full size 11~ 08 bit : Script control queue empty size 07~ 04 bit : Script data queue full size 03~ 00 bit : Script data queue empty size No operation[nop] 16 0xD0D0 CODE(HEX) p ( tp ROUPl WRITE) W DEFAULT Caption control register-1[capcon1] 31 bit : 0 (One time execution, 1 : Always) 30~26bit: Don t care 25~24bit : Event operation between first and second event 00 : None, Use first event source only D0 D1 D2 01 : OR operation 10 : AND operation 11 : XOR operation 23~16bit : Second event assign 15~ 8 bit : First event assign 7~ 0 bit : Execution command (read command only) *See event list table for event assign Caption control register-2[capcon2] (Same with script control register-1) Caption control register-3[capcon3] (Same with script control register-1) 32 0x x x D3 Caption control queue[capconq] 32 0x

163 Hardware User Manual 4.0 CODE(HEX) p ( tp ROUPl WRITE) W DEFAULT 31 bit : 0 (One time execution, 1 : Always) 30 bit : Interrupt generation when executed 0 (Disable), 1 (Enable) 29~26bit: Don t care 25~24bit : Event operation between first and second event 00 : None, Use first event source only 01 : OR operation 10 : AND operation 11 : XOR operation 23~16bit : Second event assign 15~ 8 bit : First event assign * When 0xFF, No check event, just execute command 7~ 0 bit : Execution command (read command only) *See event list table for event assign D4~D7 D8 D9~DB No operation[nop] Caption control queue clear[capqclr] No operation[nop] DC DD~DF Caption queue size configure data (0~13) [CAPQSIZECON] 15~ 12 bit : Caption control queue full size 11~ 08 bit : Caption control queue empty size 07~ 04 bit : Caption result data queue full size 03~ 00 bit : Caption result data queue empty size No operation[nop] 16 0xD0D0 CODE(HEX) p (BUS-1 ROUPl WRITE) W DEFAULT E0 Internal count data(signed)[incnt] 32 0x E1 Internal count compare data(signed)[incntcmp] 32 0x E2 Internal count scale data(unsigned) [INCNTSCALE] 8 0x00 E3 Internal count plus limit data[icp](use 0x3B for minus limit) 32 0x7FFFFFFF E4 External count data(signed)[excnt] 32 0x E5 External cont compare data(signed)[excntcmp] 32 0x E6 External count scale data(unsigned)[excntscale] 8 0x00 E7 External count plus limit data[ecp](use 0x3C for minus limit) 32 0x7FFFFFFF E8 External speed data[exspd] 32 0x E9 External speed compare data[exspdcmp] 32 0x

164 Hardware User Manual 4.0 CODE(HEX) p (BUS-1 ROUPl WRITE) W DEFAULT External signal filter depth data[exfilterd] EA 8 0x05 7~00 bit : Digital Filter for input signals EB Off region(over run or under run) decision data[offreion] 8 0x00 Deviation data(incnt EXCNT)[DEVIATION] EC ED EE EF 15 bit : Result sign 0 (Plus), 1 (Minus) 14~00 bit : Absolute value of deviation PM register bank selection configure data[pmch] 0 (PM-1 bank use), 1 (PM-1 update bank use) Comparator source selection configure[compcon] 00 : 1 st : Internal count, 2 nd : External count 01 : 1 st : Internal count, 2 nd : Internal count 10 : 1 st : External count, 2 nd : External count No operation[nop] 16 0x x0 2 0x0 CODE(HEX) p (BUS-2 ROUPl WRITE) W DEFAULT Function configure data [FUNCON] Each bit : 0 (Reset, Disable), 1 (Set, Enable) 12bit : S profile triangle drive configure 11bit : Search drive source filter configure 10bit : SYNC input signal function configure 9 bit : Limit complete stop configure 8 bit : INPOS input signal expanded function configure 7bit : Off region stop mode F0 F1 '0 (Emergency stop), 1 (Slowdown stop) 6 bit : Drive at start/stop speed '0 (Stop at STD speed), 1 (Continuous drive at STD speed) 5 bit : NSLM/PSLM input signal function configure 4 bit : NELM/PELM input signal function configure 3 bit : ESTOP/SSTOP signal function configure 2 bit : Don t care 1 bit : ALARM input signal function configure 0 bit : INPOS input signal basic function configure Mode1 data [MODE1] 7 bit : Preset drive slowdown point decision method 0 (Auto), 1 (Manual) 13 0x0C3E 8 0x

165 Hardware User Manual 4.0 CODE(HEX) p (BUS-2 ROUPl WRITE) W DEFAULT 06~04 bit : PULSE/DIR output signal configure(* See table) 03~00 bit : Signal search drive source configure(* See table) Mode2 data[mode2] Active level : 0 (Active low), 1 (Active high) 10 bit : TRI output signal active level 9 bit : INT output signal active level 8 bit : MARK input signal active level 07~06 bit : Encoder signal count mode(ecup/ecdn input signal) 00 : Single phase, (ECUP : up count, ECDN : down count) F2 F3 F4~F6 F7 01 : Two phases, 1 times multiplied 10 : Two phases,, 2 times multiplied 11 : Two phases,, 4 times multiplied 5 bit : INPOS input signal active level 4 bit : ALARM input signal active level 3 bit : NSLM input signal active level 2 bit : PSLM input signal active level 1 bit : NELM input signal active level 0 bit : PELM input signal active level Universal In/Out signal data[uiodata] 10~08 bit : Universal output bit operation 0xx : Operand bypass 100 : NOT Current output 101 : Output operand AND Current output 110 : Output operand OR Current output 111 : Output operand XOR Current output 07~04 bit : Don t care 03~00 bit : Universal output operand No operation[nop] External count clear configure data[excntclr] 8 bit : External count clear flag(clear when write 0xF7) 7 bit : External count mode 0 : Normal count, 1 : Reverse count 6 bit : Don t care 05~04 bit : Clear operation mode 00 : Clear request reset 11 0x x x

166 Hardware User Manual 4.0 CODE(HEX) p (BUS-2 ROUPl WRITE) W DEFAULT 01 : One time clear request set 10 : Full time clear request set 11 : Clear external count and LOCK to zero at clear input signal activated 03~00 bit : Clear input signal assign 0001 : IN : IN : IN : IN3 Others : Don t care(no clear) F8 F9 FA FB FC FD FE Software reset[swreset] Interrupt generation command[intencmd Interrupt mask data[intmask] Each bit : 0 (Interrupt inactivated), 1 ( Interrupt activated) EMODE1 data [EMODE1] 7 bit : Extension mode enable(0 : Disable, 1 : Enable) 0 : md_out[12:8] => md_out[12:8] 1 : md_out[12:8] => EUIO 6~ 5 bit : Don t care 4 bit : EUO4 enable/disable(0 : disable, 1 : enable) 3 bit : EUO3 enable/disable(0 : disable, 1 : enable) 2 bit : EUO2 enable/disable(0 : disable, 1 : enable) 1 bit : EUO1 enable/disable(0 : disable, 1 : enable) 0 bit : EUIO0 direction select(0 : input, 1 : output) Extension universal in/out[euiodata] 07~05 bit : Extension Universal output bit operation 0xx : Operand bypass 100 : NOT Current output 101 : Output operand AND Current output 110 : Output operand OR Current output 111 : Output operand XOR Current output 4 ~ 0 bit : Extension universal output operand Limit complete stop clear[climclr] User Interrupt source configure data[intusercon] Same with Script/Caption event list(except 0xFF event) 32 0x x00 8 0x x

167 Hardware User Manual 4.0 CODE(HEX) p (BUS-2 ROUPl WRITE) W DEFAULT 31~24 bit : User selectable interrupt 3 source selection 23~16 bit : User selectable interrupt 2 source selection 15~ 08 bit : User selectable interrupt 1 source selection 07 ~00 bit : User selectable interrupt 0 source selection FF No operation[nop] 161

168 Hardware User Manual 4.0 CAMC-FS REISTER MAP(Alphabetical) NAME Description W READ WRITE CAPCON1 Caption control register x50 0xD0 CAPCON2 Caption control register x51 0xD1 CAPCON3 Caption control register x52 0xD2 CAPCONQ Caption control queue 32 0x53 0xD3 CAPCQSIZE Caption control queue index 4 0x59 - CAPDATA1 Caption control register-1 execution result 32 0x54 - CAPDATA2 Caption control register-2 execution result 32 0x55 - CAPDATA3 Caption control register-3 execution result 32 0x56 - CAPDATAQ Caption control queue execution result data queue 32 0x57 - CAPDQSIZE Caption result data queue index 4 0x5A - CAPQSIZECON Caption queue size configure data (0~13) 16 0x5C 0xDC CAPQSLA Caption queue Full/Empty flag 7 0x5B - CAPQSTATUS Caption queue status 12 0x5D - COMPCON Comparator source selection configure 2 0x6E 0xEE DEVIATION Deviation data(incnt EXCNT) 16 0x6C 0xEC DRIVEMODE Drive mode configure data 3 0x2D 0xAD DRVPULSE PM-1 Drive pulse amount 32 0x0E 0x1E - DRVSTATUS Drive status 9 0x76 - ECM External count minus limit data 32 0x3C 0xBC ECP External count plus limit data 32 0x67 0xE7 EMODE1 EMODE1 data 8 0x7B 0xFB ENDSTATUS End status 15 0x74 - EUIODATA Extension universal in/out 8 0x7C 0xFC EXCNT External count data(signed) 32 0x64 0xE4 EXCNTCLR External count clear configure data 9 0x77 0xF7 EXCNTCMP External cont compare data(signed) 32 0x65 0xE5 EXCNTSCALE External count scale data(unsigned) 8 0x66 0xE6 EXFILTERD External signal filter depth data 8 0x6A 0xEA EXSPD External speed data 32 0x68 - EXSPDCMP External speed compare data 32 0x69 0xE9 FUNCON Function configure data 13 0x70 0xF0 ICM Internal count minus limit data 32 0x3B 0xBB ICP Internal count plus limit data 32 0x63 0xE3 INCNT Internal count data(signed) 32 0x60 0xE0 INCNTCMP Internal count compare data(signed) 32 0x61 0xE1 INCNTSCALE Internal count scale data(unsigned) 8 0x62 0xE2 INTFAL Interrupt flag data 32 0x79 - INTMASK Interrupt mask data 32 0x7A 0xFA INTUSERCON User Interrupt source configure data 32 0x7E 0xFE MECH Mechanical data 13 0x75 - MODE1 Mode1 data 8 0x71 0xF1 MODE2 Mode2 data 11 0x72 0xF2 MPCON Mpg operation configure data 7 0x2E 0xAE MSWLMTCOMP Minus software limit compare data 32 0x37 0xB7 OBJ PM-1 Object speed 16 0x02 0x82 OFFREION Off region(over run or under run) decision data 8 0x6B 0xEB PMCH PM register bank selection configure data 1 0x6D 0xED PRESETPULSE PM-1 Preset pulse amount 32 0x0F 0x1F - PSWLMTCOMP Plus software limit compare data 32 0x38 0xB8 PULSEMP Mpg preset drive pulse amount 32 0x2F 0xAF PWM PM-1 PWM output configure 3 0x0A 0x8A RANE PM-1 Range 16 0x00 0x80 162

169 Hardware User Manual 4.0 NAME Description W READ WRITE RATE1 PM-1 Rate x03 0x83 RATE2 PM-1 Rate x04 0x84 RATE3 PM-1 Rate x05 0x85 RCP1 PM-1 Rate change point(rate1 RATE2) 16 0x06 0x86 RCP2 PM-1 Rate change point(rate2 RATE3) 16 0x07 0x87 REAR PM-1 Slowdown/rear pulse amount 32 0x0B 0x8B SCRCON1 Script control register x40 0xC0 SCRCON2 Script control register x41 0xC1 SCRCON3 Script control register x42 0xC2 SCRCONQ Script control queue 32 0x43 0xC3 SCRCQSIZE Script control queue index(max to 0xD) 4 0x49 - SCRDATA1 Script data register x44 0xC4 SCRDATA1 Script data register x45 0xC5 SCRDATA1 Script data register x46 0xC6 SCRDATAQ Script data queue (Queue bottom contents) 32 0x47 0xC7 SCRDQSIZE Script data queue index(max to 0xD) 4 0x4A - SCRQSIZECON Script queue size configure data (1~13) 16 0x4C 0xCC SCRQFLA Script queue Full/Empty flag 4 0x4B - SCRQSTATUS Script queue status 12 0x4D - SPD PM-1 Current speed 16 0x0C 0x1C - SPDCMP PM-1 Current speed compare 16 0x0D 0x1D 0x8D STD PM-1 Start/Stop speed 16 0x01 0x81 SW1 PM-1 S profile resion width x08 0x88 SW2 PM-1 S profile resion width x09 0x89 SWLMTCON Software limit configure data 3 0x36 0xB6 TRCOMP Trigger compare data 32 0x3A 0xBA TRCON Trigger configure data 32 0x39 0xB9 UIODATA Universal In/Out signal data 11 0x73 0xF3 UOBJ PM-1 UP-DATE Object speed data 16 0x12 0x92 URANE PM-1 UP-DATE Range data 16 0x10 0x90 URATE1 PM-1 UP-DATE Rate-1 data 16 0x13 0x93 URATE2 PM-1 UP-DATE Rate-2 data 16 0x14 0x94 URATE3 PM-1 UP-DATE Rate-3 data 16 0x15 0x95 URCP1 PM-1 UP-DATE Rate change point(urate1 0x16 0x96 16 URATE2) URCP2 PM-1 UP-DATE Rate change point(urate2 0x17 0x97 16 URATE3) UREAR PM-1 UP-DATE Slowdown/rear pulse amount data 32 0x1A 0x9A USTD PM-1 UP-DATE Start/Stop speed data 16 0x11 0x91 USW1 PM-1 UP-DATE S profile region width-1 data 15 0x18 0x98 USW2 PM-1 UP-DATE S profile region width-2 data 15 0x19 0x99 163

170 Hardware User Manual 4.0 CAMC-FS DRIVE COMMAND/SETTIN COMMAND(write only, alphabetical) NAME Description W READ WRITE CAPQCLR Caption control queue clear 0xD8 CLIMCLR Limit complete stop clear 0xFD ESTOPCMD Emergency stop - 0xAC INTENCMD Interrupt generation command 0xF9 MCONTDRV Minus continuous drive - 0xA6 MORDRV Minus original search drive 1-0xA9 MPRESETDRV Minus preset pulse drive 32-0xA5 MSCH1DRV Minus signal search-1 drive - 0xA7 MSCH2DRV Minus signal search-2 drive - 0xA8 MSPO1DRV Minus sensor positioning drive I 32 0xB1 MSPO2DRV Minus sensor positioning drive II 32 0xB3 MSPO3DRV Minus sensor positioning drive III 32 0xB5 PCONTDRV Plus continuous drive - 0xA1 PORDRV Plus original search drive 1-0xA4 PPRESETDRV Plus preset pulse drive 32-0xA0 PSCH1DRV Plus signal search-1 drive - 0xA2 PSCH2DRV Plus signal search-2 drive - 0xA3 PSPO1DRV Plus sensor positioning drive I 32 0xB0 PSPO2DRV Plus sensor positioning drive II 32 0xB2 PSPO3DRV Plus sensor positioning drive III 32 0xB4 PULSEOVER Preset/Mpg drive pulse amount override 32-0xAA SCRQCLR Script control/data queue clear 0xC8 SSTOPCMD Slow down stop - 0xAB SWRESET Software reset 0xF8 164

171 Hardware User Manual COMMAND 기능부연설명 ² lwˆ w ˆ¹(DIR) D6 D5 D4 CW CCW L H H L L H H L ² ˆ¹ ( PULSE ) w ˆ Active H Pulse 1 Pulse wˆ Active L Pulse Active H Active H CW Pulse CCW Pulse Active L Active L Active H Active H CCW Pulse CW Pulse Active L Active L 2 Pulse wˆ 1 ² wˆ ª«ª«ªª «tµ «tµ d e 1(D6, D5, D4 Ë 000 ) ª«ª«ªª «tµ «tµ ª d e 2(D6, D5, D4 Ë 001 ) 165

172 Hardware User Manual 4.0 ª«ª«ª ªª «tµ «tµ d e 3(D6, D5, D4 Ë 010 ) ª«ª«ª ªª «tµ «tµ ª d e 4(D6, D5, D4 Ë 011 ) 2 ² wˆ ª«ª««tµ ªª «tµ d e 1(D6, D5, D4 Ë 100 ) 166

173 Hardware User Manual 4.0 ª«ª««tµ ª ªª «tµ ª d e 2(D6, D5, D4 Ë 101 ) ª«ª««tµ ªª «tµ d e 3(D6, D5, D4 Ë 110 ) ª«ª««tµ ª ªª «tµ ª d e 4(D6, D5, D4 Ë 111 ) ˆ¹ ƒ D3 D2 D1 D0 ˆ¹ v Edge ELM ˆ¹ Negative Edge ELM ˆ¹ Negative Edge SLM ˆ¹ Negative Edge SLM ˆ¹ Negative Edge IN0 ˆ¹ Edge IN1 ˆ¹ Edge 167

174 Hardware User Manual IN2 ˆ¹ Edge IN3 ˆ¹ Edge ELM ˆ¹ Positive Edge ELM ˆ¹ Positive Edge SLM ˆ¹ Positive Edge SLM ˆ¹ Positive Edge IN0 ˆ¹ Edge IN1 ˆ¹ Edge IN2 ˆ¹ Edge IN3 ˆ¹ Edge z l ( Mode2 l ƒ ƒ ) 7 bit 6 bit l ECUP ˆ¹ ECDN ˆ¹ 0 0 UP/DOWN ˆ¹ l UP l DOWN l ˆ¹ 1 w l φ A l φ B l ˆ¹ 2 w l φ A l φ B l ˆ¹ 4 w l φ A l φ B l Up/Down ˆ¹ l(d7, D6 33, lj w o s ljku o s jv u{ly W X Y utx u urx Up/Down e p e Up Counter q lj w ljku o s o s jv u{ly u utx uty Y X W Up/Down e p e Down Counter q ˆ¹ l 1 w(d7, D6 34,# 168

175 Hardware User Manual 4.0 lj w ljku o s o s jv u{ly W X Y uty utx u e p e 1~ Up Counter q lj w ljku o s o s jv u{ly u utx uty Y X W e p e 1~ Down Counter q # # lj w ljku o s o s jv u{ly W X Y Z ut[ utz uty utx u e p e 2~ Up Counter q # lj w ljku o s o s jv u{ly u utx uty utz ut[ Z Y X W e p e 2~ Down Counter q 169

176 Hardware User Manual 4.0 lj w ljku o s o s jv u{ly W X Y Z [ \ ] ^ _ ut] ut \ ut [ ut Z ut Y ut X u e p e 4~ Up Counter q lj w ljku o s o s jv u{ly u ut X ut Y ut Z ut [ ut \ ut ] ] [ \ Y ut^ ^ X W e p e 4~ Down Counter q * ªp v tp x x No detect Drive end Preset dirve start Preset dirve end Continuous drive start Continuous drive end Signal search-1 drive start Signal search-1 drive end Signal search-2 drive start Signal search-2 drive end Original search drive start Original search drive end Acceleration Constant speed Deceleration IC(internal count > internal count compare data) ICE(internal count = internal count compare data) ICL(internal count < internal count compare data) EC(external count > external count compare data) ECE(external count = external count compare data) ECL(external count < external count compare data) External speed > External speed compare data External speed = External speed compare data External speed < External speed compare data Current speed > Current speed compare data Current speed = Current speed compare data Current speed < Current speed compare data Current speed > Rate Change Point 1-2 Current speed = Rate Change Point 1-2 Current speed < Rate Change Point 1-2 Current speed > Rate Change Point 2-3 Current speed = Rate Change Point 2-3 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F x ƒ 170

177 Hardware User Manual 4.0 x Current speed < Rate Change Point 2-3 0x20 Current speed = Object speed data 0x21 Current speed = Start/Stop speed data 0x22 Emergency stop 0x23 Slowdown stop 0x24 PELM signal in active level 0x25 NELM signal in active level 0x26 PSLM signal in active level 0x27 NSLM signal in active level 0x28 Off resion error occurred 0x29 Data configure error occurred 0x2A ALARM signal in active level 0x2B Emergency(0xAC) stop command executed 0x2C Slowdown(0xAB) stop command executed 0x2D ESTOP signal in HIH level 0x2E SSTOP signal in HIH level 0x2F PELM/NELM signal in active level 0x30 PSLM/NSLM signal in active level 0x31 INPOS signal in active level 0x32 IN0 input in HIH level 0x33 IN0 input in LOW level 0x34 IN1 input in HIH level 0x35 IN1 input in LOW level 0x36 IN2 input in HIH level 0x37 IN2 input in LOW level 0x38 IN3 input in HIH level 0x39 IN3 input in LOW level 0x3A OUT0 outptu in HIH level 0x3B OUT0 outptu in LOW level 0x3C OUT1 outptu in HIH level 0x3D OUT1 outptu in LOW level 0x3E OUT2 outptu in HIH level 0x3F OUT2 outptu in LOW level 0x40 OUT3 outptu in HIH level 0x41 OUT3 outptu in LOW level 0x42 Sensor Positioning drive I start 0x43 Sensor Positioning drive I end 0x44 Sensor Positioning drive II start 0x45 Sensor Positioning drive II end 0x46 Sensor Positioning drive III start 0x47 Sensor Positioning drive III end 0x48 1 st counter N-data count clear 0x49 2 nd counter N-data count clear 0x4A MARK signal in HIH level 0x4B MARK signal in LOW level 0x4C EUIO0 signal in HIH level 0x4D EUIO0 signal in LOW level 0x4E EUO1 signal in HIH level 0x4F EUO1 signal in LOWlevel 0x50 EUO2 signal in HIH level 0x51 EUO2 signal in LOWlevel 0x52 EUO3 signal in HIH level 0x53 EUO3 signal in LOWlevel 0x54 EUO4 signal in HIH level 0x55 EUO4 signal in LOWlevel 0x56 + Software LIMIT 0x57 - Software LIMIT 0x58 Software LIMIT 0x59 Trigger enable 0x5A x ƒ 171

178 Hardware User Manual 4.0 x Interrupt generated by any source interrupt generated by command F9 Preset triangular drive start Drive busy output in HIH level Drive busy output in LOW level Just execution(in Queue command) 0x5B 0x5C 0x5D 0x5E 0x5F 0xFF x ƒ 172

179 Hardware User Manual 4.0 ô Û Ñ úñä àá. î ä, ÕÑ,, ö ø Ð æ â Ï ààá. è, ÕÑ,, ö éà ÐÑã Ñ ãï ô ÔîÐ ã äàá. á Óù à Ð àá. Ó Óò à úãï, ô è üüã ( ) ô ô à è Û á( Õ, ÕÑ, ú Õ ú, æ ú éà áñ øù) éà áñ ô ïã ú äðû, Ð éà ã äðû, ä àá. ( ) ô ú Ñîä Ó, Ó, Ó éà Õ Ó æ ú àá. ô Ó Ñ æì ( ) ïü Ó Ð ô ï Ñä Óò, ô Ñ Ó Ð í Ó, Ó éà Õ Ó æ á è Óã à á. 173