SIGNAL INTEGRITY This chapter is contributed by Raymond Y Chen, Sigrity, Inc, San Jose, California E-mail: chen@sigritycom,, 1 2 2 SI 3 21 SI 3 22 SI 3 23 Electronic Packaging SI4 3 SI 5 31 SI 5 32 Principles of SI Analysis 7 4 SI 9 41 Rise Time SI 9 42 Transmission Lines, Reflection, Crosstalk 9 43 Power/Ground Noise 10 5 Modeling and Simulation13 51 EM Modeling Techniques 13 52 SI Tools 14 53 IBIS 15 6 SI 17 References 19 7 SI Jargon 21 Fall Time 21 Flight Time 21 ISI (Inter Symbol Interference) 21 Jitter 21 Overshoot/Undershoot 21 Period 21 Push-out/Pull-in 21 Ringback 21 Rise Time 21 Skew 21 Tco (Clock to output valid delay) 22 Th (Signal hold time to clock input) 22 Tsu (Signal setup time to clock input) 22 Vil/Vih (Voltage input low/high) 22 Vol/Voh (Voltage output low/high) 22 Vt (Threshold voltage) 22 8 Resource Center23 81 Internet 23 82 Papers 23 83 Books (in alphabetical order) 24
1, signal integrity, signal integrity, EMI/EMC, signal integrity,,,, signal integrity Signal Integrity(SI) timing quality( :shape)?,,? Signal integrity, 1 0, Receiver, Vih 1, Vil 0 Figure 1 Figure 2 0 1 (sampling process) Figure 3 clock signal,,, Figure 2 ringing( ), Voltage Voltage Maximum Overshoot Gray Zone Vih Vil Ringing Time Figure 1 Ideal waveform at the receiving gate Time Figure 2 Real waveform at the receiving gate T1 T2 Common Clock Data at Driver t valid(max) Data1 t valid(min) Data2 Data at Receiver t setup Data1 t hold t flight Data2 Figure 3 Data sampling process and timing conventions 2
2 SI 21 SI Timing Signal timing, threshold, noise : Reflection Noise Due to impedance mismatch, stubs, vias and other interconnect discontinuities Crosstalk Noise Due to electromagnetic coupling between signal traces and vias Power/Ground Noise Due to parasitics of the power/ground delivery system during drivers simultaneous switching output (SSO) It is sometimes also called Ground Bounce, Delta-I Noise or Simultaneous Switching Noise (SSN) SI, Electromagnetic Compatibility Electromagnetic Interference (EMC/EMI) SI noise margin Vih Vil ; (quiet) Vil Vih ; power/ground, logic error, data drop, false switching, noise prototype,, [1] noise,,, 22 SI, timing quality, die( ) off-chip drivers c4 wire-bond connection single chip carrier multi-chip module(mcm) solder bumps, (PCB), daughter card, mother board backplane ASIC(Application Specific Integrated Circuit), memory module termination PCB Figure 4 trace, via, power/ground plane signal integrity packaging interconnection 3
Figure 4 Signal Integrity Challenges Appear in IC Packages and PCBs 23 Electronic Packaging SI / clock GHz rise-time 200ps, 10GHz signal integrity : 1960 50 µm 018 µm, 01 µm :, pico-second,, timing budget micron microprocessor,, Signal Integrity (chip carriers and PCBs) 4
3 SI 31 SI Signal integrity,, /, SI pre-layout SI prototype, postlayout SI Figure 5 SI, SI,, SI preroute analysis, postroute analysis System Requirements Architecture/ Schematic Interconnect Characterization Select I/O buffer, package, board, and connector for performance requirement Generate Physical Design Guidelines Noise budget, timing budget assessment Component Placement Constraint Driven Layout Final placement, Critical route, autoroute Verification Prototype, lab measurement SI analysis Comparison studies SI analysis Find solution space by simulating corner cases SI analysis Pre-layout analysis SI analysis Simulation of reflection, crosstalk, SSN SI analysis Post-layout simulation NO Meet SI conditions YES Successful Design Figure 5 SI analysis in the design flow 5
Preroute, SI I/Os, clock distributions, chip package types, component types, board stackups, pin assignments, net topologies, termination strategies, batch SI, SI component routing constraint driven SI Preroute constraint driven SI layout signal integrity noise timing budget /routing constraint, noise level, preroute SI /route, layout, postroute SI SI constraint reflection noise, ringing, crosstalk, ground bounce SI, preroute SI postroute layout, SI,, signal integrity layout,, SI, signal integrity routing constraint, SI,, (Figure 6 ) SI, SI SI, SI layout [2] SI vias, traces, plane stackup interconnection, driver/load termination, SI layout, (placed) (routed) SI, post-layout SI, SI, layout SI (routing),, SI routed system SI, layout, SI SI 6
32 Principles of SI Analysis :,, (EM) SI EM field [3] SI reflection, crosstalk, ground bounce EM, EM SI, Figure 7, via_a, via ( ) via, via,,,,,, EM,, interconnect model, SI SI Figure 7 Multi-layer packaging structure SPICE,, capacitor, inductor SI, interconnect, PCB trace (lumped circuit model), trace,, trace, R-L-C (distributed circuit model) trace, rise time,, PCB FR-4 3cm stripline trace 200ps 33MHz, rise time 5ns, trace, 500MHz 300ps rise time, trace 200ps, trace, (ever-decreasing) rise time SI 7
15cm 15cm PCB power ground plane capacitor Capacitor C= era/d,,, DC, rise time 300ps, power/ground, power/ground 2,, power/ground, capacitor 2 R-L-C power/ground,, rise time interconnec t SI,,, ( : ), trace R-L-C ladder (transmission line theory) ; power/ground radial transmission line theory waveguide, rise time SI rise time 8
4 SI 41 Rise Time SI, rise/fall time nano-second,,, micron, rise/fall time pico-second micron, SI dv/dt di/dt, rise time ringing, crosstalk, power/ground switching noise noise clock rise time, SI, 20Mhz clock, rise time 200MHz SI 42 Transmission Lines, Reflection, Crosstalk PCB, trace (Figure 8a) (Figure 8b) (Figure 8c) via (Figure 8d) Figure 8 A B R(resistance), L(inductance), G(conductance), C(capacitance), ( ),,, 2D static EM field solver( ) SI, interconnect,,, noise overshoot, undershoot, ringing noise routing layer, (, ), Trace (degassing holes, via holes ),, (stubs), trace,,, noise, trace (trace ), stubs, termination (,, RC, Thevenin), 9
EM coupling crosstalk noise, crosstalk timing (even mode switching,,, ), sampling window Crosstalk rise time,, Crosstalk,, ground guarding band,, trace Trace crosstalk, via coupling [4] 43 Power/Ground Noise Power/ground noise noise budget 30% Power/ground SI, EM PCB, via power/ground power [5] (core-logic, off-chip drivers) power ground, simultaneous switching noise (SSN), Delta-I noise, power/ground bounce SSN power/ground return path coupling, / common mode noise, IC I/O count, 200ps transition time, 20A, SSN,, SSN, power/ground Figure 9 (a) Effective inductor model (b) Wire antenna model (c) Inductance/capacitance mesh model 10
Principles of SI Analysis, power/ground Power/ground SSN EM SSN, wave propagaiton, reflection, edge radiation, via coupling, package resonance, inductor power/ground [6][7] inductor (Figure 9a), power/ground wave propagation Method of Moments(MoM) wire-antenna (Figure 9b) power/ground [8] wave propagation via interaction,, 2D capacitor/inductor (Figure 9c) power/ground, capacitor inductor SPICE,, 3 finite-difference time-domain(fdtd) finite element method(fem) full-wave EM field solver, 3 EM field solver ( ), power/ground SSN : 1 FEM, MoM, Partial Element Equivalent Circuit method(peec) EM field power/ground ( ) 2 Driver/receiver( behavioral model) signal trace(transmission line model) power/ground SPICE 3 SSN SPICE : 1 PCB power/ground 2 EM power/ground via power/ground 3 EM power/ground 4 5 layout 6 Power/ground signal, power/ground signal power/ground noise simulation, EM field solver Field solver circuit solver [9][10] power/ground noise power/ground, Figure 7 Figure 10 11
Circuit Solver Circuit Solver Plane Solver 1 Plane Solver 2 Plane Solver 3 Circuit Solver Circuit Solver Figure 10 Power/ground noise analysis using combined field analysis and circuit analysis Power/ground SSN decoupling, stack-up, decoupling capacitor(decap), Decap power/ground noise SI [11][12] 12
5 Modeling and Simulation 51 EM Modeling Techniques SI EM [13][14] Field solver SI SI 1 Boundary Element Method (BEM) and Method of Moment (MoM), the same methods with different na mes Integral equation formulation; Unknowns confined to conductors; Require construction of Green s Function that can be complicated to generate for complex structur es Not well suited for inhomogeneous dielectric material; Require solving dense matrix 2 Finite Difference Time Domain (FDTD) method, a general purpose and versatile approach for arbitrary inhomogeneous geometries Differential equation formulation; Direct time domain solution of Maxwell s equations ; Unknown throughout entire region Computer intensive; No matrix inversion 3 Finite Element Method (FEM), a general purpose and versatile approach for arbitrary inhomogeneous geometries Laplace/Helmholtz equation formulation; Computer intensive; Sparse matrix 4 Partial Element Equivalent Circuit (PEEC) approach, a simplified and approximate version of MoM Integral equation formulation from magneto-quasistatic analysis; Unknowns confined to conductors 13
52 SI Tools SI : single/couple RLGC 2D field solver; wirebonds, vias, metal planes 3D field solver; driver receiver behavioral modeling (timing ) layout Table 1 SI Company Tool Function Ansoft Applied Simulation Technology Cadence SI 2D SI 3D PCB/MCM Signal Integrity Turbo Package Analyzer ApsimSI ApsimDELTA-I SPECCTRAQuest 2D static DC EM simulation extracts inductanc e and capacitor 3D static DC EM simulation extracts resistanc e, inductance and capacitance PCB/MCM pre and post route SI analysis Package RLGC extraction Reflection and Crosstalk simulation for lossy co upled transmission lines Delta-I noise simulation SI simulation: transmission line simulation, pow er plane builder HP Eesof Picosecond Interconnect Modelling Suite Frequency-domain and time-domain simulation for coupled lines and I/O buffers Hyperlynx (PADS) HyperSuite Single/couple transmission line simulation INCASES (Zuken) SI-WORKBENCH Lossy coupled transmission line simulation Mentor Graphics IS_Analyzer Delay, Crosstalk simulation Quantic EMC BoardSpecialist Plus Delay, Crosstalk simulation Sigrity SPEED97/SPEED2000 Power/ground noise simulation with couple los sy transmission line analysis Viewlogic Systems XTK Couple lossy transmission line analysis (Innoveda) AC/Grade Power/ground modeling Table 1 Major Sigrity Integrity tools 14
53 IBIS Input/Output Buffer Information Specification (IBIS) (IC) (I/O) IBIS software-parsable IBIS, SI, driver receiver, crosstalk power/ground bounce (noise) signal integrity, PCB I/O,, IBIS (behavioral model) [15] IBIS, IBIS driver rise/fall time DC I/O IBIS I-V driver SI [16][17] PWR pin PWR_Clamp pin Upper Device Package Parasitics A L_pkg R_pkg Device Pin Lower Device C_comp C_pkg GND pin GND_Clamp pin Figure 11 IBIS representation of an I/O buffer Figure 11 IBIS power/ground clamp, die capacitance(c comp ) I/V (the values of the lead inductance (L pkg ), resistance (R pkg ) 15
and capacitance(c pkg )), IBIS upper/lower device DC I/V, load Z meas (normally a passive resistor) (high-to-low) (low-tohigh) IBIS, Resource Center IBIS 16
6 SI SI, SI,,,,, SI,, SI signal/power/ground/signal stack-up 4 PCB DSP 500ps edge rate Routing, trace coupling noise crosstalk constraint, driver coupling noise clock net, clock net trace, crosstalk constraint violation (Figure 12 clock net,, ), post-layout crosstalk, clock trace trace coupling, pickup noise? transition via decap chip clock switching signals Figure 12 Illustration of the problematic clock net on the PCB during simultaneous switching output Noise pick-up simultaneous switching output(sso), power/ground noise SI PCB 3D, PCB EM field Sigrity, Inc(Resource Center, SI software vendor) SI SPEED97 Figure 13 151ns power ground, Figure 14 10ns power ground noise (Figure 14), on-board decoupling capacitor, Figure 14 power/ground noise swing, clock via Clock trace routing layer, power ground via power/ground noise Figure 15 clock via simultaneous switching noise Coupling noise decoupling capacitor clock via, power/ground noise, clock coupling noise noise margin Decoupling capacitor SI PCB field SI, 17
Figure 13 Spatial noise distribution between the power and the ground plane at 151 ns Figure 14 Spatial distribution of the peak noise voltage between the power and the ground plane within 10ns 18
Figure 15 Clock net picks up simultaneous switching noise at the via location References [1] Tai-Yu Chou, Signal Integrity Analysis in ASIC Design, ASIC & EDA, pp70-81, May 1994 [2] Rob Kelley, Choosing the Right Signal Integrity Tool, Electronic Design, pp 78-80, September 1995 [3] Lisa Maliniak, Signal Analysis: A Must For PCB Design Success, Electronic Design, pp 69-81, September 1995 [4] Jin Zhao and Jiayuan Fang, Significance of Electromagnetic Coupling Through Vias in Electronics Packaging, IEEE 6 th Topical Meeting on Electrical Performance of Electronic Packaging, Conference Proceedings, p 135-138, Oct, 1997 [5] W Becker, B McCredie, G Wilkins, and A Iqbal, Power Distribuiton Modeling of High Performance First Level Computer Packages, IEEE 2nd Topical Meeting on Electrical Performance of Electronic Pack aging, Conference Proceedings, pp 203-205, Oct 20-22, 1993, Monterey, CA, USA [6] M Bedouani, High Density Integrated Circuit Design: Simultaneous Switching Ground/Power Noises Calculation for Pin Grid Array Packages, 43rd Electronic Components & Technology Conference, Conference Proceedings, pp 1039-1044, June 1-4, 1993, Orlando, FL, USA [7] R Raghuram, D Divekar, and P Wang, Efficient Computation of Ground Plane Inductances and Currents, IEEE 2nd Topical Meeting on Electrical Performance of Electronic Packaging, Conference Proceedings, pp 131-134, Oct 20-22, 1993, Monterey, CA, USA [8] AR Djordjevic and TK Sarkar, An Investigation of Delta-I Noise on Integrated Circuits, IEEE Trans Electromagn Compat, vol 35, pp 134-147, May 1993 19
[9] Y Chen, Z Chen, Z Wu, D Xue, and J Fang, A New Approach to Signal Integrity Analysis of High-Speed Packaging, IEEE 4th Topical Meeting on Electrical Performance of Electronic Packaging, Conference Proc, pp 235-238, Oct 2-4, 1995, Portland, Oregon [10] Y Chen, Z Wu, A Agrawal, Y Liu, and J Fang, Modeling of Delta-I Noise in Digital Electronics Packaging, 1994 IEEE Multi-Chip Module Conference, Conference Proc, pp 126-131, Mar 15-17,1994, Santa Cruz, CA [11] Y Chen, Z Chen, and J Fang, Optimum Placement of Decoupling Capacitors on Packages and Printed Circuit Boards Under the Guidance of Electromagnetic Field Simulation, 46th Electronic Components & Technology Conference, Conference Proc, pp 756-760, May 28-31, 1996, Orlando, Florida [12] Larry Smith, Raymond Anderson, Doug Forehand, Tom Pelc, and Tanmoy Roy, Power Distribution System Design Methodology and Capacitor Selection for Modern CMOS Technology, IEEE Transactions on Advanced Packaging, pp 284-291, August, 1999 [13] Dale Becker, Tools and Techniques for Electromagnetic Modeling of Electronic Packages, IEEE Topical Meeting on Electrical Performance of Elec tronic Pack aging, Short Course, October 1996 [14] Andrew F Peterson, Computer-Aided Engineering Tools for Electronic Packaging Analysis, IEEE Topical Meeting on Electrical Performance of Elec tronic Pack aging, Short Course, October 1996 [15] W Hobbs, A Muranyi, R Rosenbaum and D Telian, Intel Corporation, IBIS: I/O buffer Information Specification Overview, http://wwwvhdlorg, January 14, 1994 [16] Peivand F Tehrani, Yuzhe Chen, Jiayuan Fang, Extraction of Transient Behavioral Model of Digital I/O Buffers from IBIS, IEEE Electronic Components & Technology Conference, Conference Proceedings, May 1996 [17] Ying Wang and Han Ngee Tan, The Development of Analog SPICE Behavioral Model Based on IBIS Model, Proceedings of the Ninth Great Lakes Symposium on VLSI, March, 1999 20
7 SI Jargon Fall Time Time for a signal to change from a logic high state to a logic low state Flight Time Time difference between the signal at the driver reaching Vref with a reference/test load and the signal at the receiver reaching Vref Flight time is also known as bus loss, since it historically was used to derate the spec Tco timing to account for the difference between the spec load and the actual system load impact on circuit timing ISI (Inter Symbol Interference) ISI refers to the interactions between the logic value/symbol from the previous switching cycle and the symbol traveling on the same channel of the current cycle ISI occurs as a result of energy stored in the channel summing with a latter unrelated signal It is dependent upon multi-cycle reflections and affects the rising/falling edge and settling characteristics Jitter Jitter refers to deviation in time between edges of individual signals that are periodic For example, clock jitter is the time deviation from the clock period (the clock period may be compressed or expanded) Jitter can also affect source-synchronous circuits that have transactions spanning multiple cycles or edges, and it can also be applied to differences between rise and fall edges of a signal Overshoot/Unde rshoot Overshoot/Undershoot occurs when a signal transition goes beyond the Vol/Vil for a falling edge and Voh/Vih for a rising transition Period For common clock circuits and multi-clock cycle transactions, period refers to a single clock or strobe cycle duration from a rising edge transition to the next rising edge transition (or falling edge to falling edge) For example, a 1GHz cycle period is 1ns duration Push-out/Pull-in Push-out and pull-in refer to the difference in signal flight time due to signal coupling effects and signal return path discontinuities Comparing with the delay of single-bit switching, push-out means all the drivers switching at the same direction (even mode), whereas pull-in means all the other drivers switching at the opposite direction (odd mode) Ringback Ringback is when a signal rising edge crosses beyond the Vih threshold and re-crosses threshold again before settling beyond Vih Depending upon the magnitude and duration of the re-crossing, the settling time may need to be calculated from the final crossing of Vih This also applies to signal falling edges recrossing Vil before settling below Vil For a clocked signal, ringback is typically allowed as long as the signal settles beyond the Vih/Vil threshold to satisfy the setup timing requirement Rise Time Rise time is the time for a signal to change from a logic low state to logic high state This may also include partial transitions as well (10% ~ 90% amplitude change, or rise through specific voltage thresholds, such as 05V ~ 1V) Skew Skew is the difference between two or more signals in their delay at a specified voltage threshold For a common clock circuit, skew may be critical between a driver and receiver clock to determine setup or hold time impact For a source-synchronous system this can apply to strobe vs signal or strobe vs strobe 21
Tco (Clock to output valid delay) Tco is the delay between component clock input (at a specified input voltage threshold) and a valid signal output (at a specified reference load and output voltage threshold) This delay for system design is typically specified at component package pins or input/output pads Th (Signal hold time to clock input) This is the time required for the input signal to remain valid (above Vih for rising and below Vil for falling) beyond the input clock edge transition of the receiving component Hold time is used both at receiving components for common clock and source-synchronous timing Tsu (Signal setup time to clock input) This is the time required for the input signal to be settled about Vih (rising) or below Vil (falling) at the receiving component before its input clock edge transition Setup time is used both at receiving components for common clock and source-synchronous timing Vil/Vih (Voltage input low/high) Vil and Vih refer respectively to the maximum low input voltage for a high to low input transition and minimum high input voltage for a low to high input transition The input signal needs to remain stable beyond these voltage limits to be guaranteed latched in Vol/Voh (Voltage output low/high) Vol and Voh are the low and high, respectively, voltage levels guaranteed at the driver output reference point for the driven signal Vt (Threshold voltage) Vt refers to the input threshold voltage which determines whether a high or low state is sensed at the receiver input In some cases, an input threshold is specified with an additional noise margin or overdriver region specified for timing specification or signal condition requirements 22
8 Resource Center 81 Internet SI-LIST (email forum and web archives for SI discussions with 1000+ participants) Email Group: to subscribe from si-list or si-list-digest: send e-mail to majordomo@silabengsuncom In the BODY of message put: SUBSCRIBE si-list or SUBSCRIBE si-list-digest, for more help, put HELP Web Archives: si-list archives are accessible at http://wwwqslnet/wb6tpu IBIS IBIS-USERS : email forum for IBIS related discussions To participate in IBIS discussions, send your email address to ibis-request@vhdlorg Official IBIS Web site: http://wwweiaorg/eig/ibis/ibishtm Other Internet portals that provide SI related information (in alphabetical order) wwwbogatinenterprisescom wwwchipcentercom wwwdacafecom wwwednmagcom wwweetimescom wwwpcdmagcom wwwsigconcom SI Software Vendor (in alphabetical order) Ansoft (wwwansoftcom) Applied Simulation Technology (wwwapsimtechcom) Cadence (wwwcadencecom) Hyperlynx (wwwhyperlynxcom ) Incases (wwwincasescom) Mentor Graphics (wwwmentorgcom ) Quantic EMC (wwwquantic-emccom ) Sigrity (wwwsigritycom) Viewlogic (wwwviewlogiccom) 82 Papers IEEE Conference Proceedings: EPEP (Electrical Performance of Electronic Package) ECTC (Electronic Components and Technology Conference) EMC (Electromagnetic Compatibility) Symposium IEEE Journal: CPMT (Components, Packaging and Manufacturing Technology) wwwcpmtorg MTT (Microwave Theory and Techniques) wwwmttorg EMC (Electromagnetic Compatibility) wwwemcsorg 23
83 Books (in alphabetical order) Analysis of Multiconductor Transmission Lines, Clayton R Paul, John Wiley & Sons, 1994 Circuits Interconnects, and Packaging for VLSI, H B Bakoglu, Addison Wesley, 1990 Computer Circuits Electrical Design, Ron Poon, Prentice Hall, 1995 Digital Systems Engineering, William J Dally, John W Poulton, Cambridge University Press, 1998 High-Speed Digital Design: A Handbook of Black Magic, Howard W Johnson and Martin Graham, Prentice Hall, 1993 Introduction to Electromagnetic Compatibility, Clayton R Paul, John Wiley Interscience, NY, 1992 Transmission Lines in Computer Engineering, Sol Rosenstark, McGraw-Hill, 1994 24