Dual- Gate FET T he A naly s is and A pplication of Nonlinear Characteris tics of Dual- Gate FET 199 9
Dual- Gate FET T he Analysis and Applications of Nonlinear Characteris tics of Dual- Gate FET 1999 12
1999 12
Abstract. 1. Dual- Gate FET DC RF 2 2.1. Dual- Gate FET 2 2.1.1. Dual- Gate FET mode 2 2.1.2. Dual- Gate FET 9 2.1.3. Gate 2 11 2.2. Harmonic Balance Method 14 2.2.1. Harmonic Balance Analysis 14 2.2.2. Generalized Harmonic Balance Analysis 24. 26. 29 4.1. FET 30 4.1.1. mode 30 4.1.2. 31 4.2. Variable Gain Amplifier 33 4.2.1. 33 4.2.2. 33 4.3. 36. 38 39
< > 1. Dual- Gate FET 2 2. VDS1 3 3. Dual- Gate FET bi- dimensional DC 4 4. Dual- Gate FET 4 mode 5 5. VG2 mode 7 6. VGS1 mode 8 7. VGS1/VG2 VDS mode 8 8. Dual- Gate MOSFET 9 9. Dual- Gate FET 10 10. 2 11 11. 3 12 12. 13 13. 14 14. 18 15. Harmonic Balance Method Algorithm 22 16. Predistortion 27 17. 28 18. BF904 Dual- Gate MOSFET Model 29 19. VDS=6V BF904 mode 30 20. Gate 2 S11 S22 31 21. Gate 2 S21 32 22. Gate 2 S12 32
23. 7.5dB 33 24. - 2.5dB 34 25. VG2 34 26. P1dB simulation 35 27. IP3 simulation 35 28. IP3 36 29. 37 30. 37 31. 37
ABST RACT In this thesis, a simple method of identifying operating modes in Dual- Gate FET and reducing the variations of S- parameters due to termination conditions of Gate 2 is suggested. Based on the proposed method, the variable gain amplifier, w hose input as w ell as output return losses are below - 20dB w ithin the 10dB gain variation, is designed and fabricated. In order to investigate the nonlinear characteristic of the fabricated amplifier, nonlinear circuit analysis is performed using the w ell- know n harmonic balance analysis method. Based on the predicted nonlinear characteristics, the IP3 as w ell as P1dB of the designed variable gain amplifier is analyzed. T he experimental results of the nonlinear characteristics of the variable gain amplifier agree w ith the theoretical results. An IM generator, applicable to the predistortion linearizer, w hich is made of tw o hybrids and tw o variable gain amplifiers show s that at least 20dB of the main signals are rejected below the third order IM signals w ith the 15dB of dynamic range up to 12dBm/tone.
Dual- Gate FET, Gate 2 S- parameter. 10dB - 20dB (Variable Gain Amplifier),. Harmonic Balance, HPA(High Pow er Amplifier) Predistotor, 3 20dB Dynamic range 12dBm/tone 15dB.
. Dual- Gate FET Gate 4, 70., (VGA)[1][2], [3][4], phase shifter[5].,,., Gate 2, Drain, P1dB,, S- parameter,., Harmonic.,, Dual- Gate FET Single Gate FET.,. Dual- Gate FET DC, mode, Gate 2 RF, =0,, Gate 2 bias S- parameter,. Harmonic Balance Gate 2 P1d,, HPA(High Pow er Amplifier) Predistortion (IM Generator). - 1 -
. Dual- Gate FET DC RF 2.1. Dual- Gate FET 2.1.1. Dual- Gate FET mode[6][7] Dual- Gate FET 1 (b) FET cascode. Dual- Gate FET FET, VGS1, VG2, VDS, ID, D1 VDS1. VDS1 FET, Dual- Gate FET. VDS1 2. 1. Dual- Gate FET - 2 -
2. VDS1 2 RC, (2.1.1). R c l 2 l 1 + l 2 * V DS I D V GS 1 = V GS2 0. 8V at V DS 0 (2.1.1) l 1, l 2 FET channel length. D V D - I D R C, V DS1 = V D - 2 I D R C. OP amp inverting input i 1 = I D R C R, i 2 = V O - ( V D - I D R c ) R (2.1.2) R ( i 1 + i 2 ) = V D - I D R C (2.1.3) (2.1.2) (2.1.3) V O - ( V D - I D R c ) = V D - 2 I D R C (2.1.4) OP Amp D VDS1. VDS1 3 bi- dimensional DC. - 3 -
3. Dual- Gate FET bi- dimensional DC channel length, VDS1. FET mode. FET cascode 4 4 mode. FET, I D1 = I D2 = I D (2.1.5) V DS = V DS 1 + V DS2 (2.1.6) V GS2 = V G2 - V DS1 (2.1.7) FET. I D = 0 V GS - V T < 0 = ( V GS - V T ) 2 0 < V GS - V T < V DSsat = [ 2 ( V GS - V T )V DS - V 2 DS ] 0 < V DS sat < V GS - V T (2.1.8) - 4 -
4. Dual- Gate FET 4 mode mode, mode A : FET, common Source common Gate cascode. V DS1 > V DS1sat, V DS2 > V DS2sat (2.1.9) ( V GS1 - V T ) 2 = ( V GS2 - V T ) 2 (2.1.10) V GS1 = V GS 2, (2.1.8) V DS1 = V G2 - V GS1 (2.1.11) I D = ( V GS1 - V T ) 2 (2.1.12). VDS1 ID, - 5 -
VGS1 VG2. Drain current ID VGS1 VDS1 T 2 VGS2. mode B : T 1, T 2 T 1 T 2 Source. 0 < V DS1 < V DS1sat, V DS2 > V DS2sat I D1 = I D2 = I D I D = [ 2 ( V GS1 - V T )V DS1 - V 2 DS1 ] = ( V GS 2 - V T ) 2 = ( V G2 - V DS1 - V T ) 2 VDS1 2 V DS1 = 0. 5[ ( V GS1 - V T ) + V G2 - V T - ( ( V GS 1 - V T ) + V G2 - V T ) 2-2( V G2 - V T ) 2 ] I D = ( V G2 - V T - V DS 1 ) 2 VDS1 VGS1 VG2. Drain current ID VDS, T 1 (RDS1) VGS1, Drain current ID VG2. mode C : T 2, T 1. V DS1 > V DS 1sat, V DS2 < V DS 2sat V DS1 = V G2 - V T - ( V DS + V T - V G2 ] 2 + ( V GS 1 - V T ) 2 I D = ( V GS1 - V T ) 2-6 -
mode Drain current ID VDS VG2, VGS1. mode D : T 1 T 2. 0 < V DS1 < V DS1sat, 0 < V DS 2 < V DS2sat V DS1 = 0. 5( V GS1 + V G2 ) - V T - [ V DS + V T - 0. 5( V GS1 + V G2 )] 2 - V DS ( V T - V GS1 + 0. 5V DS ) I D = [ 2 ( V GS 1 - V T ) V DS1 - V 2 DS 1] Drain current ID VDS, VG2, VGS1. DC mode 5 6, VGS1 VG2 7. 5. VG2 mode - 7 -
6. VGS1 mode 7. VGS1/VG2 VDS mode - 8 -
2.1.2. Dual- Gate FET [2][8] 8. Dual- Gate MOSFET 8 Dual- Gate MOSFET. Dual- Gate FET Single- Gate Gate Gate Drain. 9. Gate 2 RF, FET, cascode Amplifier. cascode Amplifier Single- Gate FET feedback,. S12 S22. FET vds RDS2 feedback, common Gate Amplifier 1 g m 2, - 9 -
1 1 / / R g DS1 m 2 g m 2, common Source Amplifier, 1. T 1 Gate vgs1 Drain vds1. Gate 2, CGS2 vds1, gm2 gm1. CDS v ds - v ds1 * R DS2 1 g m 2 = v ds1 = v ds v ds1 = 1 + g m * R DS vds1 vds Cgd1 feedback., Cgd2 Gate 2 RF feedback. vds vds1 T 1 RDS1. 9. Dual- Gate FET - 10 -
2.1.3. Gate 2 [2] Dual- Gate FET 4, Source 3. Variable Gain Amplifier Dual- Gate FET Gate 1 RF, Gate 2 gm1., Gate 2. 10 2 L b 2 = a ' = - 1 L a 2 = S 21 a 1 + S 22 a 2 (2.1.13) a 2 = ( - 1 L - S 22 ) - 1 S 21 a 1 (2.1.14) b 1 = S 11 a 1 + S 12 a 2 = ( S 11 + S 12 ( - 1 L - S 22 ) - 1 S 21 )a 1 (2.1.15) 2, 1 S- parameter 3 2 S- parameter. 10. 2-11 -
11. 3 3 S- parameter 3*3, 2*2 S 11 S 12 S 13 S 21 S 22 S 23 - - + - = [ [ S 11 ] [ S 12 ] ] [ S 21 ] [ S 22 ] S 31 S 32 S 33 (2.1.16) (2.1.15) b [ 1 = ( [ S b 2 ] 11 ] + [ S 12 ]( = [ [ S 11 S 12 ] + [ S 13 ] S 21 S 22 S 23 ( [ - 1 3 - [ S ]) - 1 [ S ]) [ a 1 ] 22 21 a 2-1 3 ] - [ S ]) - 1 [ S S ]] [ a 1 ] 33 31 32 a 2 = S 11 + S 21 + S 13 S 31 3 1- S 33 3 S 12 + S 23 S 31 3 1- S 33 3 S 22 + S 13 S 32 3 1- S 33 3 S 23 S 32 3 1- S 33 3 [ ] a 1 a 2 (2.1.17) 3 S- parameter,,, 3. Variable Gain Amplifier port 3 parameter 3=0, (2.1.17) - 12 -
(2.1.18) port 3 b [ 1 = b 2 ] [ S 11 S 12 ] a S 21 S 22 [ 1 ] a 2 (2.1.18) 12 Gate 2 =0 50. DC, RF =0 50 DC Block C. 12. Gate 2 50-13 -
2.2. Harmonic Balance Method[9][10][11] Harmonic Balance Volterra- Series. Harmonic Balance. P1dB Harmonic, Mixer (LO) (RF), Harmonic Balance, Large- Signal- Small- Signal. Harmonic Harmonic Balance. Volterra- Series,. Generalized Harmonic Balance.,.. Dual- Gate FET Gate 2 bias P1dB, Harmonic Balance Generalized Harmonic Balance. 2.2.1. Harmonic Balance Analysis Harmonic Balance Analysis, FET Harmonic, P1dB,. - 14 -
,., FFT. 13. 13. port, port. Z S ( ) Z L ( ),. I/V,. - 15 -
Harmonic Balance Method 13 Kirchhoff' s Current Law port Harmonic. N, K Harmonic, I 1, 0 I 1, 1 : I 1, K I 2, 0 I 2, 1 : I 2, K : I N, K + I 1, 0 I 1, 1 : I 1, K I 2, 0 I 2, 1 : I 2, K : I N, K = 0 (2.2.1) I n, k port n k harmonic, Y- matrix port. I n, k port. I 1 Y 1, 1 Y 1, 2... Y 1, N Y 1, N + 1 Y 1, N + 2 V 1 I 2 Y 2, 1 Y 2, 2............ V 2 : = : : : : : : : (2.2.2) I N + 1 Y N + 1, 1 Y N + 1, 2... Y N + 1, N Y N + 1, N + 1 Y N + 1, N + 2 V N + 1 I N + 2 Y N + 2, 1 Y N + 2, 2... Y N + 2, N Y N + 2, N + 1 Y N + 2, N + 2 V N + 2-16 -
(2.2.2) vector I (2.2.3) subvector. I n, 0 I n, 1 I n = I n, 2 : (2.2.3) I n, K I n n port harmonic vector. vector V subvector. V n, 0 V n, 1 V n = V n, 2 : (2.2.4) V n, K (2.2.2) Y- matrix (2.2.3) (2.2.4) (N+2)*(N+2) K*K submatrix. submatrix p p., diagonal matrix. p, Y- matrix - 17 -
Y m, n = diag [ Y m, n ( k w p ) ], k = 0, 1, 2..., K (2.2.5) Y m, n ( 0) 0 0... 0 0 Y m, n ( w p ) 0... 0 Y m, n = 0 0 Y m, n ( 2w p )... 0 : : :... : 0 0 0... Y m, m ( K w p ) (2.2.6) subvector V N + 1 V N + 2 = V b 1 V S 0 : 0 V b 2 0 0 : 0 (2.2.7) V b 1, V b 2 bias bias, Vs. N+2, N,, N port - 18 -
I 1 Y 1, N + 1 Y 1, N + 2 Y 1, 1 Y 1, 2... Y 1, N V 1 I 2 : = Y 2, N + 1 Y 2, N + 2 : V N + 1 V N + 2 + Y 2, 1 Y 2, 2... Y 2, N : :... : V 2 : (2.2.8) I N Y N, N + 1 Y N, N + 2 Y N, 1 Y N, 2... Y N, N V N I = I S + Y N N V (2.2.9) (2.2.8) 14. 14. - 19 -
capacitance conductance. capacitance, capacitance charge (2.2.10) port q n ( t) = f qn ( v 1 ( t), v 2 ( t),..., v N ( t) ) (2.2.10) (2.2.10) fourier- transform port capacitance charge vectors. ( q n ( t ) ) - - - - - - - - - Q n Q = Q 1 Q 2 Q 3 : Q N = Q 1, 0 Q 1, 1 : Q 1, K Q 2, 0 : Q 2, K : Q N, K (2.2.11) capcitance charge w aveform, j. i c, n ( t) = d q n ( t) dt - j k w p Q n, k (2.2.12) I c = j Q (2.2.13) - 20 -
capacitance (2.2.13). main diagonal (0, 1, 2,... K) p N diagonal matrix. = 0 0 0...... 0 0 0 0 0 w p 0...... 0 0 0 0 0 0 2w p 0... 0 0 0 0 : : : :... 0 0 0 0 0... 0 K w p 0... 0 0 0 : : : 0 0 0... 0 0 : : :... 0 w p 0... 0 0 0 0... : : : : 0 0 0 0... : : : : 0 0 0 0.......... 0 K w p (2.2.14) conductance i g, n ( t) = f n ( v 1 ( t), v 2 ( t), v 3 ( t),... v n ( t) ) (2.2.15) ( i g, n ( t ) ) - - - - - - - I G, N (2.2.16) I G, 1 I G = I G, 2 : (2.2.17) I G, N (2.2.9), (2.2.13), (2.2.17) (2.2.1) - 21 -
F ( V ) = I S + Y N N V + j Q + I G = 0 (2.2.18) (2.2.18) Harmonic Balance Equation, (2.2.18) vector V. F(V) current- error vector, Optimization, Splitting Methods, New ton' s Method, Reflection Algorithm. Fast Fourier T ransform(fft ) algorithm,. 15 HP- eesof Libra Harmonic Balance Method. - 22 -
15. Harmonic Balance Method Algorithm - 23 -
2.2.2. Generalized Harmonic Balance Analysis harmonic, harmonic. Generalized Harmonic Balance Analysis, Harmonic Balance Analysis. harmonic p1, p2, K k = 0, 1, 2,... K - 1 (2.2.19) 0=0, harmonic,. k = m p1 + n p2; m, n =..., - 2, - 1, 0, 1, 2,... (2.2.20) Harmonic Balance k p harmonic. (2.2.18) (2.2.6) (2.2.14) k p (2.2.19) (2.2.20) k. (2.2.7). - 24 -
V N + 1 V N + 2 = V b 1 V S. 1 V S. 2 0 : 0 V b 2 0 0 0 : 0 (2.2.21) F(V)=0 V FFT, brute force almost- periodic Fourier. - 25 -
. [12][13] Gate 2 P1dB (IP3). P1dB (IP3). HPA(High Pow er Amplifier) Predistortion 16 main Amplifier,. 16. Predistortion - 26 -
17. overdriving Predistortion ( 16 ) P1dB, main Amp P1dB back- off, main Amplifier., main Amp. 17 ( 16 ), P1dB, overdriving. 17, 3, 5 Single Gate FET,. Phase Shifter., P1dB, 3. Single- Gate FET Dual- Gate FET, 17 B Gate 2, E Dual- Gate FET. Single- Gate FET,. Dual- Gate FET Gate 2,. - 27 -
17. - 28 -
. Philips Dual- Gate MOSFET BF904, Dual- Gate FET mode, Gate 2 Variable Gain Amplifier,, HP ADS(Advanced Design System) simulation.,. 18 simulation. 18. BF904 Dual- Gate MOSFET Model - 29 -
4.1. FET 4.1.1. mode Variable Gain Amplifier bias VDS=6V, IDS=10mA, VG2=4V. VGS1 1.5V. 19 VDS 6V mode. VG2 2.3V mode A mode B. 19. VDS=6V BF904 mode - 30 -
4.1.2. Variable Gain Amplifier Gate 2 bias, RF Gate 2 RF. 3. Variable Gain Amplifier, VG2 Gate 2 S- parameter, 3 = 0. 20, 21, 22 VG2 1.5V 4.2V, Gate 2 RF 3 = 0 S- parameter. RF cascode S12, S22. S- Parameter, 3 = 0 RF, RF S22 1, 3 = 0. 20. Gate 2 S11 S22-31 -
. 21. Gate 2 S21 22. Gate 2 S12-32 -
4.2. Variable Gain Amplifier 4.2.1. : Philips BF904 Dual- Gate MOSFET : 849 869MHz (KMT - CDMA ) : 10dB VSWR : 1.2 (return Loss:- 20dB) VSWR : 1.2 (return Loss:- 20dB) 4.2.2. 7.5dB - 2.5dB Variable Gain Amplifier Gate 2 3 = 0. VSW R 1.2. 23 24 7.5dB, - 2.5dB. 23. 7.5dB - 33 -
24. - 2.5dB 25 VG2 simulation. Gate 2 0.2V. 25. VG2-34 -
26 VG2 P1dB simulation. 27-15dBm/tone, VG2 IP3 simulation. 26. P1dB simulation 27. IP3 simulation - 35 -
28, VG2 IP3. 28. IP3 4.3. 29,. Dual- Gate FET Gate 2 3V, - 10dBm/tone 12dBm/tone VG2 phase shifter 30 31. 3 20dB - 3dBm/tone 12dBm/tone 15dB Dynamic Range. - 36 -
29. 30. - 37 -
31. - 38 -
. Dual- Gate FET DC, mode. Gate 2 RF, Gate 2 S- parameter 3=0, Variable Gain Amplifier. Variable Gain Amplifier Philips BF904 Dual- Gate MOSFET, KMT - CDMA 10dB - 20dB. Variable Gain Amplifier (P1dB, IP3), HP ADS(Advanced Design System) simulation. simulation mode A, mode B. mode (VG2=2.3V)., IP3, mode, bias ID. VG2. Simulation Body Effect, FET 4. conversion error,. Variable Gain Amplifier. Single- Gate FET, 15dB 20dB. - 39 -
[1] M. Maeda and Y. Minai, Microw ave variable- gain amplifier w ith dual- gate GaAs FET, IEEE T rans. Microw ave T heory T ech., vol. MT T - 22, pp.1226-1230, Dec. 1974. [2] C. A. Liechti, Performance of Dual- Gate GaAs MESFET ' s as Gain- Controlled Low - Noise Amplifiers and High- Speed Modulators, IEEE T rans. Microw ave T heory T ech., vol. MT T - 23, pp.461-469, June. 1975. [3] S. C. Crippss, O. Nielsen, D. Parker, and J. A. T urner, An experimental evaluation of X- band GaAs FET mixers using single- and dual- gate devices, MT T - S International Microw ave Symposium Digest, pp.285-287, 1977. [4] R. E. Miles and M. J. How es, Large- Signal Equivalent- Circuit Model of a GaAs Dual- Gate MESFET Mixer, IEEE T rans. Microw ave T heory T ech., vol. MT T - 33, pp.433-436, May. 1985. [5] I. D. Robertson, MMIC Design, Chap. 7, T he Institution of Electrical Engineers, 1988. [6] C. T sironis and R. Meierer, Microw ave Wide- Band Model of GaAs Dual Gate MESFET ' s, IEEE T rans. Microw ave T heory T ech., vol. MT T - 30, pp.243-251, Mar. 1982. [7] R. A. Minasian, Modelling DC characteristics of dual- gate GaAs MESFET s, IEE Proc. Solid- State Electron., vol.130, pp. 182-186, Aug. 1983. - 40 -
[8] J. R. S cott and R. A. Minas ian, A Simplified Microw ave Model of the GaAs Dual- Gate MESFET, IEEE T rans. Microw ave T heory T ech., vol. MT T - 32, pp.243-247, Mar. 1984. [9] S. A. Mass, Nonlinear Microw ave Circuits, Artech House, 1988. [10] J. H. Haywood, Y. L. Chow, Intermodulation Distortion Analysis Using a Frequency- Domain Harmonic Balance T echnique, IEEE T rans. Microw ave T heory T ech., vol. MT T - 36, pp. 1251-1257, Aug. 1988. [11] R. A. Minasian, Intermodulation Distortion Analysis of MESFET Amplifier Using the Volterra Series Representation, IEEE T rans. Microw ave T heory T ech., vol. MT T - 28, pp.1-8, Jan. 1980. [12] R. C. T upynamba and E. Camargo, MESFET Nonlinearities Applied T o Predistortion Linearizer Design, MT T - S International Microw ave Symposium Digest, vol., pp.955-958, 1992. [13] Y. Kim, Y. Yang, S. Kang and B. Kim, Linearization of 1.85GHz Amplifier Using Feedback Predistortion Loop, MT T - S International Microw ave Symposium Digest, vol., pp.1675-1678, 1998. - 41 -