DSD_VerilogHDL_11 1 디지털시스템설계 (Verilog HDL) Latch Gated Latch RS, D, JK, T Flip-Flop Flip-Flop with PRS, CLR inputs

DSD_VerilogHDL_11 1 디지털시스템설계 (Verilog HDL) Latch Gated Latch RS, D, JK, T Flip-Flop Flip-Flop with PRS, CLR inputs

DSD_VerilogHDL_11 2 설계과제 [ 설계 1-1] RS Latch 설계 (NOR type) module nor_rs_latch (R, S, Q, Qbar); input R, S; output Q, Qbar; // NOR type, High Active, Structural nor U1 (Q, R, Qbar); nor U2 (Qbar, Q, S); S R Q Q' 0 0 No change 0 1 0 1 1 0 1 0 1 1 Invalid

DSD_VerilogHDL_11 3 [ 설계 1-2] RS Latch 설계 (NAND type) module nand_rs_latch (R, S, Q, Qbar); input R, S; output Q, Qbar; // NAND type, Low Active, Structural nand U1 (Q, S, Qbar); nand U2 (Qbar, Q, R); S' R' Q Q' 0 0 Invalid 0 1 1 0 1 0 0 1 1 1 No change

DSD_VerilogHDL_11 4 [ 설계 2-1] Gated RS Latch 설계 (NOR type) odule nor_gated_rs_latch (CP, R, S, Q, Qbar); input CP; input R, S; output Q, Qbar; wire ss, rr; // Gated RS Latch, NOR type, Structural and U1 (ss, S, CP); and U2 (rr, R, CP); nor_rs_latch L1(rr, ss, Q, Qbar); S R Q(t+1) 0 0 Q(t) 0 1 0 1 0 1 1 1 Invalid

DSD_VerilogHDL_11 5 [ 설계 2-2] Gated RS Latch 설계 (NAND type) module nand_gated_rs_latch (CP, R, S, Q, Qbar); input CP; input R, S; output Q, Qbar; wire ss, rr; // Gated RS Latch, NAND type, Structural nand U1 (ss, S, CP); nand U2 (rr, R, CP); nand_rs_latch L1 (rr, ss, Q, Qbar); S R Q(t+1) 0 0 Q(t) 0 1 0 1 0 1 1 1 Invalid

DSD_VerilogHDL_11 6 [ 설계 3] Gated D Latch 설계 D Q(t+1) 0 0 1 1 module Gated_D_Latch (CP, D, Q, Qbar); input CP; input D; output Q, Qbar; // Gated D Latch, NOR type, Structural //nor_gated_rs_latch (CP, ~D, D, Q, Qbar); // Gated D Latch, NAND type, Structural nand_gated_rs_latch (CP, ~D, D, Q, Qbar);

DSD_VerilogHDL_11 7 * Flip-Flop - Master/Slave Type으로구현 - Edge Trigger( positive or Negative ) : posedge, negedge - 예 ) SR Flip-Flop

DSD_VerilogHDL_11 8 [ 설계 4-1] RS Flip-Flop 설계 module RS_flipflop (clk, RESET, R, S, Q, Qbar); input clk, RESET, R, S; output Q, Qbar; reg Q; // RS f/f assign Qbar = ~Q; always @(posedge clk, negedge RESET) begin if(!reset) Q <= 0; else if (R==1 && S==0) Q <= 0; else if (R==0 && S==1) Q <= 1; else Q <= Q; end S R Q(t+1) 0 0 Q(t) 0 1 0 1 0 1 1 1 Invalid

DSD_VerilogHDL_11 9 [ 설계 4-2] D Flip-Flop 설계 module D_flipflop (clk, RESET, D, Q, Qbar); input clk, RESET, D; output Q, Qbar; reg Q; // D f/f assign Qbar = ~Q; always @(posedge clk, negedge RESET) begin if(!reset) Q <= 0; else Q <= D; end

DSD_VerilogHDL_11 10 [ 설계 4-3] JK Flip-Flop 설계 module JK_flipflop (clk, RESET, K, J, Q, Qbar); input clk, RESET, K, J; output Q, Qbar; reg Q; // JK f/f assign Qbar = ~Q; always @(posedge clk, negedge RESET) begin if(!reset) Q <= 0; else if (K==0 && J==0) Q <= Q; else if (K==1 && J==0) Q <= 0; else if (K==0 && J==1) Q <= 1; else Q <= ~Q; end J K Q(t+1) 0 0 Q(t) 0 1 0 1 0 1 1 1 Q(t)'

DSD_VerilogHDL_11 11 [ 설계 4-4] T Flip-Flop 설계 module T_flipflop (clk, RESET, T, Q, Qbar); input clk, RESET, T; output Q, Qbar; reg Q; // T f/f assign Qbar = ~Q; always @(posedge clk, negedge RESET) begin if(!reset) Q <= 0; else if (T) Q <= ~Q; else Q <= Q; end

DSD_VerilogHDL_11 12 [ 설계4-5] Flip-Flops 설계 * 위의플립플롭모듈을참조하여 * PRESET(/PRS) 기능추가및 * CLK의하강에지트리거방식으로설계

DSD_VerilogHDL_11 13 [ 설계 5] Flip-Flops with asynchronous inputs(/prs, /CLR) * [ 한산 09] P.406, Fig.7.45 & Fig.7.46 참조

DSD_VerilogHDL_11 14 [ 설계6] RS, D, JK, T Flip-flops 실습 * 'edit'-'insert template'-'verilog HDL'- 'Altera Primitive'-'Registers and Latches' * SRFF, DFF, JKFF, TFF 템플릿이용 // using JKFF primitive // module JKFF_test (q, clk, j, k, clr, pr); input clk, j, k, clr, pr; output q; JKFF (.j(j),.k(k),.clk(clk),.clrn(clr),.prn(pr),.q(q) );

DSD_VerilogHDL_11 15 Blocking/NonBlocking Assignment * 설계목표 : 2 비트쉬프트레지스터

DSD_VerilogHDL_11 16 Blocking/NonBlocking Assignment( 계속 ) * Blocking assignment, [ 한산 09]P.402 // blocking assignment module ex01(d, Clk, Q1, Q2); input D, Clk; output reg Q1, Q2; always @(posedge Clk) begin Q1 = D; Q2 = Q1; end

DSD_VerilogHDL_11 17 Blocking/NonBlocking Assignment( 계속 ) * Non-blocking assignment : 각할당의결과가 always 블록이끝날때까지적용되지않음. // Non-blocking assignment : always @(posedge Clk) begin Q1 <= D; Q2 <= Q1; end :

DSD_VerilogHDL_11 18 [ 설계과제 ] 다음의카운터회로를설계 * 다음주 OHP 자료참조 1) 리플카운터 (UP, DOWN) 2) 링카운터 3) 존슨카운터 끝.

[ 설계과제 ] 4 비트리플카운터 (16 진카운터 ) DSD_VerilogHDL_11 19