조합논리회로 2 (Combinational Logic Circuits 2) 2011 6th
강의내용 패리티생성기와검출기 (Parity generator & Checker) 인에이블 / 디제이블회로 (Enable/Disable Circuits) 디지털집적회로의기본특성 (Basic Characteristics of Digital ICs) 디지털시스템의문제해결 (Troubleshooting Digital System) PLD (Programmable Logic Devices) 교재 : Chapter 4-7 ~ 4-14 2
패리티생성기와검출기 (Parity generator & Checker) Even-parity generator.d 3 D 2 D 1 D 0 = {0111} P = 1. D 3 D 2 D 1 D 0 = {1001} P = 0 Even-parity checker.pd 3 D 2 D 1 D 0 = {01010} E = 0.PD 3 D 2 D 1 D 0 = {10000} E = 1 3
인에이블 / 디제이블회로 (Enable/Disable Circuits) < Enable회로 vs. Disable회로 > * A= 신호입력, B= 제어신호 * 정의 : 출력신호입력복사 / 복사의역출력이항상상수 (1/0) 4
인에이블 / 디제이블회로 (Enable/Disable Circuits) Ex4-21) 제어신호 B=C=1 일때만출력이통과되고, 그렇지않으면 LOW 되는논리회로? Sol) Enable condition (B C) A Disable condition ~(B C) 0 x=a (BC) Ex4-22) 제어신호 B,C 중, 오직하나만 HIGH 일때출력이통과되고, 그렇지않으면 HIGH 되는논리회로? Sol) Enable condition ( ) A Disable condition ( ) 1 x= A+( ) 5
인에이블 / 디제이블회로 (Enable/Disable Circuits) Ex4-23) 입력신호 A, 제어신호 B, 출력신호 X, Y 일때, 다음 1) 과 2) 를동시에만족하는회로? 1) B=1 일때 X 는 A 를추종, Y=0 2) B=0 일때 X=0, Y 는 A 를추종 Sol) X,Y는 Enable condition에서 A Disable condition 0 각출력에 AND gate 필요 ( disable output = 0 ) X=B A, Y= (~B) A 6
디지털집적회로의기본특성 (Basic Characteristics of Digital ICs) Dual-in-line package (DIP) Top view (14=V CC,/V DD 7=GND) Actual silicon chip (the protective package) Complexity in digital IC 7
디지털집적회로의기본특성 (Basic Characteristics of Digital ICs) Bipolar IC(=BJT) TTL INVERTER circuit Unipolar IC CMOS INVERTER circuit Bipolar & Unipolar Digital ICs ( See chapter 8 lately! ) 8
디지털집적회로의기본특성 (Basic Characteristics of Digital ICs) TTL Series Prefix Example IC Standard TTL 74 7404 (hex INVERTER) Schottky TTL 74S 74S04 (hex INVERTER) Low-power Schottky TTL 74LS 74LS04 (hex INVERTER) Advanced Schottky TTL 74AS 74AS04 (hex INVERTER) Advanced low-power Schottky TTL 74ALS 74ALS04 (hex INVERTER) Various series within the TTL logic family TTL Series Prefix Example IC Metal-gate CMOS 40 4001 (quad NOR gates) Metal-gate, pin-compatible with TTL 74C 74S04 (hex INVERTER) Silicon-gate, pin-compatible with TTL, high-speed 74HC 74LS04 (hex INVERTER) Silicon-gate, high-speed, pin-compatible and electrically with TTL Advanced-performance CMOS, not pin-compatible or electrically compatible with TTL Advanced-performance CMOS, not pin-compatible with TTL, but electrically compatible with TTL 74HCT 74AC 7474ACT 74AS04 (hex INVERTER) 74ALS04 (hex INVERTER) Various series within the CMOS logic family 9
디지털집적회로의기본특성 (Basic Characteristics of Digital ICs) Logic-level voltage range TTL vs. CMOS 0 / 1 0 / 1 [0, 0.8V] / [2.0, 5.0V] [0, 1.5V] / [3.5, 5.0V] Floating (Unconnected inputs) TTL vs. CMOS HIGH recognized Overheated & destroy the chip [1.4, 1.8V] Unpredictable output (indetermined but HIGH) Susceptible to picking up noise Susceptible to picking up noise 10
디지털집적회로의기본특성 (Basic Characteristics of Digital ICs) 논리회로연결다이어그램 : 모든전기적연결, 핀번호, IC 번호, 신호이름, 전원전압등을표시한회로 11
디지털시스템의문제해결 (Troubleshooting Digital System) < 디지털회로 / 시스템의오류 / 고장고치기 > 1. Fault detection : 작동을관찰, 정상작동과비교 (logic probe, oscilloscope, logic pulser, ) 2. Fault isolation : 테스터실시후고장을분리하기위한측정 3. Fault correction : 고장난부품을교체, 고장연결을고치고, 단락부분을제거등 A logic probe for monitoring the logic level activity at an IC pin or any other accessible point in a logic circuit 12
디지털 IC 의내부결함 (Internal Digital IC Faults) < 디지털회로 / 시스템의내부결함 / 고장 > 1. 내부회로의오작동 (malfunction) : 내부부품의결함 / 동작범위초과 2. 입 / 출력의접지 / 전원에단락 (short) : (a) / (b) & (c)/(d) 3. 입 / 출력의개방 (open-circuited) : 4. 두핀간의단락 13
디지털 IC 의내부결함 (Internal Digital IC Faults) < Ex 4-24 > 다음회로를 logic probe 로검사한결과를표에나타내었다. 회로가정상적으로동작하고있는가? Sol) Z1-4 should be pulsing but is stuck to LOW. 1) Z1 의내부결함가능성, 2) Z1-4 핀의접지단락가능성, 3) Z2-1 핀의접지단락가능성 < Ex 4-25 > 개방회로입 / 출력문제 다음회로와같이내부적으로개방이되었을때 Ex 4-24 와같이핀 13 과핀 6 에서의 logic probe 의검사결과는? Sol) 1) 핀 13 의논리신호는입력신호와동일, 2) 핀 6 의논리신호는 dim light for indetermined logic level 14
디지털 IC 의내부결함 (Internal Digital IC Faults) < Ex 4-26 > 다음회로 (TTL) 를 logic probe 로검사한결과를표에나타내었다. 회로가정상적으로동작하고있는가? Sol) Z2-3 should be HIGH but is pulsing. Why? Z2-1 의내부개방가능성 Z2-1 이 HIGH 로간주 (TTL) < 두핀간의내부단락 > : i) Z1-1 = Z1-3 Z1-2 = Z1-4 (1/0) ii) Z1-1 Z1-3 Z1-2 = Z1-4 (intermediate level) = signal contention ( 신호쟁탈 ) 15
외부결함 (External Faults) < 디지털회로 / 시스템의외부결함원인 > 1. 연결선절단 2. 불량납땜 3. PCB(Printed Circuit Board: 인쇄회로기판 ) 상에서 trace 의균열 / 절단 4. IC 핀의굴절 / 절단 5. C 핀이정확하게삽입되지않는불량 IC socket 6. 신호선간의단락 7. 불량전원수준 < Ex 4-27 > 다음회로 (CMOS) 를 logic probe 로검사한결과를표에나타내었다. 회로의어디에결함이있는가? Sol) Z2-2 should be LOW but is intermediate. Why? Z1-6 Z2-2 open circuit from Z1-6 to Z1-2. 16
문제해결사례연구 (Troubleshooting Case Study) < Ex 4-28 > 다음회로를 logic probe 로검사한결과, 출력 Y=1 if 1) A=1, B=0, C don t care 또는 2) A=0, B=1, C=1. Sol) Y=1 whenever A=1 or C=1 & test inputs : A=B=0, C=1 Z1-3 should be LOW but actually HIGH. Why? ( 가능성 ) 1. Z1 의내부결함 2. 3 X 사이에어느점에서전원 (V CC ) 에단락되었을 3. Z1-3 핀의 V CC 에내부적단락 / 4. Z2-5 핀의 V CC 에내부적단락 / 5. Z2-13 핀의 V CC 에내부적단락 < 결함부분분리 / 대체과정 > 1. Z1 의 V CC /GND level 검사 (14/7) 2. 전원을끄고저항기로단락검사 : X V CC (Z1-14, Z2-14) If no short : Z1 내부결함! Z1 대체! 3. If a short 모든외적단락가능성육안으로조사 / 대체 4. 3. 도아니면 Z1-3, Z2-13, Z2-5 중 V CC 와내적단락 /gate 대체 17
PLD (Programmable Logic Devices) < PLD : 프로그램가능논리소자 > 1. Program 통해원하는논리연산을 H/W 적으로가능케하는소자 2. 컴퓨터와 PLD 개발 S/W(development software) 만으로귀찮은작업의자동화 / 효율화 3. Fuse 와 SOP architecture 18 ZIF socket (Zero Insertion Force socket)
PLD (Programmable Logic Devices) < PLD 프로그래밍 & 개발 S/W > 1. 제조사와관계없이표준 H/W & S/W format 존재 (JDEC standard 3) Joint Electronic Device Engineering Council 2. 개발 S/W : hardware discription language (HDL) + compilers ex) ABEL compiler(by Data I/O Corporation) CUPL ( Universal Compiler for Programmable Logic by Logical Devices, Inc.) Verilog HDL compiler (VHDL) 회로설계의컴파일러구현방법 3 종류 19
PLD (Programmable Logic Devices) Logic-level voltage range Name TestCircut; Partno atf16v8c; Date 2010/10/04; Rev 01; Designer ygryu; Company kut; Assembly None; Location None; Device g16v8; /****************************************************/ /* Test simple circuit */ /****************************************************/ /* 입출력을위한핀정의 ***/ < CUPL 프로그래밍 format > 1. Syntax for logic operations : AND & OR # NOT! XOR $ 2. 예 ( ) 3. Fig.4-44 의 CUPL file 로부터얻어진 GAL16V8 H/W 회로결선 ( ) /** Inputs **/ Pin 2 = IN1; /* Input pin 1 */ Pin [5..7] = [A1..3]; /* Input vector */ /** Outputs **/ Pin 14 = OUT1; /* Output 1 */ Pin [17..19] = [O1..3]; /* Output vector */ /* 기능을구현한다. */ OUT1 = IN1 & A1 & A2 & A3 #!IN1 &!A1 &!A2 &!A3; O1 = A1 &!A2 &!A3; O2 =!A1 & A2 &!A3; O3 =!A1 &!A2 & A3; 20
PLD (Programmable Logic Devices) PLD 개발사이클 < PLD 개발사이클 > - Simulator : a computer program calculating the correct output logic states for the given inputs test vectors - In-circuit test : tested functionally with all peripheral components 21
강의내용 ( 복습 ) 패리티생성기와검출기 (Parity generator & Checker) 인에이블 / 디제이블회로 (Enable/Disable Circuits) 디지털집적회로의기본특성 (Basic Characteristics of Digital ICs) 디지털시스템의문제해결 (Troubleshooting Digital System) PLD (Programmable Logic Devices) 다음시간수업 교재 : Chapter 5-1 ~ 5-12 22
연습문제 Examples 4-7 ~ 4-14 꼭풀어보세요. Problems Section 4-7 ~ 4-14 에서홀수만풀어보세요. 23