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VHDL Simulation Synthesis - Synopsys Tool - System ASIC Design Lab : jcho@asiclabinchonackr -I - : -Bit Full Adder Simulation Synopsys Simulation Simulation Tool -2 : -Bit Full Adder Synthesis Synopsys Synthesis Synthesis Tool -3 : -Bit Serial Adder Synopsys Tool -4 : 3-tap FIR Filter -5 : Counter 7-Segment Display -II -6 : Traffic Light Controller Digital System RTL VHDL Synopsys Tool Ma+PlusII FPGA SynopsysVHDL NO-2

Simulation Synopsys VSS Simulator Built-in Library (standard, IEEE, synopsys, ASIC vendor) VHDL Source code (#vi eamvhd) Compile (#vhdlan eamvhd) eamsim eammra Working Library startup files synopsys_vsssetup Simulation (#vhdldb) VHDL compile : $ vhdlan {vhdl_source_file_name} Built-in Library standard, IEEE, synopsys, ASIC vendor, your own Working Library VHDL code compile (*sim, *mra) Simulation : $ vhdldb setup file synopsys_vsssetup SynopsysVHDL NO-3 VSS Simulator () synopsys _vsssetup file Working_Library_Name Working_Library_Directory User Working_Library_Name : Compile Symbolic Name Working_Library_Directory : Working Library Directory Path TIMEBASE WAVEFORM WORK Working_Library_Name = NS = waves > Working_Library_Name : Working_Library_Directory EDITCMD = term -geom 926 -T Synopsys-Editor -e vi User Home Directory sim_work directory Uni $ mkdir ~/sim _work synopsys _vsssetup file TIMEBASE = NS WAVEFORM = waves WORK > sim_work sim_work : ~/sim_work EDITCMD = term -geom 926 -T Synopsys-Editor -e vi SynopsysVHDL NO-4 2

VSS Simulator (2) UNIX vi editor ~/synopsys_vsssetup file Simulation Default : TIMEBASE Simulation Default : WAVEFORM Compile : WORK SynopsysVHDL NO-5 - : Full Adder Block VHDL Simulation Stimulus File Test Bench VHDL Simulation test bench for Full adder (tb_favhd) A C_out stimulus vectors (vecvhd) B C_in full adder (favhd) Sum SynopsysVHDL NO-6 3

- : Full Adder Data flow VHDL Data Flow library IEEE; use IEEEStd_logic_64all; entity fa is port ( A : in std_logic; B : in std_logic; C_in : in std_logic; C_out: out std_logic; Sum : out std_logic); end fa; architecture rtl of fa is signal S : std_logic; begin S <= A or B; Sum <= S or C_in; C_out <= (A and B) or (S and C_in); end rtl; SynopsysVHDL NO-7 - : Stimulus Vector VHDL Stimulus Vector library IEEE; use IEEEStd_logic_64all; entity vec is port (A, B, C_in : out std_logic); end vec ; -- architecture rtl of vec is begin process begin A <= ; B <= ; C_in <= ; wait for ns; A <= ; B <= ; C_in <= ; wait for ns; A <= ; B <= ; C_in <= ; wait for ns; A <= ; B <= ; C_in <= ; wait for ns; A <= ; B <= ; C_in <= ; wait for ns; A <= ; B <= ; C_in <= ; wait for ns; A <= ; B <= ; C_in <= ; wait for ns; A <= ; B <= ; C_in <= ; wait for ns; end process; end rtl; SynopsysVHDL NO-8 4

- : Full Adder Test Bench VHDL Test Bench VHDL library IEEE;use IEEEstd_logic_64all; entity tb_fa is end tb_fa; -- architecture rtl of tb_fa is component fa port ( A,B,C_in : in std_logic; C_out,Sum: out std_logic); end component; component vec port ( A,B,C_in : out std_logic); end component; -- Signal Assign signal A, B, C_in : std_logic; signal C_out, Sum : std_logic; for U : fa use entity workfa(rtl); for U2 : vec use entity workvec (rtl); begin -- U, U2 Component Label -- -- -- U : fa port map ( A=> A,B=> B,C_in => C_in, C_out=> C_out,Sum=> Sum); U2 : vec port map ( A=> A,B=> B,C_in=> C_in); end rtl; SynopsysVHDL NO-9 - : VHDL Code Compile Code Compile Design Tree VHDL Code Compile tb_favhd favhd vecvhd Uni Command $ vhdlan favhd $ vhdlan vecvhd $ vhdlan tb_favhd Compile Window SynopsysVHDL NO- 5

- : Compile File Compile Error ~/sim _work Directory SynopsysVHDL NO- - : Test Bench Compile Loading Simulation Engine Test Bench VHDL Loading $ vhdldb & Window Loading Window Working Library Design Simulation Simulation Configuration Entity_Architecture_n ame ( configuration) SynopsysVHDL NO-2 6

- : Test Bench Compile Loading Loading Window VHDL Top Model Source code typing Command line SynopsysVHDL NO-3 - : VHDL Debugger Command Command () trace * source code cd label : cd U sub-block trace signal_name : trace s cd block SynopsysVHDL NO-4 7

- : Simulation Engine Command (2) run Simulation Engine ns Simulation waveform scale >tool-bar menu View sub-menu SynopsysVHDL NO-5 - : Simulation Waveform Full Fit ( ) Zoom In ( ) Zoom Out ( ) Zoom Fit ( ) SynopsysVHDL NO-6 8

-2 : VHDL (Logic Synthesis)? Synthesis = Translation + Optimization + Mapping Translate into Boolean Representation HDL Source code Optimize + Map Synthesis Generic Boolean (GTECH) Target Technology SynopsysVHDL NO-7 Synopsys Synthesis Tool File Design Compiler Setup File : synopsys _dcsetup Setup File Setup File : Synopsys Tool Default Setup File (account) : Directory : Directory Design Model ~user $SYNOPSYS/admin/setup synopsys_dcsetup synopsys_dcsetup specific design synopsys_dcsetup User's General Setup User's Specific Project (design) Setup Standard setup SynopsysVHDL NO-8 9

Synopsys Synthesis Tool synopsys _dcsetup File : Target Library ALTERA FLEXK Target Library lsi_k SynopsysVHDL NO-9-2 : Design Analyzer Window Design Analysis Tool Loading Uni Command $ design_analyzer & Window Command menus View Select Up/Down Hierarchy Informational Message Appear Here Current View SynopsysVHDL NO-2

-2 : Check Design Compiler Setup Design Analysis Command Menu Setup Defaults >Setup > Defaults Window Call synopsys_dcsetup File Loading Link Library Target Library Symbol Library SynopsysVHDL NO-2-2 : Technology Library Link Library Optimization Design Compiler cells wireloads, technology library Link Library HDL Code Instantiated : adders, NORs, assorted gates Gate Level Netlist input Design Compiler Target Library Synthesis design compiler mapping technology library Design Compiler output Optimized Netlist Target Design mapped to gates from the Target Library Library link library target library technology library SynopsysVHDL NO-22

-2 : Design Compiler File () Design Analysis Command Menu File Read >File > Read Window File Name File Format, OK Reading Design File Supports many different formats Format db edif equation lsi mif pla st tdl verilog vhdl nf Description Synopsys Internal Format Electronics Design Interchange format Synopsys Equation Format LSI Logic Corporation Format Mentor Intermediate Format Berkeley (Epresso) PLA Format Synopsys State Table Format Tegas Design Language Format Cadence Design Systems Inc HDL IEEE Standard VHDL Xilin Netlist Format SynopsysVHDL NO-23-2 : Design Compiler File (2) File Read Window Error Window VHDL Code Symbol SynopsysVHDL NO-24 2

-2 : HDL Files Translate File Read Analyze Elaborate Design Analysis Command Menu >File > Analyze >File > Elaborate SynopsysVHDL NO-25-2 : HDL Files Translate Translate Symbol Window Symbol Symbol Double Click Target Library, SynopsysVHDL NO-26 3

-2 : Optimization Constraints Optimization Design Block Optimization Constraints, MaArea >Attributes > Optimization Area Constraints > Design Constraints Vendor Target Window Technology Library eg : 2-input-NAND-gate, inverters, transistors, or square mils, etc Design Rule Constraints Ma Fanout typing Optimization Fanout SynopsysVHDL NO-27-2 : Optimization Optimization Design Block, >Tools > Design Optimization Design Optimization Window OK Optimization Window SynopsysVHDL NO-28 4

-2 : Optimization Symbol Target Library Symbol Double Click VHDL Modeling Behavioral Modeling : Structural Modeling : Component Symbol SynopsysVHDL NO-29-2 : Optimization Report () Cell, Delay Critical Path Command Menu >Analysis>Report Window SynopsysVHDL NO-3 5

-2 : Optimization Report (2) Area Report File Delay Report File Window Area Window Timing SynopsysVHDL NO-3-2 : Optimization Critical Path Path Timing Delay Path Command Menu >Analysis>Highlight>Critical Path Window Path Critical Path SynopsysVHDL NO-32 6

-2 : Synthesis ALTERA Library edif file file Recommendation : Always use the save ALL Designs in Hierarchy option SynopsysVHDL NO-33-3 : Full Adder N-Bit VHDL carry -Bit Flip-Flop Bit Serial Adder (bit_addvhd) a b a b c_in sum Full Adder (favhd) c_out sum carry_in D F/F (regvhd) carry_out reset clock SynopsysVHDL NO-34 7

-3 : VHDL -Bit Flip-Flop VHDL library IEEE;use IEEEstd_logic_64all; entity reg is port ( reset, clock: in std_logic; d_in : in std_logic; d_out : out std_logic); end reg; architecture rtl of reg is begin process ( reset, clock, d_in ) begin if reset = '' then d_out <= ''; elsif clock = '' and clock'event then d_out <= d_in; end if; end process; end rtl; VHDL library IEEE; use IEEEstd_logic_64all; entity bit_add is port ( a, b, reset, clock : in std_logic; sum : out std_logic); end bit_add; architecture rtl of bit_add is component fa port ( a, b, c_in : in std_logic; sum, c_out : out std_logic); end component; component reg port ( reset, clock, d_in : in std_logic; d_out : out std_logic); end component; for u : fause entity workfa(rtla); for u : reg use entity workreg(rtl); signal carry_in, carry_out : std_logic; begin u :faport map (a, b, carry_in, sum, carry_out); u : reg port map (reset, clock, carry_out, carry_in); end rtl; SynopsysVHDL NO-35-3 : File Read 3 VHDL Code File Read VHDL Code File Read >File>Read>favhd >File>Read>regvhd >File>Read>bit_addvhd bit_addvhd favhd regvhd SynopsysVHDL NO-36 8

-3 : Clock Clock attributes Design Analyzer clock Design Analysis Command Menu Attributes Clock, Specify >Attributes > Clock > Specify SynopsysVHDL NO-37-3 : Design Constraint Optimization Optimization Design Rule symbol >Attributes > Optimization Constraints > Design Constraints typing SynopsysVHDL NO-38 9

-3 : Optimization Optimization Design Block, >Tools > Design Optimization Design Optimization Window OK Optimization Window Cell Delay Report File SynopsysVHDL NO-39-3 : -Level ( ) -Level, >Edit > Ungroup -Level SynopsysVHDL NO-4 2

-4 : 3-Tap FIR Filter RTL 3-Tap FIR Filter RTL VHDL, Simulation Synthesis fir_in 8 8 8 Reg Reg sequential Logic 8 clock reset "" 5 5 5 "" "" 3 3 3 ADDER combinational Logic fir_out SynopsysVHDL NO-4-4 : 3-Tap FIR Filter VHDL library IEEE; use IEEEstd_logic_64all; use IEEEstd_logic_signedall; entity fir is port ( fir_in : in std_logic_vector(7 downto ); clock : in std_logic; reset : in std_logic; fir_out : out std_logic_vector(9 downto )); end fir; -- architecture rtl of fir is signal t_, t_2 : std_logic_vector(7 downto ); -- filter constant a : std_logic_vector(4 downto ) := ""; constant a2 : std_logic_vector(4 downto ) := ""; constant a3 : std_logic_vector(4 downto ) := ""; begin --filter register process(clock,reset) begin if reset = '' then t_ <= (others => ''); t_2 <= (others => ''); elsif clock'event and clock = '' then t_ <= fir_in; t_2 <= t_; end if; end process; --filter process(fir_in, t_, t_2) variable b_, b_, b_2, tmp : std_logic_vector(2 downto ); begin b_ := a * fir_in; b_ := a2 * t_; b_2 := a3 * t_2; tmp := b_ + b_ + b_2; fir_out <= tmp(2 downto 3); end process; end rtl; SynopsysVHDL NO-42 2

-4 : FIR Filter Test Bench VHDL library IEEE; use IEEEstd_logic_64all; entity tb_fir is end tb_fir; -- architecture rtl of tb_fir is -- component fir port ( fir_in : in std_logic_vector(7 downto ); clock : in std_logic; reset : in std_logic; fir_out : out std_logic_vector(9 downto )); end component; -- for u: fir use entity workfir(rtl); -- signal fir_in : std_logic_vector(7 downto ); signal clock, reset : std_logic := ''; signal fir_out : std_logic_vector(9 downto ); -- begin u: fir port map ( fir_in, clock, reset, fir_out); clock <= not clock after 2 ns; -- reset <= '' after ns; -- process begin fir_in <= "", "" after ns, "" after 2 ns, "" after 3 ns, "" after 4 ns, "" after 5 ns, "" after 6 ns, "" after 7 ns; wait for 8 ns; end process; end rtl; -- configuration conf of tb_fir is for rtl end for; end conf; SynopsysVHDL NO-43-4 : Synopsys Simulator VHDL Waveform SynopsysVHDL NO-44 22

-4 : Synopsys Synthesis Tool, Report File SynopsysVHDL NO-45-5 : Synthesis Tool Counter Simulation Tool RESE T CLK CNT_OU T(n) CNT_OUT(n+) X X Counter? Counter? CNT_OUT(n) + Seven-Segment Segment CNT_OUT SEG_OUT "" COUNTER "" "" "" f "" e a 7-SEG "" g Driver "" d b c "" "" " SynopsysVHDL NO-46 23

-5 : Behavioral Level VHDL Counter VHDL library IEEE; use IEEEStd_logic_64all; use IEEEStd_logic_unsigned"+"; entity Counter is port ( RESET : in std_logic; Clk : in std_logic; CNT_out : out std_logic_vector(3 downto )); end Counter; architecture Counter_Arch of Counter is signal CNT : std_logic_vector(3 downto ); begin process(reset, CLK) begin if RESET = '' then -- same epression of CNT <= ""; CNT <= (others => ''); elsif Clk'event and Clk = '' then if CNT = "" then CNT <= (others => ''); else CNT <= CNT + ''; end if; end if; end process; CNT_out <= CNT; end Counter_Arch; Segment VHDL library IEEE; use IEEEStd_logic_64all; entity Segment is port ( Seg_IN : in std_logic_vector(3downto ); Seg_OUT : out std_logic_vector(6downto )); end Segment; architecture Segment_Arch of Segment is begin process(seg_in) begin case Seg_IN is when "" => Seg_OUT <= ""; when "" => Seg_OUT <= ""; when "" => Seg_OUT <= ""; when "" => Seg_OUT <= ""; when "" => Seg_OUT <= ""; when "" => Seg_OUT <= ""; when "" => Seg_OUT <= ""; when "" => Seg_OUT <= ""; when "" => Seg_OUT <= ""; when "" => Seg_OUT <= ""; when others => Seg_OUT <= ""; end case; end process; end Segment_Arch; SynopsysVHDL NO-47-5 : Structural Level Test Bench VHDL CNT_SEG VHDL library ieee; use ieeestd_logic_64all; entity CNT_SEG is port ( RESET : in std_logic; Clk : in std_logic; Seg_out : out std_logic_vector(6 downto)); end CNT_SEG; architecture CNT_SEG_Arch of CNT_SEG is component Counter port ( RESET : in std_logic; Clk : in std_logic; CNT_out : out std_logic_vector(3 downto)); end component; component Segment port ( Seg_IN : in std_logic_vector(3 downto); Seg_OUT : out std_logic_vector(6 downto)); end component; signal CNT_out : std_logic_vector(3 downto); for CNT : Counter use entity workcounter(counter_arch); for Seg : Segment use entity worksegment(segment_arch); begin CNT : Counter port map (RESET=> RESET,Clk=> Clk,CNT_out=> CNT_out); Seg : Segment port map (Seg_IN=> CNT_out,Seg_OUT=> Seg_OUT); end CNT_SEG_Arch; configuration CNT_SEG_C of CNT_SEG is for CNT_SEG_Arch end for; end CNT_SEG_C; Test-Bench VHDL library IEEE; use IEEEStd_logic_64all; entity TB_CNT_SEG is end TB_CNT_SEG; -- architecture TB_CNT_SEG_Arch of TB_CNT_SEG is component CNT_SEG port ( RESET : in std_logic; Clk : in std_logic; Seg_out : out std_logic_vector(6 downto )); end component; signal RESET : std_logic := '' ; signal Clk: std_logic := '' ; signal Seg_out : std_logic_vector(6 downto ); begin RESET <= '' after 5 ns; Clk <= not Clk after ns; Counter : CNT_SEG port map ( RESET => RESET, Clk => Clk, Seg_out => Seg_out); end TB_CNT_SEG_Arch; -- configuration TB_CNT_SEG_C of TB_CNT_SEG is for TB_CNT_SEG_Arch end for; end TB_CNT_SEG_C; SynopsysVHDL NO-48 24

-5 : VSS Simulator VHDL Source Code Analysis $ vhdlan Countervhd $ vhdlan Segmentvhd $ vhdlan CNT_SEGvhd $ vhdlan TB_CNT_SEGvhd File_Namescr, Script File ( : Compscr) Debugging Tool Loading Simulation Library Design Model $ vhdldb & Design Model SIM_WORKTB_CNT_SEG_C Waveform Waveform trace * trace /TB_CNT_SEG/Counter/CNT_out run 3 Script File File_Namescr Command include Compscr Waveform SynopsysVHDL NO-49-5 : Design Analyzer Window Design Analysis Tool Loading $ design_analyzer & Window Call SynopsysVHDL NO-5 25

-5 : VHDL File Read VHDL Source File Read Window File -> Read Window Call Window Bottom -Up, VHDL Code Read Countervhd Segmentvhd CNT_SEGvhd CNT_SEG Conter Segment SynopsysVHDL NO-5 Clock CNT_SEG Double -5 : Clock 2 Clk 3 Attribute -> clock -> Specify Apply SynopsysVHDL NO-52 26

-5 : Design Constraint Optimization Design Rule symbol Attributes -> Optimization Constraints ->Design Constraints SynopsysVHDL NO-53-5 :, Block CNT_SEG Level Component Unit Double Click SynopsysVHDL NO-54 27

-5 : Physical Design EDIF File EDIF File File -> Save as File Format EDIF File Name CNT_SEGedf SynopsysVHDL NO-55-5 : FPGA Compiler Physical Design MAX+PLUSII $ maplus2& File -> Project -> Name CNT_SEGedf MAX+PLUSII -> Compile Interface -> Edif Netlist Reader Settings Synopsys Interface -> VHDL Netlist Writer VHDL File Project Namevho Timing Assign -> Device Family FLEX8 Devices EPF8282LC84-3 Compiler Window Start SynopsysVHDL NO-56 28

-5 : Timing Simulation VHDL Source Code Function Simulation Waveform FPGA Compiler Timing VHDL File Timing Simulation Waveform SynopsysVHDL NO-57-6 : Traffic Light Controller Word Description Highway Farm road Farm Road Car Highway Green TL Car Highway Yellow Mode, Highway Yellow Mode TS, Highway Red Mode Farm Road Green Mode TL Car Farm Road Yellow Mode, Car TL Farm Road Yellow Mode Farm Road Yellow Mode TS Highway Green Mode TL (6 CLK)*(CLK 3 ), TS ( CLK)*(CLK 3 ) Farmroad FL C HL Highway Highway C FL SynopsysVHDL NO-58 29

-6 : Traffic Light Controller Block Block Diagram Module : Modular Design I/O Pin SynopsysVHDL NO-59-6 : Traffic Light Controller Car Sensor Short Time Long Time Car-Async 4- Counter CLK /Reset Car_Async CLK Car_Sync /Reset Highway Green ST count count Highway Green "" 2 ST "" 4 "" "" "" count +'' Car_Async D Q Car_Sync 4 4 "" Clk 4 D Q 4 CLK count = "" + 4 /Reset /Reset count "" "" TL TS SynopsysVHDL NO-6 3

-6 : Traffic Light Controller Light Decoders Traffic Light State Controller 4 4 High-Way Farm-Road State Table State Diagram 4 Current Net ST Reset TS TL C State State (Net state) Decoder H(F) H(F) 2 HG(FG) HY(FY) HR(FR) Not Allowed Light Decoder 3 3 Light Green Yellow Red HG HY HR FG FY FR TS TL C/ST S S S S S S S2 S2 S2 S3 S3 S TL+C Reset TS/ST S S S S S S2 S2 S3 S3 S3 S S S3 TS/ST TL+C/ST TS S2 TL C SynopsysVHDL NO-6-6 : Traffic Light Controller VHDL VHDL library IEEE; use IEEEstd_logic_64ALL; use IEEEstd_logic_unsigned"+"; entity TRAFFIC is port (RESET, CLK, C_ASYNC : in std_logic; HG, HY, HR, FG, FY, FR : out std_logic); end TRAFFIC; architecture RTL of TRAFFIC is type STATE is (S, S, S2, S3); type LIGHT is (GREEN, YELLOW, RED); signal C_STATE, N_STATE : STATE; signal H, F : LIGHT; signal C_SYNC, ST, TS, TL : std_logic; signal COUNT:std_logic_vector(3 downto ); begin A: block begin process (RESET, CLK) begin if RESET = '' then C <= ''; elsif CLK = '' and CLK'event then C <= C_ASYNC; end if; end process; --Timer counter -- HG count process (RESET, CLK) begin if RESET= then COUNT <= ; elsif CLK = '' and CLK'event then if ST = '' then COUNT <= ""; elsif C_STATE=S and COUNT= then COUNT <= COUNT; --NULL else COUNT <= COUNT + ''; end if; end if; end process; --Long time, short time TS<='' when COUNT="" else ''; TL<='' when COUNT="" else ''; --High-way ON/OFF HG<='' when H=GREEN else ''; HY<='' when H=YELLOW else ''; HR<='' when H=RED else ''; SynopsysVHDL NO-62 3

-6 : Traffic Light Controller VHDL --Farm road ON/OFF FG<='' when F=GREEN else ''; FY<='' when F=YELLOW else ''; FR<='' when F=RED else ''; end block; -- B: block begin process (RESET, CLK) begin if RESET = '' then C_STATE <= S; elsif CLK = '' and CLK'event then C_STATE <= N_STATE; end if; end process; -- timer process (C_STATE, TS, TL, C_SYNC) begin case C_STATE is when S => H <= GREEN; F <= RED; if (TL = '') and (C_SYNC = '') then N_STATE <= S; ST <= ''; else N_STATE <= S; ST <= ''; end if; when S => H <= YELLOW; F <= RED; if TS = '' then N_STATE <= S2; ST <= ''; else N_STATE <= S; ST <= ''; end if; when S2 => H <= RED; F <= GREEN; if (TL = '') or (C_SYNC = '') then N_STATE <= S3; ST <= ''; else N_STATE <= S2; ST <= ''; end if; when S3 => H <= RED; F <= YELLOW; if TS = '' then N_STATE <= S; ST <= ''; else N_STATE <= S3; ST <= ''; end if; end case; end process; end block; end RTL; SynopsysVHDL NO-63-6 : Traffic Light Controller Test Bench Simulation Test Bench Stimulus Vector Traffic Light Controller library IEEE; use IEEEstd_logic_64ALL; --Empty entity entity TB_TRAFFIC is end TB_TRAFFIC; architecture RTL of TB_TRAFFIC is --Test component component TRAFFIC port (RESET,CLK,C_AYNC : in std_logic; HG,HY,HR,FG,FY,FR : out std_logic); end component; -- signal RESET : std_logic; signal CLK : std_logic := ''; signal C_ASYNC : std_logic; signal HG,HY,HR,FG,FY,FR : std_logic; --component configuration for U : TRAFFIC use entity worktraffic(rtl); begin -- vector CLK <= not CLK after 5 sec; -- vector RESET <= '', '' after sec; --Random vector process begin C_ASYNC <= ''; wait for min; C_ASYNC <= ''; wait for 5 min; C_ASYNC <= ''; wait for 5 min; C_ASYNC <= ''; wait for 5 min; end process; -- Pin Wire U : TRAFFIC port map (RESET, CLK, C_ASYNC, HG, HY, HR, FG, FY, FR); end RTL; SynopsysVHDL NO-64 32

-6 : Traffic Light Controller VHDL Test Bench Synopsys Simulation SynopsysVHDL NO-65-6 : Traffic Light Controller Script File read -f vhdl trafficvhd group -hdl_block A group -hdl_block B create_clockclk ma_delay -to all_outputs() compile -map_effort high create_schematic write -f db write -f edif -hierarchy -o trafficedf 2 Sub-Block Block Label VHDL Block Label SynopsysVHDL NO-66 33

-6 : Traffic Light Controller -Level -Level Script File read -f vhdl trafficvhd create_clockclk ma_delay -to all_outputs() compile -map_effort high create_schematic write -f db write -f edif -hierarchy -o trafficedf 7 Flip-Flop Random Logic SynopsysVHDL NO-67-6 : Traffic Light Controller VHDL FPGA Synthesis ( NO-33 ) ALTERA Library FPGA edif SynopsysVHDL NO-68 34

-6 : Traffic Light Controller VHDL FPGA directory MAX Sub-directory trafficedf MAX directory MAX directory Ma+plus : ma2win& Project File -> Project -> Name trafficedf SynopsysVHDL NO-69-6 : Traffic Light Controller VHDL FPGA Device Options SynopsysVHDL NO-7 35

-6 : Traffic Light Controller VHDL FPGA Compiler Ma+plus II -> Compiler Processing -> Preserve All Node Name Synonyms ( bit Node Name ) Interfaces -> Edif Netlist Reader Settings Interfaces -> VHDL Netlist Writer Settings Interfaces -> VHDL Netlist Writer ( Gate Delay Timing Simulation vho ) SynopsysVHDL NO-7-6 : Traffic Light Controller VHDL FPGA Start Compiler error error rpt compile SynopsysVHDL NO-72 36

-6 : Traffic Light Controller VHDL FPGA Pin Re-Fitting rpt, compile FPGA, Ma+plus II -> Compiler, Assign -> Back-Annotate Project Hierarchy Display -> acf FPGA Chip, acf In, Out port SynopsysVHDL NO-73-6 : Traffic Light Controller VHDL FPGA, C_ASYNC : INPUT_PIN = 73 CLK : INPUT_PIN = 2; RESET : INPUT_PIN = 3; FG : OUTPUT_PIN = 3; FR : OUTPUT_PIN = 56; FY : OUTPUT_PIN = 25; HG : OUTPUT_PIN = 24; HR : OUTPUT_PIN = 28; HY : OUTPUT_PIN = 6; compiler, Ma+plus II MAX directory traffiche 27C256 ROM Download FPGA 256ROM FPGA C_ASYNC High Way Farm Road SynopsysVHDL NO-74 37

-6 : FPGA Prototyping Traffic Light Controller FPGA Board 75 77 79 8 83 3 5 7 9 74 76 78 8 82 84 2 4 6 8 3 2 72 73 5 4 7 7 7 6 68 69 9 8 66 67 2 2 64 65 23 22 62 63 25 24 6 6 27 26 58 59 29 28 56 57 3 3 54 55 52 5 48 46 44 42 4 38 36 34 32 53 5 49 47 45 43 4 39 37 35 33 VCC VCC 33 Car Detect farmway highway PUSH SW VCC PUSH SW D? 33 33 47 uf VCC R? 4 3 9 8 7 6 4 3 3 33 75 74 53 73 3 56 25 24 28 6 DATA DATA DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 RESET nconfig nsp MSEL MSEL c_async fg fr fy hg hr hy EPF8282ALC84-2 nstatus LED 33 VCC 32 A A A2 A3 A4 A5 A6 A7 A8 A9 A A A2 A3 A4 CONF_DONE K CLK 78 76 7 7 69 67 66 65 64 63 62 6 6 58 57 2 7 38 59 8 5 K 26 47 52 68 VCC VCC 9 8 7 6 5 4 3 25 24 2 23 2 26 27 2 22 A A A2 A3 A4 A5 A6 A7 A8 A9 A A A2 A3 A4 CE OE VPP 27C256 VSS 4 VDD VCC 8 O O O2 O3 O4 O5 O6 O7 2 3 5 6 7 8 9 28 VCC R? 2 TR Q 3 K C? DIS 7 uf 5 CV THR 6 R? D? K N C? uf R 4 NE555 SynopsysVHDL NO-75 38