THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE. 215 Apr.; 26(4), 424434. http://dx.doi.org/1.5515/kjkiees.215.26.4.424 ISSN 1226-3133 (Print)ISSN 2288-226X (Online) FPGA Design and Implementation of FPGA Based Real-Time Adaptive Beamformer for AESA Radar Applications 김동환 김은희 박종헌 김선주 Dong-Hwan KimEun-Hee Kim*Jong-Heon Park**Seon-Joo Kim 요약. FPGA. FPGA. VPX FPGA. QR., FPGA., FPGA. Abstract Adaptive beamforming algorithms have been widely used to remove interference and jamming in the phased array radar system. Advances in the field programmable gate array(fpga) technology now make possible the real time processing of adaptive beamforming (ABF) algorithm. In this paper, the FPGA based real-time implementation method of adaptive beamforming system(beamformer) in the pre-processor module for active electronically scanned array(aesa) radar is proposed. A compact FPGA-based adaptive beamformer is developed using commercial off the shelf(cots) FPGA board with communication via OpenVPX(Virtual Path Cross-connect) backplane. This beamformer comprises a number of high speed complex processing including QR decomposition & back substitution for matrix inversion and complex vector/matrix calculations. The implemented result shows that the adaptive beamforming patterns through FPGA correspond with results of simulation through Matlab. And also confirms the possibility of application in AESA radar due to the real time processing of ABF algorithm through FPGA. Key words: AESA, Pre-Processor Module, Adaptive Beamformer, MVDR, FPGA. 서론,, 3(The 3rd R&D Institute, Agency for Defense Development) * (Department of Defense System Engineering, Sejong University) **(Edeltech) Manuscript received January 15, 215 ; Revised March 11, 215 ; Accepted March 31, 215. (ID No. 215115-8) Corresponding Author: Dong-Hwan Kim (e-mail: kdh812@add.re.kr) 424 c Copyright The Korean Institute of Electromagnetic Engineering and Science. All Rights Reserved.
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THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE. vol. 26, no. 4, Apr. 215. (task),., FPGA DSP, DSP DSP. FPGA (systolic array)., FPGA (I/O), DSP,. (COTS) FPGA,,, [5].,.. 설계및 M&S 2-1 적응빔형성기구성 (prototype) (PCU: Processing Control Unit) (PPM: Pre-Processor Module). 2. (MRM: Multichannel Receiver Module) 16( 12 그림 2. Fig. 2. Configuration and functional data flow diagram for ABF. 4) X, 2, ADC/ DDC, 4. 4,. (redundancy), 426
FPGA,. [5]. 2-2 적응빔형성알고리즘, [6]. LCMV (Linearly Constrained Minimum Variance),.,.. min, subject to (1) w, R x, C, g [7]. (Lagrange multiplier) w LCMV. (2) (2) C v( ), v( ). ( ) = sin sin (3) d,, λ. g 1(unity), (main beam),. (C=v( ), g=1) MVDR(Minimum Variance Distortionless Response). (2), w MVDR [8]. (4) w MVDR R x.,., QRD(QR Decomposition) - RLS(Recursive Least Squares) [9]. 2-3 적응빔형성 M&S 2-2 FPGA, FPGA. 2-3-1 부배열모델링 5 X (AESA), 12 ADC DDC. 24(Az) 21(El), 54, 6, 7 4(Az) 3(El) (4) 427
THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE. vol. 26, no. 4, Apr. 215.. λ/2. 2-3-2 시뮬레이션결과 matlab. (Az), (El) 2, 3, (Az, El)=(, ) (jammer),. 3. 3 (c), (d) (a), (b), (, ). 3 2 3, 4 (, ). 4 (, ).. 2 MHz (LFM) Beam Pattern 1 8 Beam Pattern -5-1 -15 Elevation(deg) 6 4 2-2 -2 1 5 5-5 -5 Elevation(deg) -1-1 Azimuth(deg) (a) (3) (a) DBF pattern(3d) 1-4 -6-8 -1-1 -5 5 1 Azimuth(deg) (b) (2) (b) DBF pattern(2d) Beam Pattern 1 8 Beam Pattern 6-5 -1 Elevation(deg) 4 2-2 -15 1 5 Elevation(deg) -5-1 -1-5 Azimuth(deg) (c) (3) (c) ABF pattern(3d) 5 1 그림 3. (a), (b) (c), (d) Fig. 3. DBF (a), (b) and ABF (c), (d) patterns. -4-6 -8-1 -1-5 5 1 Azimuth(deg) (d) (2) (d) ABF pattern(2d) 428
FPGA -2 Elevation pattern -2 DBF+PC ABF+PC -4-4 Gain(dB) -6-8 -6-8 -1-12 -1-8 -6-4 -2 2 4 6 8 1 Elevation(deg) -1-12 -14 2 4 6 8 1 12 Gain(dB) -1-2 -3-4 -5-6 -7-8 Azimuth pattern -9-1 -8-6 -4-2 2 4 6 8 1 Azimuth(deg) 그림 4. ()/() Fig. 4. Elevation pattern(top) and azimuth pattern(bottom) of DBF and ABF. 그림 6. Fig. 6. Results of beamforming and pulse compression. Real. JNR(Jammer to Noise Ratio) SNR (Signal to Noise Ratio) 4 db 2 db. 6. (correlation),.. FPGA 구현및결과 1.5 x 14 input signal 1.5 -.5-1 -1.5 1 2 3 4 5 6 7 8 9 1 그림 5. real Fig. 5. Input real signal waveform for pulse compression., 1 usec,, (3, 3 ), 5. 5 그림 7. FPGA Fig. 7. Configuration of COTS FPGA board for ABF implementation. 429
THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE. vol. 26, no. 4, Apr. 215. 3-1 하드웨어구성 7 Mercury COTS FPGA. Xilinx FPGA XC6VLX24T-2 3, FPGA. 15, LUTS 14 Mbit RAM 768 DSP 48E1 Slices 3-2 FPGA 기능블록구성 FPGA,,,,,,. FPGA 8. 3-2-1 가중치연산블록 training QRD. QRD Givens rotations McWhirter [1],[11]. 9 4 4. 그림 9. 4 4 Fig. 9. Block diagram of systolic array for 4 4 matrix inversion. 9... (5) (6) 그림 8. FPGA Fig. 8. Block diagram of FPGA s functional configuration. 1 FPGA. X-node Y-node 66 clock latency, X-node 54 clock 1, Y- node latency 13 clock, Throughput 1/clock, 1 Y- node 54 clock 41(54-13) Y-node. X-node Y-node 11. 43
FPGA 그림 1. FPGA Fig. 1. Conceptual architecture of FPGA for weight calculation. 12 training 1(12 1 ) 5 FPGA, 2 MHz 1 usec (42 usec ), FPGA 77 %. 12 FPGA. 3-2-2 적응빔형성블록 2-3 matlab 13. matlab, FPGA. FPGA. 3-2-3 펄스압축블록, LFM. FFT zero padding FFT, IFFT. 14. 그림 11. X () Y () Fig. 11. Architecture of X-node(top) and Y-node(bottom). FFT IP LogiCORE IP Fast Fourier Transform v8., FFT 5122,48 431
THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE. vol. 26, no. 4, Apr. 215. 그림 12. Fig. 12. Flow chart and runtime for weight calculation., 32 bit single precision. 2 MHz, latency 17 usec, FPGA 38 %., 2. 15 FPGA, 16 FPGA.. 결론, COTS FPGA. MVDR, 그림 13. () FPGA() Fig. 13. Adaptive beamforming pattern using matlab(top) and FPGA(bottom). 그림 14. Fig. 14. Block diagram of pulse compression. QRD-RLS. FPGA, 1 usec (42 usec ),. FPGA 432
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