Microsoft PowerPoint - verilog_intro and project example_실험4까지 설명후 project 진행_66 [호환 모드]

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1 Verilog HDL Intro.

2 . Overview

3 ..2 HDL HDL (hardware description language) : 하드웨어를기술하고시뮬레이션, 합성을하기위해고안된프로그래밍언어 ex.) Verilog HDL, VHDL Advantages of HDL - Easy to describe hardware system - Easy to convert designs to implementations (Automatic hardware implementation by computer) - Easy to debug (Simulation by computer) - Easy for rapid prototyping. Electronic Design Automation

4 ..4 Simulation & Synthesis Simulation : 모의실험 - 만들지않으니까돈이들지않는다. - 제대로만들었는지확인하기쉽다. - 설계가틀렸을경우, 고쳐서다시시뮬레이션하여확인하기쉽다. - 모든경우를다테스트할수없으므로, 실수의가능성이항상상존한다. - HDL 을써서 simulation 과 synthesis 를함께진행하면시간과노력이절약된다. 멍청한컴퓨터가계산한결과를그대로믿다가는쫄딱망하는경우도있다! 시스템사양 human HDL simulator Synthesis : 자동화된디자인합성 - C 프로그래밍처럼 behavior 만기술하면나머지는컴퓨터가알아서합성한다. - 사람손으로할때보다최적화된결과 설계결과 동작확인 synthesizer CAD tools. Electronic Design Automation

5 HDL-Based Design Flow PLD Design specification Design entery Functional verification CPLD/FPGA Target-independent part GA/standard cell Target-dependent part Device selected Programming Prototyping Device selected Synthesis and optimization Post-synthesis verification Place and route Timing analysis Programming Prototyping Cell library selected Synthesis and optimization Post-synthesis verification Place and route Timing analysis Prototyping Synthesis Implementation -5

6 .2. Structural Description Structural Description in Verilog HDL - 주어진블록을다른 primitives 의연결로나타냄. - Symbol, schematic, HDL code 로구성. - 설계자는 symbol 과 schematic 을작성하고, HDL code 는 schematic 으로부터자동적으로생성됨. a b a b Add_half (symbol) c_out_bar sum c_out sum c_out module Add_half (sum, c_out, a, b); input a, b ; output sum, c_out ; wire c_out_bar ; xor(sum, a, b) ; nand (c_out_bar, a,b) ; not (c_out, c_out_bar) ; endmodule (schematic) (HDL code).2 Overview of Verilog HDL

7 .2. Structural Description HDL code module module_name(module_port_list); // declaration of port modes input input_mode_module_port_list ; output output_mode_module_port_list ; // declaration of internal signals wire internal_signal_list ; // design primitives primitive_name(signal_list) ; primitive_name(signal_list) ; primitive_name(signal_list) ; endmodule a b c_out_bar module Add-half (sum, c_out, a, b); // declaration of port modes input a, b ; output sum, c_out ; // declaration of internal signals wire c_out_bar ; // design primitives xor (sum, a, b) ; nand (c_out_bar, a, b) ; not (c_out, c_out_bar) ; endmodule sum c_out.2 Overview of Verilog HDL

8 .2.2 Behavioral Description Behavioral Description in Verilog HDL - input 이어떠한값일때 output 이어떠한값을갖는지를기술. - Symbol, HDL code 로구성되고 schematic 은없음. - 설계자는 symbol 과 HDL code 만을작성. a b Add_half (symbol) sum c_out module Add_half (sum, c_out, a, b); input a, b ; output sum, c_out ; reg sum, c_out ; always@(a or b) begin sum = a ^ b ; c_out = a & b; end endmodule (HDL code).2 Overview of Verilog HDL

9 .2.2 Behavioral Description HDL code module module_name(module_port_list); a b Add_half sum c_out // declaration of port modes input input_mode_module_port_list ; output output_mode_module_port_list ; // declaration of abstract memory variables reg output_mode_module_port_list ; // behavioral function always@(event_list) begin output = f(input) ; output = f(input) ; output = f(input) ; end endmodule module Add_half (sum, c_out, a, b); // declaration of port modes input a, b ; output sum, c_out ; // declaration of abstract memory variables reg sum, c_out ; // behavioral function always@(a or b) begin sum = a ^ b ; c_out = a & b ; end endmodule.2 Overview of Verilog HDL

10 .2.3 Example of Verilog HDL Behavioral Description of D-type flip-flop rst data_in Flip_flop clk q module Flip_flop (q, data_in, clk, rst); // declaration of port modes input data_in, clk, rst ; output q ; // declaration of abstract memory variables reg q ; // behavioral function always@(posedge clk) begin if (rst==) q = ; else q = data_in ; end endmodule.2 Overview of Verilog HDL

11 .2.3 Example of Verilog HDL Behavioral Description of 4-bit adder a b c_in 4 4 Adder_4 4 c_out sum module Adder_4 (sum, c_out, a, b, c_in); // declaration of port modes input [3:] a, b ; input c_in ; output [3:] sum ; output c_out ; // behavioral function assign {c_out, sum} = a + b + c_in ; endmodule.2 Overview of Verilog HDL

12 2. Syntax

13 2.. Module Module: Basic unit of design in Verilog HDL Module is never declared within another module. Structural description and behavioral descriptions can be mixed together in a single module. A module consists of: () Module port : input, output, inout (2) Module implementation (2-) Sub-modules and connections (Structural description) (2-2) Behavioral functions (Behavioral description) 2. Verilog Module

14 2..2 Module Instantiation Add_full c_in a b M a sum Add_half b c_out w w2 a sum Add_half b c_out M2 w3 M3 sum c_out module Add_full (sum, c_out, a, b); input a, b, c_in ; output sum, c_out ; wire w, w2, w3 ; Add_half M (w, w2, a, b) ; Add_half M2 (sum, w3, w, c_in) ; or M3 (c_out, w2, w3) ; endmodule module Add-half (sum, c_out, a, b); input a, b ; output sum, c_out ; wire c_out_bar ; xor (sum, a, b) ; nand (c_out_bar, a, b) ; not (c_out, c_out_bar) ; endmodule 2. Verilog Module

15 2.2. Primitives Primitive: Predefined module (=Predefined structural/functional element) Module Primitive Built-in Verilog Primitives Combitional Logic and nand or nor xor xnor buf not Three State bufif bufif notif notif MOS Gate nmos pmos rnmos rpmos CMOS Gate cmos rcmos Bi-directional Gate tran tranif tranif rtran rtranif rtranif Pull Gate pullup pulldown 2.2 Verilog Primitive

16 2.2.2 Delay Modeling # N: 입력과출력사이의지연시간을 N unit delay 로설정 #: unit delay module AOI_4_unit (y_out, x_in, x_in2, x_in3, x_in4); x_in x_in2 x_in3 x_in4 y y2 y_out input x_in, x_in2, x_in3, x_in4 ; output y_out ; wire y, y2 ; and # (y, x_in, x_in2) ; and # (y2, x_in3, x_in4) ; nor # (y_out, y, y2) ; endmodule 2.2 Verilog Primitive

17 2.3.2 Behavioral Description Continuous Assignment: - operator 를사용하여 combinational logic 을기술 a b 8 8 Bit_or8_gate 8 module Bit_or8_gate (y, a, b) ; input [7:] a, b ; output [7:] y ; assign y = a b ; endmodule y 2.3 Descriptive Style

18 Useful Operators Operator + - ~ & ^ ~& ~ ~^ arithmetic operation addition subtraction bitwise operation negation and or exclusive-or nand nor exclusive-nor module Nand2_RTL (y, x, x2) ; input x, x2 ; output y ; assign y = ~(x & x2) ; endmodule module And2_8bit_RTL (y, x, x2) ; input [7:] x ; input [7:] x2 ; output [7:] y ; assign y = x & x2 ; endmodule 2.3 Descriptive Style

19 Useful Operators Operator << >> ~ & ^ ~& ~ ~^ shift operation shift left shift right reduction operation negation and or exclusive-or nand nor exclusive-nor module Shl_4bit_RTL (y, x, c) ; input [3:]x ; input [:]c ; output [3:]y ; assign y = x << c; endmodule module And4_RTL (y, x) ; input [3:]x ; output y ; assign y = &x ; endmodule 2.3 Descriptive Style

20 Useful Operators Operator! && ==!= < <= > >= logical operation negation and or equal inequal relational operation less less or equal greater greater or equal module And2_algo (y, x, x2) ; input x, x2 ; output y ; reg y ; always@(x or x2) begin if ((x==)&&(x2==)) y = ; else y = ; end endmodule 2.3 Descriptive Style

21 2.3.2 Operator Concatenation: { } 기호를사용하여두개이상의 signal 을하나의 binary number 처럼취급 a b c_in 4 4 Adder_4 4 c_out sum module Adder_4 (sum, c_out, a, b, c_in) ; // declaration of port modes input [3:] a, b ; input c_in ; output [3:] sum ; output c_out ; // behavioral function assign {c_out, sum} = a + b + c_in ; endmodule 2.3 Descriptive Style

22 2.5.3 Sequential & Concurrent Execution of Statements Module 내의모든 statement 는 기본적으로병렬수행 always ( ) begin end 의내부에서는 그내부에서만순차적으로수행 a clk b clk 두개의 FF 은병렬적으로수행 c module Ring_osc2 (a, clk) ; input clk ; output a ; reg b, c ; // inverter not (a,c) ; // st flip-flop always@(posedge clk) begin b = a ; end // 2nd flip-flop always@(posedge clk) begin c = b ; end endmodule 2.5 Behavioral Description

23 2.5.3 Sequential & Concurrent Execution of Statements Structural Description & RTL Description (assign) : 입력신호가바뀔때마다출력신호가바뀜. // Structural description not (b,a) ; // RTL description assign c = ~b ; Algorithm-based Description (always, if) : always 이바뀔때마다 begin end 가수행됨. always@(posedge clk) begin b = a ; end 2.5 Behavioral Description

24 2.5.4 Wire & Reg Wire - Structural Description에쓰임 - module과 primitive를연결하는 signal 중에서 input, output을제외한모든 signal을 wire로선언 module Add_half (sum, c_out, a, b); a b c_out_bar sum c_out input a, b ; output sum, c_out ; wire c_out_bar ; xor (sum, a, b) ; nand (c_out_bar, a,b) ; not (c_out, c_out_bar) ; endmodule 2.5 Behavioral Description

25 2.5.4 Wire & Reg Reg - Algorithm-based Description에쓰임 - 대입문 (A = B) 의 A에해당하는모든 signal을 reg로선언 module Flip_flop (q, data_in, clk, rst) ; input data_in, clk, rst ; output q ; reg q ; always@(posedge clk) begin if (rst==) q = ; else q = data_in ; end endmodule 2.5 Behavioral Description

26 2.9. Synthesis Methods Synthesis : HDL description Physical gates and connections Synthesis for Various Description Methods - Structural description : primitive를 gate로치환한다음 logic optimization을실시 - RTL description : 각각의 assign문을 gate로변환한다음 logic optimization을실시 - Algorithm-based description : always...begin end문안의내용을 Verilog HDL이분석한다음, 그내용을수행할수있는논리회로를생성해서 gate로바꾼다음 logic optimization을실시 2.9 Synthesis

27 2.9.2 Synthesizability Synthesizability of Various Description Methods - Structural Description : 각모듈이하드웨어요소와 대로대응되므로합성이매우쉬움 - RTL Description : behavioral description이지만 assign문을손쉽게하드웨어요소로변환할수있으므로합성이비교적쉬움 - Algorithm-based Description : 프로그래밍언어로기술하므로합성이비교적어려움 - Synthesizability: Structural > RTL > Algorithm-based 2.9 Synthesis

28 2.9.3 Flexibility & Design Time Flexibility and Design Time of Various Description Methods - Structural Description : 설계를수정, 확장하기번거롭고복잡한시스템을설계하기불편하다. - RTL Description : Structural 과 Algorithm-based의중간 - Algorithm-based Description : 사람이생각하는방식대로프로그래밍언어를사용하여기술하므로, 수정, 확장이용이하고설계시간이짧음 - Flexibility: Structural < RTL < Algorithm-based - Design Time: Structural > RTL > Algorithm-based 2.9 Synthesis

29 2.. Representation of Numbers number value stored binary pattern Numbers in Verilog HDL 2 b 2 - <size> <base_format><number> 4 d - b: binary (2) 4 o 8 d: decimal () o: octal (8) h: hexadecimal (6) - number가 x 나 z 로시작하면, 자릿수를맞추고남은부분을 8 ha 5 bzx 2 hxa bz zzzx xxxxxxxx z.z(32bits) 모두 x 나 z 로채움. 3 b5 Invalid! Invalid! 2 da Invalid! Invalid! 2. Representation of Numbers

30 3. Simulation

31 3.2. Verilog HDL Simulation Design Unit Testbench (DUTB) : Verilog HDL 에서시뮬레이션을하기위해서만드는 module Unit under Test (UUT) : 시뮬레이션당하는 module Design Unit Testbench = 시뮬레이션해야할 module + stimulus generator + response monitor Stimumus generator, response monitor 는 Verilog HDL 로 기술되지만, 실제설계할하드웨어와는전혀관계가없다. 3.2 Testbench

32 3.2.2 Active-Low NAND Latch module Nand_Latch_ (q,qbar,preset,clear); output q, qbar; input preset, clear; preset # q nand # G (q, preset, qbar), G2 (qbar, clear, q); endmodule clear # qbar Preset Clear q(n+) qbar(n+) q(n) qbar(n) active low 라함은 Preset,Clear 가 일때에각각 preset latch, clear latch 의동작을수행한다는뜻이다. 3.2 Testbench

33 3.2.3 Design Unit Testbench (DUTB) 실제하드웨어테스트 Verilog HDL Simulation Design_Unit_Testbench (DUTB) Signal Generator Chip Under Test Stimulus Generator Unit_Under_Test (UUT) Oscilloscope Response Monitor 3.2 Testbench

34 3.2.3 Design Unit Testbench (DUTB) DUTB preset Stimulus Generator time UUT clear time Response Monitor 3.2 Testbench

35 3.2.4 Stimulus Generator preset time clear time # delay 후 signal change Nothing No change initial begin # preset = ; clear = ; # preset = ; # clear = ; # clear = ; # preset = ; end initial #6 $finish; 3.2 Testbench

36 3.2.5 Response Monitor initial begin $monitor( time=%2d preset=%b clear=%b q=%b qbar=%b,$time,preset,clear,q,qbar); end C++ Analogy %b:2 진수, %o:8 진수, %d: 진수, %h:6 진수 $time: simulation time 을나타내는함수 C++ Analogy printf( time=%2d preset=%d clear=%d q=%d qbar=%d, time(),preset,clear,q,qbar); 3.2 Testbench

37 3.2.6 Monitor Output When there is an event. preset clear q qbar time time time time 52 time= preset=x clear=x q=x qbar=x time= preset= clear= q=x qbar=x time= preset= clear= q= qbar=x time=2 preset= clear= q= qbar= time=2 preset= clear= q= qbar= time=3 preset= clear= q= qbar= time=3 preset= clear= q= qbar= time=32 preset= clear= q= qbar= time=4 preset= clear= q= qbar= time=5 preset= clear= q= qbar= time=5 preset= clear= q= qbar= time=52 preset= clear= q= qbar= 3.2 Testbench

38 3.2.7 DUTB Codes DUTB module test_nand_latch_; reg preset, clear; wire q, qbar; // Unit under Test Nand_Latch_ M (q,qbar,preset,clear); preset clear Stimulus Generator UUT Response Monitor q qbar // Stimulus Generator initial begin # preset = ; clear = ; # preset = ; # clear = ; # clear = ; # preset = ; end initial #6 $finish; // Response Monitor initial begin $monitor( time=%2d preset=%b clear=%b q=%b qbar=%b,$time,preset,clear,q,qbar); end endmodule

39 4. Advanced Syntax

40 4.3. Net and Register Net - data types: wire, supply, supply - structural description에주로쓰임 - physical connection을의미 Register - data types: reg, integer, real... - behavioral description에주로쓰임 - program variable (FF out, 기억의의미 ) 을의미 4.3 Data Types

41 4.3.2 How to Find Out Net and Register Register - 대입문 (A=B) 에서 A에해당하는모든 signal을 register로선언 - assign 명령어가들어가있는 continuous assignment에서는대입문이있더라도 register로선언되지않는다. Net - module 과 primitive 를연결하는 signal 중에서 input, output, register 를제외한모든 signal 을 net 로선언 4.3 Data Types

42 4.3.3 Example of Net and Register module A(O, O, I, I, I2, I3, Clk); g input I, I, I2, I3, Clk ; output O, O ; reg O, O; supply g ; wire a, b, s, c ; I I I2 I3 ^ & a b A Cin Sum Add_full B Cout s c Clk Clk O O assign a = I ^ I ; assign b = I2 & I3 ; Add_full M (s,c,a,b,g) ; always@(posedge clk) begin O = s ; end always@(posedge clk) begin O = c ; end endmodule 4.3 Data Types

43 4.3.7 Hierarchical Referencing test_add_rca_4 module test_add_rca_4; reg [3:] a, b; reg c_in; wire [3:] sum; wire c_out; a[3:] b[3:] c_in Add_rca_4 M sum[3:] A c_out M.A initial begin $monitor ($time, c_out=%b c_in4=%b c_in3=%b c_in2=%b c_in=%b, c_out, M.c_in4, M.c_in3, M.c_in2, c_in); end Add_rca_4 M(sum,c_out,a,b,c_in); endmodule a[3] b[3] a[2] b[2] a[] b[] a[] b[] c_in Add_full G4 G3 G2 G Add_full Add_full Add_full c_in4 c_in3 c_in2 c_out sum[3] sum[2] sum[] sum[]

44 4.6. Operator + - * / % arithmetic operator addition subtraction multiplication division modulus & ~& ~ ^ ~^ 또는 ^~ reduction operator reduction AND reduction NAND reduction OR reduction NOR reduction XOR reduction XNOR ~ & ~& ~ ^ ~^ 또는 ^~ bitwise operator bitwise negation bitwise AND bitwise NAND bitwise OR bitwise NOR bitwise XOR bitwise XNOR! && ==!= logical operator logical negation logical and logical or logical equality logical inequality 4.6 Operator

45 4.6. Operator relational operator shift operator < <= > >= less than less than or equal to greater than greater than or equal to << >> left shift right shift concatenation operator { A,B } concatenate A and B A? B : C conditional operator if A then B else C a[4:] = {c_out,c_in[3:]}; a = (select==)? b : c; c_out c_in[3:] b select== c select!= a[4:] a 4.6 Operator

46 7. Behavioral Description

47 7.2. Behavioral Statement Behavioral Statement - initial 또는 always로시작 - initial로시작되는 behavioral statement는 번만수행됨 - always로시작되는 behavioral statement는반복수행됨 - 모든 behavioral statement는각각병렬로수행됨 - behavioral statement 내부의 begin end 사이에서는순차적으로수행됨 7.2 Behavioral Statement

48 7.2. Behavioral Statement Clock Generator Example # module clock_gen (clock); parameter Clock_period = ; parameter Clock_disable = ; output clock; reg clock; initial clock = ; always begin #Clock_period/2 clock = ~clock; end initial #Clock_disable $finish; endmodule clock = #5 clock = ~clock # $finish Behavioral Statement

49 7.2. Behavioral Statement Clock Generator Example #2 module clock_gen2 (clock); parameter Clock_period = ; parameter Clock_period2 = 4; output clock; reg clock; initial clock = ; always begin #Clock_period clock = ; #Clock_period2 clock = ; end clock = # clock = ; #4 clock = endmodule Behavioral Statement

50 7.5.5 WAIT WAIT - event: 정해진 signal의값이변화하거나정해진 event가발생할때수행됨. - WAIT: 정해진조건이만족될때까지실행문의수행을멈추고기다림 module df(q,q_bar,clk,set,reset,data); output q,q_bar; input clk,set,reset,data; reg q; assign q_bar = ~q; clk) begin if (reset==) q=; else if (set==) q=; else q = data; end endmodule (D flip-flop) (D Latch) module latch(q,q_bar,clk,set,reset,data); output q,q_bar; input clk,set,reset,data; reg q; assign q_bar = ~q; always begin wait (clk==); if (reset==) q=; else if (set==) q=; else q = data; end endmodule 7.5. Timing Control and Synchronization

51 7.2.? : module mux(y, sel, a, b); input sel; input [5:] a, b; output [5:] y; reg [5:] y; or b or sel) y = (sel)? a : b; endmodule 7.2 Activity Flow Control

52 7.2.2 CASE module mux(y, sel, a, b); input sel; input [5:] a, b; output [5:] y; reg [5:] y; or b or sel) begin case (sel) : y = a; : y = b; default y = bx; endcase end endmodule 7.2 Activity Flow Control

53 7.2.3 IF ELSE module mux(y, sel, a, b); input sel; input [5:] a, b; output [5:] y; reg [5:] y; or b or sel) begin if (sel==) y = a; else y = b; end endmodule 7.2 Activity Flow Control

54 7.2.4 REPEAT module count_s(a, b); input [5:] a; output [4:] b; reg [4:] b; integer i; initial begin b = ; i = ; repeat (6) begin if (a[i]==) b = b + ; i = i + ; end end endmodule 7.2 Activity Flow Control

55 7.2.5 FOR module count_s(a, b); input [5:] a; output [4:] b; reg [4:] b; integer i; initial begin b = ; for (i=; i<6; i=i+) if (a[i]==) b = b + ; end endmodule 7.2 Activity Flow Control

56 7.2.6 WHILE module count_s(a, b); input [5:] a; output [4:] b; reg [4:] b; integer i; initial begin b = ; i = ; while (i<6) begin if (a[i]==) b = b + ; i = i + ; end end endmodule 7.2 Activity Flow Control

57 7.2.7 REPEAT and WHILE module count_s(a, b); input [5:] a; output [4:] b; reg [4:] b; integer i; initial begin b = ; i = ; repeat (6) begin if (a[i]==) b = b + ; i = i + ; end end endmodule repeat 문은고정된횟수만큼 loop 를수행하고, while 은주어진조건을만족하는동안 loop 를수행한다. module count_s(a, b); input [5:] a; output [4:] b; reg [4:] b; integer i; initial begin b = ; i = ; while (i<6) begin if (a[i]==) b = b + ; i = i + ; end end endmodule 7.2 Activity Flow Control

58 System Tasks for Simulation $display displays values of variables, string, or expressions $display(ep, ep2,, epn); ep, ep2,, epn: quoted strings, variables, expressions. $monitor monitors a signal when its value changes. $monitor(ep, ep2,, epn); $monitoton enables monitoring operation. $monitotoff disables monitoring operation. $stop suspends the simulation. $finish terminates the simulation. -58

59 Time Scale for Simulations Time scale compiler directive `timescale time_unit / time_precision The time_precision must not exceed the time_unit. For instance, with a timescale ns/ ps, the delay specification #5 corr esponds to 5 ns. It uses the same time unit in both behavioral and gate-level modeling. For FPGA designs, it is suggested to use ns as the time unit. -59

60 Modeling and Simulation Example (A 4-bit adder) // Gate-level description of 4-bit adder module four_bit_adder (x, y, c_in, sum, c_out); input [3:] x, y; input c_in; output [3:] sum; output c_out; wire C,C2,C3; // Intermediate carries // -- four_bit adder body-- // Instantiate the full adder full_adder fa_ (x[],y[],c_in,sum[],c); full_adder fa_2 (x[],y[],c,sum[],c2); full_adder fa_3 (x[2],y[2],c2,sum[2],c3); full_adder fa_4 (x[3],y[3],c3,sum[3],c_out); endmodule -6

61 Modeling and Simulation Example (A 4-bit adder) c_in [] [] [] fa_.ha_.c fa_.ha_2.s x[3:] y[3:] [3:] [3:] [] [] fa_.ha_.s fa_.ha_2.c fa_.cout [] [] full_adder x S y Cout Cin fa_2 [] [2] [2] full_adder x S y Cout Cin fa_3 [2] [3] [3] full_adder x S y Cout Cin fa_4 [3] [3:] sum[3:] c_out After dissolving one full adder. -6

62 Modeling and Simulation Example (A Test Bench) `timescale ns / ps // time unit is in ns. module four_bit_adder_tb; //Internal signals declarations: reg [3:] x; reg [3:] y; reg c_in; wire [3:] sum; wire c_out; // Unit Under Test port map Tools used before or after Verilog-XL in the design process, such as pre-layout and postlayout tools, produce Standard Delay Format (SDF) files. These files can include timing information for the following: Delays for module io paths, devices, ports, and interconnect delays Timing checks Timing constraints Scaling, environmental, technology, and user-defined parameters SDF files are the input for the SDF annotator, which uses the PLI as an interface to backannotate timing information into Verilog HDL designs. four_bit_adder UUT (.x(x),.y(y),.c_in(c_in),.sum(sum),.c_out(c_out)); reg [7:] i; initial begin // for use in post-map and post-par simulations. // $sdf_annotate ("four_bit_adder_map.sdf", four_bit_adder); // $sdf_annotate ("four_bit_adder_timesim.sdf", four_bit_adder); end -62

63 Modeling and Simulation Example (A Test Bench) initial for (i = ; i <= 255; i = i + ) begin x[3:] = i[7:4]; y[3:] = i[3:]; c_in ='b; #2 ; end initial #6 $finish; initial $monitor($realtime, ns %h %h %h %h", x, y, c_in, {c_out, sum}); endmodule -63

64 Modeling and Simulation Example (Simulation Results) # ns # 2ns # 4ns 2 2 # 6ns 3 3 # 8ns 4 4 # ns 5 5 # 2ns 6 6 # 4ns 7 7 # 6ns 8 8 # 8ns 9 9 # 2ns a a # 22ns b b # 24ns c c # 26ns d d # 28ns e e # 3ns f f # 32ns # 34ns 2 # 36ns 2 3 # 38ns 3 4 # 4ns 4 5 # 42ns 5 6 # 44ns 6 7 # 46ns 7 8 # 48ns 8 9 # 5ns 9 a # 52ns a b # 54ns b c -64

65 Modeling and Simulation Example -65

66 Verilog Example ( 또한개의파일의설명후 Desktop Calculator 중점 Project 추진 )

67 실험. Adder/Subtractor

68 . MUX Multiplexer 2 n data inputs, n control inputs, output used to connect 2 n points to a single point control signals = binary index of input connected to output I I S= S= Z Choose I if S = Choose I if S =. MUX

69 . MUX 2 to Multiplexer (2: MUX) Z = S' I + S I 4 to Multiplexer (4: MUX) Z = S' S' I + S' S I + S S' I 2 + S S I 3 I I I I I 2 I 3 2: MUX S 4: MUX Z Z I I I I I 2 I S S[:] 2 Z Z 8 to Multiplexer (8: MUX) Z = S2' S' S' I + S2' S' S I + S2' S S' I 2 + S2' S S I 3 + S2 S' S' I 4 + S2 S' S I 5 + S2 S S' I 6 + S2 S S I 7 I I I 2 I 3 I 4 I 5 I 6 I 7 S 8: MUX S Z I I I 2 I 3 I 4 I 5 I 6 I 7 S[2:] Z S 2 S S. MUX

70 . MUX Gate implementation of MUX S AND input S S Z I I S I S AND input S S S S S S S S Z I I I2 I3 I I Z Z I 2 I I 3 S S S. MUX

71 . MUX 8: MUX from 4: MUX and 2: MUX I I I 2 I 3 I 4 I 5 I 6 S C S C S C 2 3 S A S B Z I I I 2 I 3 I 4 I 5 I 6 I S B 2 3 S S C S S A Z I 7 S B C C. MUX

72 .2 2 s Complement s complement = bitwise complement + -> + -> (representation of -3) -> + -> (representation of 3) like 's comp except shifted one position clockwise = + 3 = Number range for n bits: - 2 n- ~ (2 n- - ) - Only one representation of - One more negative number than positive number - Easy addition / subtraction.2 Addition / Subtraction

73 .2 Addition and Subtraction 2 s Complement 2 s complement = bitwise complement + -> + -> (representation of -7) -> + -> (representation of 7) 덧셈 부호없는덧셈을수행한다. 뺄셈 2 s complement 를사용하여덧셈으로변환한후, 2 부호없는덧셈을수행한다. 4 + (+3) (+3) -4 + (-3) (-3) - 2 s complement 는덧셈, 뺄셈이간단하기때문에대부분의디지털회로에사용된다..2 Addition / Subtraction

74 .2 Addition and Subtraction (-3) - (+3) - (-3) (-2) - (+2) - (-2) (-2) - (+2) - (-2) Addition / Subtraction

75 .2 Overflow Add two positive numbers to get a negative number or two negative numbers to get a positive number = = +7.2 Addition / Subtraction

76 .3 Adder Cascaded Multi-bit Adder C2 C C A3 A2 A A A3 B3 A2 B2 A B A B B3 B2 B B S3 S2 S S + FA + FA + FA + HA S3 C2 S2 C S C S.3 Adder / Subtractor

77 .3 Half Adder Half Adder C A i B i Ai Bi Sum Carry Ai Bi Sum = Ai Bi + Ai Bi = Ai + Bi Ai Bi Carry = Ai Bi S A i Sum B i Carry Half-adder Schematic.3 Adder / Subtractor

78 .3 Full Adder Full Adder Co Ci Ai Bi S A B Ci S Co S = Ci xor A xor B S Co Ci Ci A B A B Co = B Ci + A Ci + A B = Ci (A + B) + A B.3 Adder / Subtractor

79 .3 Full Adder Standard Approach: 6 Gates A B Ci S A B Ci A B Co Alternative Implementation: 5 Gates A B Half S Adder Co A B A + B Half S Adder Co A + B + Ci Ci (A + B) S Ci + Co A B + Ci (A + B) = A B + B Ci + A Ci.3 Adder / Subtractor

80 .3 Adder / Subtractor Bitwise complement of B A - B = A + (-B) = A + (B+) = A + B + 2 s complement of B (Addition) C = A + B (Subtraction) C = A + B + A 4-bit Adder C (Addition) C = A + B + Mode if Mode= (Subtraction) C = A + B + Mode if Mode= B Mode B.3 Adder / Subtractor

81 .3 Adder / Subtractor A3 B3 A2 B2 A B A B A B A B A B A B Co FA Ci Co FA Ci Co FA Ci Co FA Ci S S S S S3 S2 S S Mode.3 Adder / Subtractor

82 .4 Adder/Subtractor 실험 () p.5 의회로를 Verilog HDL 모듈로표현하세요. Schematic A[3] B[3] A[2] B[2] A[] B[] A[] B[] A[3:] B[3:] M ADDSUB Symbol S[3:] A B A B A B A B Verilog HDL Co Ci Co Ci Co Ci Co Ci S S S S S[3] S[2] S[] S[] M module ADDSUB(S, A, B, M) endmodule.4 Adder / Subtractor 실험

83 .4 Adder/Subtractor 실험 (2) p.6 에사용된 full adder 와 mux 를 p.3 과 p.4 를참조하여 Verilog HDL 모듈로표현하세요. A B Ci A Co I I Z B S.4 Adder / Subtractor 실험

84 .4 Adder/Subtractor 실험 (3) 다음과같은연산을검증할수있도록 A[3:], B[3:], M을생성하는 stimulus generator를 Verilog HDL 코드로표현하세요. ( 가 ) 시뮬레이션끝 -4 A XXXX + (-3) -7 4 ( 나 ) B XXXX - (-3) 7 M X addition subtraction Adder / Subtractor 실험

85 .4 Adder/Subtractor 실험 (4) 시간 $time, 입력신호 A, B, M, 출력신호 S 를측정하는 response monitor 를 Verilog HDL 코드로표현하세요. initial begin $monitor( Time=%3d A=%4b B=%4b M=%b S=%4b,$time,A,B,M,S); end C++ Analogy %b:2 진수, %o:8 진수, %d: 진수, %h:6 진수 $time: simulation time 을나타내는함수 C++ Analogy printf( A=%4b B=%4b M=%4b S=%4b, time(),a,b,m,s);.4 Adder / Subtractor 실험

86 .4 Adder/Subtractor 실험 (5) 앞의 ()-(4) 에서작성한 Verilog HDL 코드를조합하여, () 의회로를테스트하는 DUTB의 Verilog HDL 코드를작성하세요. (6) SILOS 프로그램을사용하여 (5) 에서작성한 DUTB를시뮬레이션하고, 출력신호 S가시간에따라어떻게변하는지관찰하세요..4 Adder / Subtractor 실험

87 실험 2. Decoder

88 2. Decoder Decoder n control inputs, 2 n outputs used to make one point to out of 2 n points used as a minterm generator control signals = binary index of minterm S= S= Z Z Z = if S = Z = if S = 2. Decoder

89 2. Decoder Decoder O O (control) input I 2-to-4 decoder I-th output is output O O 2 O 3 I I I O O O 2 O I I 2. Decoder

90 2. Decoder Decoder as a minterm generator F = A'B'CD + A'BC'D + ABCD F 2 = ABC'D' + ABCD' + ABCD F 3 = A' + B' + C' + D' = (ABCD)' A B C D S 3 S 2 S S 4-to-6 decoder A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D F 3 F F 2 2. Decoder

91 2.2 CASE 문 module mux(y, sel, a, b); input sel; input [5:] a, b; output [5:] y; reg [5:] y; or b or sel) begin case (sel) : y = a; : y = b; default y = bx; endcase end endmodule 2.2 CASE 문

92 2.2 CASE 문 I I I O O O 2 O 3 module dec2to4(o, i); input [:] i; output [3:] o; reg [3:] o; 2 3 begin case (i) 2 b : o = 4 b; 2 b : o = 4 b; 2 b : o = 4 b; 2 b : o = 4 b; default y = 4 bxxxx; endcase end endmodule 2.2 CASE 문

93 2.3 Decoder 실험 () () p.23의회로를아래그림과같이수정한후, Verilog HDL 모듈로표현하세요. I[] I[] Symbol Schematic I[:] DECODER O[3:] Ib[] Ib[] Ob[] 4 Ob[] 3 Ob[2] 3 Ob[3] 2 2 O[3] O[2] O[] O[] Verilog HDL module DECODER( ) endmodule 2.3 Decoder 실험 ()

94 2.3 Decoder 실험 () (2) 2-to-4 Decoder 를검증할수있도록다음과같은 파형의입력신호 I 를생성하는 stimulus generator 를 Verilog HDL 코드로표현하세요. I[] I[] O[] O[] O[2] O[3] 시뮬레이션끝 I XX time 2.3 Decoder 실험 ()

95 2.3 Decoder 실험 () (3) 시간 $time, 입력신호 I, 출력신호 O를측정하는 response monitor를 Verilog HDL 코드로표현하세요. (4) 앞의 ()-(3) 에서작성한 Verilog HDL 코드를조합하여, () 의회로를테스트하는 DUTB의 Verilog HDL 코드를작성하세요. (5) SILOS 프로그램을사용하여 (4) 에서작성한 DUTB를시뮬레이션하고, 출력신호 O가시간에따라어떻게변하는지관찰하세요. 2.3 Decoder 실험 ()

96 2.4 Decoder 실험 (2) () p.26 을참조하여 2-to-4 Decoder 를 CASE 문을사용하여 Verilog HDL 모듈로표현하세요. 이때, 입력이들어가서출력이 나오기까지의 Delay 는 5 이라고가정하세요. (2) p.28 을참조하여 2-to-4 Decoder 를검증할수있는입력 신호 I 를생성하는 stimulus generator 를 Verilog HDL 코드로 표현하세요. 2.4 Decoder 실험 (2)

97 2.4 Decoder 실험 (2) (3) 시간 $time, 입력신호 I, 출력신호 O를측정하는 response monitor를 Verilog HDL 코드로표현하세요. (4) 앞의 ()-(3) 에서작성한 Verilog HDL 코드를조합하여, () 의회로를테스트하는 DUTB의 Verilog HDL 코드를작성하세요. (5) SILOS 프로그램을사용하여 (4) 에서작성한 DUTB를시뮬레이션하고, 출력신호 O가시간에따라어떻게변하는지관찰하세요. 2.4 Decoder 실험 (2)

98 실험 3. BCD Adder

99 3. BCD (Binary-Coded Decimal) 숫자 BCD 합 BCD 숫자 X +Y 2 Z 숫자 BCD BCD X 8 +Y 5 Z 3 숫자 BCD X 7 +Y 3 Z 숫자 BCD X 9 +Y 9 Z 8 3. BCD

100 3.2 BCD Adder 실험 () 다음그림과같은 4bit BCD (binary-coded decimal) adder 를 Verilog HDL 모듈로표현하세요. X[3:] Y[3:] c_out L M K A[3:] B[3:] CO Add_4 C[3:] N3 N2 N N CI c_in logic O A[3:] B[3:] CO Add_4 C[3:] CI logic Z[3:] 3.2 BCD Adder 실험

101 3.2 BCD Adder 실험 (2) p.34 에사용된 Add_4 를 Verilog HDL 모듈로표현하세요. (structural description 이든 behavioral description 이든관계 없으며, delay 는 이라고가정하세요.) 3.2 BCD Adder 실험

102 3.2 BCD Adder 실험 (3) 시간에따른 X, Y 값이다음과같도록하는 stimulus generator 를 Verilog HDL 코드로표현하세요. 시간이 눈금지난후에 X[3:] 이숫자 6(=) 의값을가지게하는 HDL 코드는 # X = 4 b 가된다. 시간 X Y 시뮬레이션끝.4 BCD Adder 실험

103 3.2 BCD Adder 실험 (4) 시간 $time, 입력신호 X, Y, 출력신호 X+Y를측정하는 response monitor를 Verilog HDL 코드로표현하세요. 이때, c_out, Z[3:] 이하나로묶여서 5bit 값으로출력되는것에주의하세요. time= X= Y= X+Y= 3.2 BCD Adder 실험

104 3.2 BCD Adder 실험 (5) 앞의 ()-(4) 에서작성한 Verilog HDL 코드를조합하여, () 의회로를테스트하는 DUTB의 Verilog HDL 코드를작성하세요. (6) SILOS 프로그램을사용하여 (5) 에서작성한 DUTB를시뮬레이션하고, 출력신호 X+Y가시간에따라어떻게변하는지관찰하세요. (7) 이실험에서만든모든파일을저장해서보관하세요. 다음실험에다시사용됩니다. 3.2 BCD Adder 실험

105 실험 4. Desktop Calculator

106 4. Desktop Calculator 실험 () 다음그림은 4자리의 진수로표시되는 6비트 BCD 숫자두개를더해서 5자리의 7-segment LED에표시하는계산기의블록도입니다. 이블록을 Verilog HDL 모듈로표현하세요. A3[3:] B3[3:] A2[3:] B2[3:] A[3:] B[3:] A[3:] B[3:] X[3:] Y[3:] X[3:] Y[3:] X[3:] Y[3:] X[3:] Y[3:] c_out c_in C2 c_out c_in C c_out c_in C c_out c_in BCD_Add_4 BCD_Add_4 BCD_Add_4 BCD_Add_4 Z[3:] Z[3:] Z[3:] Z[3:] D3[3:] D2[3:] D[3:] D[3:] X[3:] X[3:] X[3:] X[3:] BCD_LED_7 BCD_LED_7 BCD_LED_7 BCD_LED_7 Y[6:] Y[6:] Y[6:] Y[6:] logic L4 L3[6:] L2[6:] L[6:] L[6:] (Schematic) 4. Desktop Calculator 실험

107 4. Desktop Calculator 실험 A3[3:] B3[3:] A2[3:] B2[3:] A[3:] B[3:] A[3:] B[3:] BCD_Add_Calc L4 L3[6:] L2[6:] L[6:] L[6:] (Symbol) 4. Desktop Calculator 실험

108 4. Desktop Calculator 실험 (2) 다음은각각의 4비트 BCD 숫자를 7-segment LED에표시하는 BCD_LED_7 블록을나타낸것입니다. 이블록을 Verilog HDL 모듈로표현하세요. 이때, case문을사용하면편리합니다. A B C D BCD_LED_7 Y[] Y[] Y[2] Y[3] Y[4] Y[5] Y[6] Y[5] Y[4] Y[] Y[6] Y[3] Y[] Y[2] Desktop Calculator 실험

109 4. Desktop Calculator 실험 (3) 시간에따른 A~A3, B~B3의숫자값이다음과같을때입력신호 A[3:], A[3:], A2[3:], A3[3:], B[3:], B[3:], B2[3:], B3[3:] 를생성하는 stimulus generator를 Verilog HDL 코드로표현하세요. 시간이 눈금지난후에 X[3:] 이숫자 6(=) 의값을가지게하는 HDL 코드는 # X = 4 b 가된다. 시간 A A A 3 A B3 4 9 B B B 시뮬레이션끝 4. Desktop Calculator 실험

110 4. Desktop Calculator 실험 (4) 시간 $time, 입력신호 A3~A, B3~B, 출력신호 L4~L 를 측정하여다음과같이출력하는 response monitor 를 Verilog HDL 코드로표현하세요. time= A=234 B=432 L= 4. Desktop Calculator 실험

111 4. Desktop Calculator 실험 (5) 앞의 ()-(4) 에서작성한 Verilog HDL 코드와, 이전실험에서작성했던 BCD_Add_4 모듈을조합하여, () 의회로를테스트하는 DUTB의 Verilog HDL 코드를작성하세요. (6) SILOS 프로그램을사용하여 (5) 에서작성한 DUTB를시뮬레이션하고, 출력신호 L4~L가시간에따라어떻게변하는지관찰하세요. 4. Desktop Calculator 실험

112 실험 5. Barrel Shifter

113 5. CASE 문 module mux(y, sel, a, b); input sel; input [5:] a, b; output [5:] y; reg [5:] y; or b or sel) begin case (sel) : y = a; : y = b; default y = bx; endcase end endmodule 5. CASE 문

114 5.2 FOR 문 module count_s(a, b); input [5:] a; output [4:] b; reg [4:] b; integer i; initial begin b = ; for (i=; i<6; i=i+) if (a[i]==) b = b + ; end endmodule 5.2 FOR 문

115 5.3 Barrel Shifter 실험 () Barrel Shifter는입력신호 I[7:] 와제어신호 C[:], S[2:] 을받아서, C=일때에는출력신호 O[7:] = I (load), C=일때에는 O = O>>S (shift right), C=일때에는 O=O<<S (shift left), C=일때에는 O값을그대로유지시키는블록입니다. 이때, 출력신호는클록신호 Clk의 positive edge에서 #2 만큼의시간이지난후에바뀌며, 쉬프트시킨빈자리에는 이채워집니다. 5.3 Barrel Shifter 실험

116 5.3 Barrel Shifter 실험 Clk C I[7:] O O I << S I >> S I S[2:] Clk I S C #2 B O A A «B (A «B)» C X A C I[7:] C[:] S[2:] O[7:] Clk Barrel_shifter O[7:] C[:] 5.3 Barrel Shifter 실험

117 5.3 Barrel Shifter 실험 (2) p.5의 Barrel Shifter를 case문과 for문을사용하여 Verilog HDL 모듈로표현하세요. 이때, shift operator <<, >> 를사용하지마세요. ( 힌트 ) C값에따라서 load, shift left, shift right 등의동작을수행하도록하는부분은 case 문으로, I[7:] 을, S[2:] 비트만큼쉬프트시켜서 O[7:] 을생성하는부분은 for 문으로기술하세요. 5.3 Barrel Shifter 실험

118 5.3 Barrel Shifter 실험 (3) 다음과같은입력신호를생성하는 stimulus generator 를 Verilog HDL 코드로표현하세요. time I[7:] C[:] S[2:] 시뮬레이션끝 5.3 Barrel Shifter 실험

119 5.3 Barrel Shifter 실험 (4) 시간 $time, 입력신호 I, C, S, 출력신호 O 를측정하여 다음과같이출력하는 response monitor 를 Verilog HDL 코드로 표현하세요. time= I= C= S= O=XXXXXXXX (5) (2) 에서기술한 Barrel_shifter 모듈을테스트할수있도록 DUTB 를완성한후, SILOS 프로그램을사용하여시뮬레이션하고, 출력 O 를시간에따라관찰하세요. 5.3 Barrel Shifter 실험

120 실험 6. ALU

121 6. ALU 실험 () ALU는산술연산 (arithmetic operation) 과논리연산 (logic operation) 을담당하는블록으로, 마이크로프로세서의핵심블록입니다. 이번실험에서설계할 8비트 ALU는아래와같은구조와기능을가집니다. S[2:] Output F = A F = A+B F = A-B F = -A F = A B F = A & B F = A ^ B F = ~A Function Transfer Addition Subtraction Negation OR AND XOR NOT A[7:] ALU F[7:] B[7:] S[2:] 6. ALU 실험

122 6. ALU 실험 A[7:] B[7:] A[7:] B[7:] add_unit S[:] S[:] add_unit logic_unit S[:] X[7:] X[7:] S[2] mux_8 F[7:] Y[7:] A[7:] B[7:] S[:] logic_unit Y[7:] 6. ALU 실험

123 6. ALU 실험 (2) 8비트덧셈기 add_8(o,a,b), 8비트뺄셈기 sub_8(o,a,b), 8비트 MUX인 mux_8(o,a,b,s) 을 behavioral description 방식으로 Verilog HDL로표현하세요. 이때, 문제에는 carry와 borrow가표시되어있지않으므로, 이를포함하여기술하세요. (3) p.56의 add_unit 모듈을 Verilog HDL 코드로표현하세요. 이때, behavioral description을사용하지말고, (2) 에서만든 add_8, sub_8, mux_8만을사용하여 structural description으로기술하세요. ( 힌트 ) F=A, F=A+B의계산은 add_8과 mux_8로, F=A-B, F=-A의계산은 sub_8로구현할수있습니다. mux_8은모두 4개가필요합니다. 6. ALU 실험

124 6. ALU 실험 (4) p.56의 logic_unit를 Verilog HDL로표현하세요. 이때, behavioral description을사용하지말고, Verilog HDL primitives인 or, and, xor, not와 (2) 에서만든 mux_8만을사용하여 structural description으로기술하세요. ( 힌트 ) mux_8은모두 3개가필요합니다. (5) p.55 의 ALU 를 add_unit 와 logic_unit 를사용하여 Verilog HDL 모듈로표현하세요. 6. ALU 실험

125 6. ALU 실험 (6) 다음과같은입력신호를생성하는 stimulus generator 를 Verilog HDL 코드로표현하세요. time A[7:] B[7:] S[2:] 시뮬레이션끝 6. ALU 실험

126 6. ALU 실험 (7) 시간 $time, 입력신호 A, B, S, 출력신호 F 를측정하여다음과 같이출력하는 response monitor 를 Verilog HDL 코드로표현하세요. time= A= B= S= F=XXXXXXXX (8) (5) 에서기술한 ALU 모듈을테스트할수있도록 DUTB 를완성하세요. (9) SILOS 프로그램을사용하여시뮬레이션하고, 출력 F 를시간에따라 관찰하세요. 6. ALU 실험

127 실험 7. BCD to Excess-3 Code Converter

128 7. State Machine Datapath/Control Approach: Simpler to Design Computer Hardware = Datapath + Control Combinational Functional Units Registers, Buses Qualifiers Control FSM generating sequences of control signals Complex to design Small in size Little repetition Sequential logic Simple to design Large in size Much repetition Combinational logic Qualifiers and Inputs Control State Datapath "Master of Puppets" Control Signal Outputs "Puppet" 7. State Machine

129 7. State Machine Parity Checker: assert output whenever input bit stream has odd # of 's Reset Even [] Present State Even Even Odd Odd Input Next State Even Odd Odd Even Output Symbolic State Transition Table (Symbol) Odd [] State Diagram Present State Input Next State Output Encoded State Transition Table (Binary Number) 7. State Machine

130 7. State Machine Implementation Next State/Output Functions NS = PS xor PI; OUT = PS Input CLK \Reset NS D R Q Q PS/Output Input CLK \Reset T R Q Q Output D FF Implementation T FF Implementation 7. State Machine

131 7.2 Timing Timing Behavior Input Clk Output Timing Behavior: Input 7.2 Timing

132 7.2 Timing Timing: When are inputs sampled, next state computed, outputs asserted? State Time: Time between clocking events - Clocking event causes state/outputs to transition, based on inputs - After propagation delay, Next State entered, Outputs are stable NOTE: Asynchronous signals take effect immediately Synchronous signals take effect at the next clocking event ex) tri-state enable: effective immediately sync. counter clear: effective at next clock event async. counter clear: effective immediately 7.2 Timing

133 7.2 Timing Example: Positive Edge Triggered Synchronous System Inputs sampled Clock Inputs State T ime On rising edge, inputs sampled outputs, next state computed After propagation delay, outputs and next state are stable IMPORTANT: Inputs to FSM should be settled down before clock edge. Outputs Outputs and next states are stable 말로는쉽지만굉장히햇갈리고잘까먹게된다. 유일한방법은많이디자인해보는것뿐! 7.2 Timing

134 7.2 Timing Example: Positive Edge Triggered Synchronous System X FSM FSM 2 Y CLK FSM A A B Y= A [] Y= X= C [] X= X FSM 2 C D D Y= X= X= Y Y=, B [] X= D [] - Initial inputs/outputs: X =, Y = 7.2 Timing

135 7.3 Vending Machine Example General Machine Concept - deliver package of gum after 5 cents deposited - single coin slot for dimes ( cents), nickels (5 cents) - no change Step : Understand the problem: draw a block diagram Coin Sensor N D Reset Vending Machine FSM Open Gum Release Mechanism 거스름돈떼어먹는못된자판기는각성하라!!! Clk 7.3 Vending Machine Example

136 7.3 Vending Machine Example Step 2: Map into more suitable abstract representation Reset S Tabulate typical input sequences: - three nickels - nickel, dime - dime, nickel - two dimes - two nickels, dime Draw state diagram: - Inputs: N, D, reset - Output: open N S7 [open] N D S S2 N D N D S3 S4 S5 S6 [open] [open] [open] D S8 [open] 7.3 Vending Machine Example

137 7.3 Vending Machine Example Step 3: State Minimization Reset D N N N, D? 5?? 5? [open] reuse states whenever possible D Present State 5 5 Inputs D N X X Next State 5 X 5 5 X 5 5 X 5 Symbolic State Table Output Open X X X 7.3 Vending Machine Example

138 7.3 Vending Machine Example Step 4: State Assignment Present State Q Q Inputs D N Next State D D X X X X X X X X Output Open X X X X 7.3 Vending Machine Example

139 7.3 Vending Machine Example Step 5: State Register Implementation K-map for D K-map for D K-map for OPEN Q Q Q Q Q Q Q Q Q D N D N D N N N X X X X X X X X X X X X N D D D Q Q Q D = Q + D + Q N D = N Q + Q N + Q N + Q D Q N N \ Q Q D D D Q CLK Q R \reset Q \Q OPEN OPEN = Q Q Q \ N Q N Q D D D Q CLK R Q \reset Q \Q 7.3 Vending Machine Example

140 7.4 Moore Macine and Mealy Machine Moore Machine Next-State Combinational Logic State Register Output Combinational Logic Outputs are function solely of the current state Outputs change synchronously with state changes 7.4 Moore Machine and Mealy Machine

141 7.4 Moore Macine and Mealy Machine Mealy Machine Next-State Combinational Logic State Register Output Combinational Logic Outputs depend on state AND inputs Input change causes an immediate output change Asynchronous outputs 7.4 Moore Machine and Mealy Machine

142 7.4 Moore Macine and Mealy Machine Moore Machine Reset N D + Reset Reset/ (N D + Reset)/ Mealy Machine Reset [] N Reset/ N/ N D 5 [] D N D/ 5 D/ N N/ D [] N+D N D D/ N+D/ N D/ 5 5 [] Reset Reset/ Outputs are associated with State Outputs are associated with Transitions 7.4 Moore Machine and Mealy Machine

143 7.4 Moore Macine and Mealy Machine - Mealy Machine typically has fewer states than Moore Machine for same output sequence - Timing of Mealy Machine is more complex than Moore Machine Moore Machine [] / / / Mealy Machine 자신없으면 Moore Machine 으로설계하는편이수월하다. [] 2 [] Same I/O behavior but Different # of states / Mealy Machine 은 state 의수가적기때문에전문 designer 들은복잡해도그냥사용한다. 7.4 Moore Machine and Mealy Machine

144 7.5 Complex Counter Example Problem Definition A sync. 3 bit counter has a mode control M. When M =, the counter counts up in the binary sequence. When M =, the counter advances through the Gray code sequence. Binary:,,,,,,, Gray:,,,,,,, Example of Valid I/O behavior Mode Input M Current State Next State (Z2 Z Z) 7.5 Complex Counter Example

145 7.5 Complex Counter Example State Diagram of Moore Machine S [] S [] S2 [] S3 [] S4 [] S5 [] S6 [] S7 [] 7.5 Complex Counter Example

146 7.6 Traffic Controller Example Problem Definition A busy highway is intersected by a little used farmroad. Detectors C sense the presence of cars waiting on the farmroad. With no car on farmroad, light remain green in highway direction. If vehicle on farmroad, highway lights go from Green to Yellow to Red, allowing the farmroad lights to become green. These stay green only as long as a farmroad car is detected but never longer than a set interval. When these are met, farm lights transition from Green to Yellow to Red, allowing highway to return to green. Even if farmroad vehicles are waiting, highway gets at least a set interval as green. Assume you have an interval timer that generates a short time pulse (TS) and a long time pulse (TL) in response to a set (ST) signal. TS is to be used for timing yellow lights and TL for green lights. 7.6 Traffic Controller Example

147 Illustration 7.6 Traffic Controller Example Farmroad FL C HL Highway Highway HL C FL Farmroad 7.6 Traffic Controller Example

148 7.6 Traffic Controller Example Tabulation of Inputs and Outputs: Input Signal reset C TS TL Output Signal HG, HY, HR FG, FY, FR ST Description place FSM in initial state detect vehicle on farmroad short time interval expired long time interval expired Description assert green/yellow/red highway lights assert green/yellow/red farmroad lights start timing a short or long interval Tabulation of Unique States State S S S2 S3 Description Highway green (farmroad red) Highway yellow (farmroad red) Farmroad green (highway red) Farmroad yellow (highway red) 7.6 Traffic Controller Example

149 7.6 Traffic Controller Example State Diagram of Mealy Machine TL C/ST TS S TS/ST TL + C Reset S TS/ST S3 TS TL + C/ST S2 TL C S: HG S: HY S2: FG S3: FY 7.6 Traffic Controller Example

150 7.7 State Machine Reduction Parity Checker Example S [] S [] S [] S [] S2 [] - Identical output behavior on all input strings - FSMs are equivalent, but require different implementations 7.7 State Machine Reduction

151 7.7 State Machine Reduction Implement FSM with fewest possible states - Least number of flip-flops - Boundaries are power of two number of states - Fewest states usually leads to more opportunities for don't cares - Reduce the number of gates needed for implementation 7.7 State Machine Reduction

152 7.7 State Machine Reduction Goal - Identify and combine states that have equivalent behavior Approach - Equivalent States: for all input combinations, states transition to the same or equivalent states - Parity Checker Example: S, S2 are equivalent states Both output a Both transition to S on a and self-loop on a - Start with state transition table - Identify states with same output behavior - If such states transition to the same next state, they are equivalent - Combine into a single new renamed state - Repeat until no new states are combined 7.7 State Machine Reduction

153 7.7 State Machine Reduction 4-bit Sequence Detector Example Single input X, output Z Taking inputs grouped four at a time, output if last four inputs were the string or I/O Behavior: X =... Z =... Upper bound on FSM complexity Fifteen states ( ) Thirty transitions ( ) sufficient to recognize any binary string of length four! 7.7 State Machine Reduction

154 7.7 State Machine Reduction State Diagram Reset / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / 7.7 State Machine Reduction

155 7.7 State Machine Reduction State Transition Table Input Sequence Reset Present State S S S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S S S 2 S 3 S 4 Next State X = X = S S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S S S 2 S 3 S 4 S S S S S S S S S S S S S S S S Output X = X = 7.7 State Machine Reduction

156 7.7 State Machine Reduction Input Sequence Reset Present State S S S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S S S 2 S 3 S 4 Next State X = X = S S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S S S 2 S 3 S 4 S S S S S S S S S S S S S S S S Output X = X = 7.7 State Machine Reduction

157 7.7 State Machine Reduction Input Sequence Reset or Present State S S S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S ' S S 3 S 4 Next State X = X = S S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S ' S S ' S 3 S 4 S S S S S S S S S S S S S S Output X = X = 7.7 State Machine Reduction

158 7.7 State Machine Reduction Input Sequence Reset or Present State S S S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S ' S S 3 S 4 Next State X = X = S S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S ' S S ' S 3 S 4 S S S S S S S S S S S S S S Output X = X = 7.7 State Machine Reduction

159 7.7 State Machine Reduction Input Sequence Reset not ( or ) or Present State S S S 2 S 3 S 4 S 5 S 6 S 7 ' S ' Next State X = X = S S 2 S 3 S 4 S 5 S 7 ' S 7 ' S 7 ' S 7 ' S S S 6 S 7 ' S ' S ' S 7 ' S S Output X = X = 7.7 State Machine Reduction

160 7.7 State Machine Reduction Input Sequence Reset not ( or ) or Present State S S S 2 S 3 S 4 S 5 S 6 S 7 ' S ' Next State X = X = S S 2 S 3 S 4 S 5 S 7 ' S 7 ' S 7 ' S 7 ' S S S 6 S 7 ' S ' S ' S 7 ' S S Output X = X = 7.7 State Machine Reduction

161 7.7 State Machine Reduction Final Reduced State Transition Table Corresponding State Diagram Input Sequence Reset or or not ( or ) or / Present State S S S2 S3' S4' S7' S' S / / S / Next State X= X= S S2 S3' S4' S4' S3' S7' S7' S7' S' S S S S Reset / S2 / Output X= X= S3' S4',/ / /,/ S7' S' / / 7.7 State Machine Reduction

162 7.7 State Machine Reduction Row-Matching Method - Straightforward to understand and easy to implement - Problem: does not allows yield the most reduced state table! Example: 3 State Parity Checker Present State S S S 2 Next State X = X = S S S S 2 S 2 S Output No way to combine states S and S2 based on Next State Criterion! 7.7 State Machine Reduction

163 () BCD Code 와 Excess-3 Code 는 모두 4 비트코드이며, 다음 테이블과같습니다. 7.8 BCD to Excess-3 Code Converter 실험 BCD Excess-3 xxxx xxxx xxxx xxxx xxxx xxxx 7.8 BCD to Excess-3 Code Converter 실험 해당되는 BCD Code 가없으므로출력은 Don t Care

164 7.8 BCD to Excess-3 Code Converter 실험 (2) 이번실험에서설계할 BCD to Excess-3 Code는다음그림과같이 4비트의 BCD Code를 비트씩입력받아서 4비트의 Excess-3 Code를 비트씩출력하는기능과구조를가집니다. BCD Input (Serial, LSB First) Reset Clock In Rst Clk Out Excess-3 Output (Serial, LSB First) 7.8 BCD to Excess-3 Code Converter 실험

165 7.8 BCD to Excess-3 Code Converter 실험 (3) BCD to Excess-3 Code Converter 의 State Diagram 을 Mealy Machine 으로그리세요. 간략화하지말고 p.88 처럼 5 개의 State 가모두표시되어야합니다. (4) 그려진 State Diagram 에서 p.89 와같은 State Transition Table 을그리세요. (5) 그려진 State Transition Table 을가지고 p.9~p.95 와같이 State Reduction 을실시하세요. 7.8 BCD to Excess-3 Code Converter 실험

166 7.8 BCD to Excess-3 Code Converter 실험 (6) 최종 State Diagram 을 Verilog HDL 로표현하세요. Mealy Machine 의구조는다음과같으므로, 블록이 3 개가되어야합니다. Next-State Combinational Logic State Register Output Combinational Logic 7.8 BCD to Excess-3 Code Converter 실험

167 7.8 BCD to Excess-3 Code Converter 실험 (7) BCD Code 개를입력하여출력이제대로나오는지를 확인할수있도록하는 stimulus generator, response monitor, DUTB 를 Verilog HDL 로표현하세요. (8) SILOS 프로그램을사용하여시뮬레이션하고, 출력 F 를 시간에따라관찰하세요. 7.8 BCD to Excess-3 Code Converter 실험