Verilog HDL Syntax
HDL 이란? HDL(Hardware Description Language) VLSI 설계가복잡도증가및 time-to-market 감소 GLM 의 schematic 설계불가능 HDL 언어를이용한시스템및회로수준구현보편화 하드웨어기술언어논리회로의프로그래밍언어에의한표현네트리스트및프로그래밍언어적표현 다양한하드웨어설계방법지원 Structural 및 Functional 방법에의한설계 병렬처리구문의설계가능하드웨어구현이전에시뮬레이션가능 concurrent language A B C -2-
HDL 종류 VHDL ADA 와비슷한 syntax 미국국방성중심으로 1987 년표준화 (IEEE 1076) 언어기술방법이다양하고엄격함 학계에서많이사용 Verilog HDL C 와비슷한 syntax Gateway Design System 사에서개발 Cadence 로흡수 약 70% 이상의기업체에서사용 -3-
HDL 의장단점 장점설계효율화 설계기간단축 검증정확도향상 디자인재사용가능 회로기능변경용이 라이브러리화지원 공정라이브러리에무관한설계가능 -4-
일반적인 ASIC 설계흐름 Design Specification Behavioral Description RTL Description (HDL) Functional Verification Logic Synthesis Gate-Level Netlist Logical Verification Floor Planning Automatic Place & Route Back annotation Physical Layout Layout Verification Implementation -5-
Verilog 의다양한기술형태 Verilog 는다양한형태로기술될수있다. 가장일반적으로는다음의 3 가지기술형태를혼용한다 Structural model primitive (built-in verilog logic gate, 라이브러리모듈의인스턴스, 혹은사용자설계모듈 ) 들의계층적구조로기술 Dataflow model expression 을사용한 combinational logic 기술 assign target = expression 의형태 Arithmetic operators: +, -, *, /, %, >>, << Relational operators: <, <=, ==,!=, >=, >, ===,!== Logical operators: &&,,!,?: Bit-wise operators: ~, &,, ^, ~^, ^~ Reduction operators: &, ~&,, ~, ^, ~^ Concatenation, replication: {sigs } {number{ }} -6-
Verilog 의다양한기술형태 Behavioral model Blocking assignment, non-blocking assignment, conditional statement, case statement 등으로기술된 always, initial block 으로기술 RTL 설계 Register Transfer Level 설계 회로구성요소인 register들과그들사이의데이터전송관계를표현 Clock 존재 논리합성의대상 일반적으로 dataflow model + behavioral model 을의미 -7-
Verilog 코딩의기본구조 모듈 (Module) Verilog HDL 프로그램의기본구조 대소문자구별 Statement terminator 로 semicolon 을사용 Timing specification 은시뮬레이션을위해서사용 module module_name(port_list); port declarations data type declarations circuit functionality endmodule timing specifications -8-
모듈의구성요소 module (port (port list) list) Timing Specificatons port port declarations data data type type declaratoins circuit functionality subprograms input output input net net register parameter continuous assignment assign procedural blocks initial block instantiation task task function system tasks tasks always block compiler directives -9-
모듈구조예 module Add_half_1 (sum, c_out, a, b); input a, b; output sum, c_out; wire c_out_bar; xor (sum, a, b); nand (c_out_bar, a, b); not (c_out, c_out_bar); endmodule 모듈선언 포트선언 데이터타입선언 회로 function 기술 Predefined primitives 를사용하여 instantiation a b Add_half_1 sum c_out c_out Sum = a ^ b C_out = a & b -10-
모듈구조예 module Add_half_2 (sum, c_out, a, b); input a, b; output sum, c_out; assign {c_out, sum} = a + b; endmodule 회로 function 기술 continuous assignment 구문사용 a b Add_half_2 sum c_out Sum = a ^ b C_out = a & b -11-
모듈구조예 module Add_full (sum, c_out, a, b, c_in); input a, b, c_in; output sum, c_out; wire w1, w2, w3; Add_half_1 M1 (w1, w2, a, b); Add_half_2 M2 (sum, w3, w1, c_in); or (c_out, w2, w3); endmodule 기존에설계한 half_adder 를이용한 Structural description module instantiation 사용 (parent module / child module) module instantiation 시반드시 module instance name 이들어가야함 (primitive instantiation 시는 optional) c_in w1 M2 w3 sum a b M1 w2 c_out -12-
모듈구조예 module full_adder (sum, carryout, in1, in2, carryin); input in1, in2, carryin; output sum, carryout; reg sum, carryout; always @(in1 or in2) begin {carryout, sum} = in1+in2+carryin; end sum HA = a ^ b c_out HA = ab sum FA = (a + b) ^ c_in c_out FA = (a + b) c_in + abc_in Half_adder 의결과를 sum 을연산자 +, c_out 를연산자 & 로치환하면 sum FA = (a + b) + c_in c_out FA = a&b a&b&c_in endmodule in1 in2 carryout full_adder carryin sum -13-
모듈구조예 module stimulus; reg clk; reg reset; wire [3:0] q; ripple_carry_counter r1(q, clk, reset); initial clk = 1 b0; always #5 clk = ~clk; initial begin reset = 1 b1; #15 reset = 1 b0; #180 reset = 1 b1; #10 reset = 1 b0; #20 $finish; end initial $ monitor($time, output q = %d, q); endmodule task 및 Timing specification -14-
포트선언 포트리스트모듈에사용되는포트이름의 list 예 : module mux_latch(y_out, sel_a, sel_b, data_a, data_b); 포트타입 input : 입력포트 output : 출력포트 inout : 입 출력포트포트선언포트리스트에나열된포트명의타입을결정하는과정을의미 <port type> <port_name>; 예 input sel_a, sel_b, data_a, data_b; output y_out; input [3:0] a; output [3:0] a, b; -15-
데이터형태 물리적데이터형태 논리값종류 논리값 0 1 X Z 의미논리적 0 값또는조건False 논리적 1 값또는조건True Unknown 논리값 High impedance 추상적테이터형태 Integer, real, time 등 논리값 integer Count integer K[1:63] 의미 32 bit integer Array of 64 integers -16-
데이터형태 변수선언 ( 데이터형태선언 ) 종류 reg : register (latch 또는 flip-flop) 일시적으로데이터를저장하는변수를의미 하드웨어레지스터를의미하지는않는다 always, initial 문등에서사용 예 : reg alu_reg; reg [7:0] alu_reg; wire : net ( 배선 ) 값저장불가능 assign 문에서사용 예 : wire adder_out; wire [15:0] adder_out, mult_out; constant 파라미터를이용하여변수값을사용할때 -17-
데이터형 수표현 Sized 또는 unsized 형식의수표현가능 Sized 형식의수표현 형식 : <size> <base format><number> 예 : 3 b010 //3 의 prefix 는수의 size 를의미 Unsized 형식의수표현 Base format 이없는경우는 default 로 decimal 을의미 Size 가없는경우는 default 로 32-bit 의수를의미 예 : 321 //32-bit 을갖는 decimal number 321 을의미 Base format Decimal : d 또는 D Hexadecimal : h 또는 H Binary : b 또는 B Octal : o 또는 O -18-
데이터형 수표현 음수의표현 <size> 앞에 부호를위치하여표현 예 : -8 d3 //3 의 2 의보수형태로저장된 8bit 의음수 틀린예 : 4 d-2 수의확장법칙 MSB 가 0, X, 또는 Z 인경우 각각MSB가 0, X, Z가되도록확장 예 : 3 b01 = 3 b001, 3 bx1 = 3 bxx1, 3 bz = 3 bzzz MSB 가 1 인경우 MSB를 0으로채우는방향으로확장 예 : 3 b1 = 3 b001-19-
데이터형 수표현 Number #Bits Base Dec. Equiv. Stored 10 32 Decimal 10 00...01010 2 b10 2 Binary 2 10 3 d5 3 Decimal 5 101 8 o5 8 Octal 5 00000101 8 ha 8 Hex 10 00001010 3 b01x 3 Binary - 01x 12 hx 12 Hex - xxxxxxxxxxxx 8 b0000_0001 8 Binary 1 00000001 8 bx01 8 Binary - xxxxxx01 8 HAD 8 Hex 173 10101101-20-
연산자 Binary 연산자의종류 Operator Name Comments + Addition - Subtraction * Multiplication / Division Divide by zero produces an x. % Modulus ( 예 ) A = 4 b0011, B = 4 b0100, D = 6, E =4 일때 A * B = 4 b1100 D / E = 1 //Truncates any fractional part A + B = 4 b0111 B A = 4 b0001 13 % 3 = 1 ( 예 ) 어떤 operand bit이 x값을가지면전체연산결과는 x 이다. in1 = 4 b101x, in2 = 4 b1010 일때 Sum = in1 + in 2; //sum은 4 bx -7 % 2 = -1 // 첫번째operand의부호 7 % -2 = 1 // 첫번째operand의부호 -21-
연산자관계연산자 Operator Name Comments > Greater than >= Greater than or equal < Less than <= Less than or equal == Logical equality!= Logical inequality ( 예 ) ain = 3 b010, bin = 3 b100, cin = 3 b111, din = 3 b01z, ein = 3 b01x일때 ain > bin 은 false(1 b0) 의결과 ain < bin 은 ture(1 b1) 의결과 ain >= bin 은 unknown(1 bx) 의결과 ain <= ein은 unknown(1 bx) 의결과 -22-
연산자논리연산자 Operator Name! Logical negation && Logical AND Logical OR Comments ( 예 ) A = 3 ; B = 0; A && B //Evaluates to 0. Equivalent to (logical 1 && logical 0) A B //Evaluates to 1. Equivalent to (logical 1 && logical 0)!A //Evaluates to 0. Equivalent to not(logical 1)!B //Evaluates to 1. Equivalent to not(logical 0) A = 2 b0x ; B = 2 b10; A && B //Evaluates to x. Equivalent to (x && logical 1) (a == 2) && (b == 3) //Evaluates to 1 if both a == 2 and b==3 are true -23-
연산자 Bitwise 연산자 Operator Name Comments ~ Bitwise negation & Bitwise AND Bitwise OR ^ Bitwise XOR ~& Bitwise NAND ~ Bitwise NOR ~^ or ^~ Bitwise XNOR Bitwise NOT XOR 만일두 operand의길이가다르면짧은길이의 operand가 0으로 left-extend ( 예 ) X = 4 b1010, Y = 4 b1101, Z = 4 b10x1일때 ~X //Result is 4 b0101 X & Y //Result is 4 b1000 X Y //Result is 4 b1111 X ^ Y //Result is 4 b0111 X ^~ Y //Result is 4 b1000 X & Z //Result is 4 b10x0-24-
연산자 Unary Reduction 연산자 Operator Name & AND reduction OR reduction ^ XOR reduction ~& NAND reduction ~ NOR reduction ~^ XNOR reduction Comments vector를하나의 bit로줄이는연산을수행한다. X 또는 Z는연산자에따라서 unknown일수도있고known일수도있다. ( 예 ) ain = 5 b10101, bin = 4 b0011, cin = 3 bz00, din = 3 bx011일때 &ain //Result is 1 b0 ~&ain //Result is 1 b1 cin //Result is 1 bx &din //Result is 1 b0-25-
연산자 Equality 연산자 Operator Name Possible Logic Comments Value == Equality 0, 1, x!= Inequality 0, 1, x === Case equality 0, 1 including x and Z!== Case inequality 0, 1 including x and Z case equality 와 case inequality 를제외하고 operand 에 X 나 Z 를포함하면결과는 unknown ( 예 ) A = 4, B = 3, X = 4 b1010, Y = 4 b1101, Z = 4 b1xxz, M = 4 b1xxz, N = 4 b1xxx 일때 A == B //Result is logical 0 X!= Y //Result is logical 1 X == Z //Result is x Z == M //Result is logical 1(all bits match, including x and z) Z == N //Result is logical 0(least significant bit does not match) M!= N //Result is logical 1-26-
연산자기타연산자 Operator Name Comments << Shift left Vacated bit positions are filled with zeros, e. g., A = A << 2; shifts A two bits to left with zero fill. >> Shift right Vacated bit positions are filled with zeros.? : Conditional Assigns one of two values depending on the conditional expression. E. g., A = C>D? B+3 : B-2 means if C greater than D, the value of A is B+3 otherwise B-2. { } Concatenate ain = 3 b010, bin = 4 b1100 {ain, bin} results 7 b0101100 { { } } Replicate {3{2 b10}} results 6 b101010-27-
Multi bit 선언 신호선언 [MSB:LSB] Input [7:0] abus; reg [15:8] add; 한비트의선택 assign abc = abus[5] ; assign abus[5] = abc ; 여러신호를하나의신호로할당 assign abcd[15:0] = {abus[7:0],add[15:8]} ; -28-
Array Register 형은 array 로선언가능 Reg [15:0] mem [0:255]; mem 은 16bit * 256word, 512 byte 의메모리 resister 배열은 bit 선택과부분선택불가 반드시 word 단위의액세스 Bit 선택이나부분선택 일시적인 net 신호를이용 Ex) wire [15:0] temp; assign temp = mem [100]; -29-
기술방법 (Description) 구조적기술방법 (Structural description) Explicit structural description Primitive 또는라이브러리셀의 instance 및연결을통한기술 Implicit structural description Continuous assignment를통한기술 동작기술방법 (Behavioral description) 회로의동작을기술함으로설계하는방법대표적으로 initial, always behavior를사용 Procedural block 과 procedural statement로구성 -30-
기술방법 Explicit description module 8bit_or_gate (y, a, b) ; input [7:0] a, b ; output y ; or G1 (y, a, b) ; endmodule module 8bit_or_gate (y, a, b) ; input [7:0] a, b ; output y ; or8bit (y, a, b) ; endmodule Primitive 를이용한기술 라이브러리셀을이용한기술 Implicit description module 8bit_or_gate (y, a, b) ; input [7:0] a, b ; output y ; assign y = a b ; endmodule -31-
정보통신용정보통신용 SoC SoC 설계연구실설계연구실 -32- Primitives Primitives Predetermined primitives pullup pulldown tran tranif0 tranif1 rtran rtranif0 rtranif1 cmos rcmos nmos pmos rnmos rpmos bufif0 bufif1 notif0 notif1 and nand or nor xor xnor buf not Pull Gates Bi-Directional Gates CMOS Gates MOS Gates Three State Combinationa l logic
Module instantiation Port connection 의 2 가지방법 Connecting by ordered list Connecting ports by name Connecting by ordered list module Top; reg [3:0] A, B; reg C_IN; wire[3:0] SUM; wire C_OUT; fulladd4 fa_ordered(sum, C_OUT, A, B, C_IN);. <stimulus>. endmodule module fulladd4(sum, c_out, a, b, c_in); output [3:0] sum; output c_out; input [3:0] a, b; input c_in; <module internals> endmodule -33-
Module instantiation Connecting ports by name module Top; reg [3:0] A, B; reg C_IN; wire[3:0] SUM; wire C_OUT; fulladd4 fa_byname(.c_out(c_out),.sum(sum),.b(b),.c_in(c_in),.a(a) );. module fulladd4(sum, c_out, a, b, c_in); <stimulus> output [3:0] sum;. output c_out; endmodule input [3:0] a, b; input c_in; <module internals> endmodule -34-
Continuous Assignments Continuous Assignments Wire 에값을가하고 update 하기위해사용 LHS (Left Hand Side) 의데이터타입은항상 net data type이여야한다 Always active RHS (Right Hand Side) 의어느한operand라도변화하면, expression은실행되고 LHS 값은즉시 update 된다 RHS 의데이터타입은 net, register, function call 등어떤것이여도상관없다 implicit continuous assignment wire adder_out = mult_out + out; implicit continuous assignment wire adder_out; assign adder_out = mult_out+out; -35-
Procedural Blocks Procedure 의정의 sequential 하게동작하는코드부분을의미 procedural statement procedure 안에존재하는 statement 예를들어, 2-to-1 MUX 의경우 Execution Flow begin if (sel == 0) Y = B; else Y = A; end Procedural assignments: Y must must be be reg reg!!!! -36-
Initial Block Initial block 시뮬레이션을위한초기화, 모니터링, waveform의기술시에주로사용된다시뮬레이션타임 0에서시작하여오직 1번만실행된다 하나의 initial block 이여러개의 behavioral statement 를가질경우 begin ~ end 로 group 되어야한다 독립적인 initial block 은서로 concurrent 하다 Initial block 내부의 statement 들은 sequential 하게동작한다 initial block 은중첩될수없다 synthesis 되지않는다 -37-
Initial Block module TestBench; reg a, b, c, d; initial a = 1 b0; initial begin b = 1 b1; #5 c = 1 b0; #10 d = 1 b0; end initial #20 $finish; endmodule Time 0 5 15 20 simulation event a = 1 b0; b = 1 b1; c = 1 b0; d = 1 b0; $finish -38-
Always Block Always block 항상반복되는행동블록을모델링할때사용시뮬레이션타임 0 에서시작하여시뮬레이션이끝날때까지반복 C 언어의무한루프와비슷한개념 $finish 나 $stop 에의해서만정지하나의 always block 이여러개의 behavioral statement 를가질경우 begin ~ end 로 group 되어야한다독립적인 initial block 은서로 concurrent 하다 Initial block 내부의 statement 들은 sequential 하게동작한다 ( 예 ) 클록발생모듈을기술 initial clk = 1 b0; always #10 clk = ~ clk; initial #1000 $finish; -39-
Initial vs Always Statement Looks like Starts How it works Use in Synthesis? initial always initial begin end always begin end Starts when simulation starts Execute once and stop Continually loop while (power on) do statements; Not used in synthesis Used in synthesis -40-
Timing Control Timing control Procedural statement 가실행될때 simulation time 을규정하는방법을제공 Timing control 의 3 가지방법 Delay-based timing control Event-based timing control Level-based timing control -41-
Delay-based Timing Control(cont d) Delay statement 를 encounter 한부터그 statement 를실행하기전까지의시간 Delay-based timing control 의 3 가지형태 Regular delay control Intra-assignment delay control Zero-delay control Syntax <delay> ::= #<NUMBER> = #<identifier> = #(<mintypemax_exp><,<mintypmax_exp>>*) -42-
Delay-based Timing Control (cont d) Regular Delay Control Delay symbol 으로 # 을사용 procedural assignment의왼쪽에 non-zero delay를규정 statement가 encounter되는시뮬레이션타임을기준으로 delay 를적용 parameter latency = 20; parameter delta = 2; reg x, y, z, p, q; initial begin x = 0; #10 y = 1; //delay control with a number #latency z = 0; //delay control with identifier #(latency + delta) p = 1; //delay control with expression #y x = x + 1; //delay control with identifier #(4:5:6) q = 0; //minimum, typical, maximum delay value end -43-
Delay-based Timing Control (cont d) Intra-assignment delay control assignment 의우변에 delay 를규정 regular vs intra-assignment regular assignment 문장전체를 delay intra-assignment delay 없이우변의표현을계산, 좌변으로의대입을 delay reg x, y, z; initial begin x = 0; z = 0; y = #5 x + z; //Take value of x and z at the time=0, evaluate end //x+z and then wait 5 time units to assign value to y initial begin x =0; z =0; temp_xz = x + z; #5 y = temp_xz; //Take value of x + z at the current time and end //store it in a temporary variable. Even though // x and z might change between 0 and 5, the value // assigned to y at time 5 is unaffected. -44-
Delay-based Timing Control Zero Delay Control #0 의 symbol 사용 동일한시뮬레이션타임에서로다른 initial/always block 의 statement 의실행순서는 non-deterministic zero delay는동일한시뮬레이션타임에실행되는 statement 중에서제일나중에실행되는것을보장동일한시뮬레이션타임에여러개의 zero delay를사용한경우 는역시 non-deterministic race condition 을막을수있다 initial begin x = 0; y= 0; end initial begin #0 x = 1; #0 y = 1; end -45-
Event-based Timing Control (cont d) Event : register 나 net 값의변화 Event-based timing control event 가발생하는시점을기준으로어떤 statement 가실행되도록기술하는방법 Event-based timing control 의종류 Regular event control Named event control Event OR control -46-
Event-based Timing Control (cont d) Regular event control 형식 : @(<event>) event 의종류 posedge sig: sig 신호가임의의값에서 1로변화또는0에서임의의값으로변화 negedge sig : sig 신호가임의의값에서 0으로변화또는 1에서임의의값으로변화 sig : sig 신호의임의의변화 @(clock) q = d; // q=d is executed whenever signal clock changes values @(posedge clock) q = d; //q=d is executed whenever signal clock does a //positive transition (0 to 1, x, or z, x to 1, z to 1) @(negedge clock) q = d; //q=d is executed whenever signal clock does a //negative transition (1 to 0, x or z, x to 0, z to 0) q = @(posedge clock) d; //d is evaluated immediately and assigned to q //at the positive edge of clock -47-
Event-based Timing Control Event OR control 다수의 event 중에어느한 event 가발생하였을때 block 이 trigger 되도록할때사용 sensitivity list : 일련의 event 들. event 사이에 or keyword 사용 always @(reset or clock or d) //wait for reset or clock or d to change begin if(reset) q = 1 b0; else if(clock) q = d; end -48-
Procedural Statement if-else statement 어떤조건을근거로하여 statement를실행할것인지를결정하는데사용 TOP에서 BOTTOM으로조건평가실시 모든조건이 false 이면 else 에관계되는 statement 를실행 if(<condition1>) sequence of statement(s) else if(<condition2>) sequence of statement(s) else sequence of statements(s) E.g. 4-to-1 mux module mux4_1(out, in, sel); output out; input [3:0] in; input [1:0] sel; reg out; wire [3:0] in; wire [1:0] sel; always @(in or sel) if (sel == 0) out = in[0]; else if (sel == 1) out = in[1]; else if (sel == 2) out = in[2]; else out = in[3]; endmodule -49-
Procedural Statement case statement if else 와같이조건평가에의한 statement 의실행 모든가능한조건이고려되어야함 default : 기술되지않은모든가능한조건에해당 중첩될수있다 expression의결과와 condition의 bit 수가같지않을때는 MSB 부터 0 fill 한다 case (expression) <condition1>: sequence of statement(s) <condition2>: sequence of statement(s) default : sequence of statement(s) endcase E.g. 4-to-1 mux module mux4_1(out, in, sel); output out; input [3:0] in; input [1:0] sel; reg out; wire [3:0] in; wire [1:0] sel; always @(in or sel) case (sel) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; endcase endmodule -50-
Procedural Statement forever 시뮬레이션동안 $finish 를만날때까지무한 loop 를수행 Testbench 안에서 clock generation module 기술에주로사용 module test; reg clk; initial begin clk = 0; forever #10 clk = ~clk; end T clk = clk 20 20 time time units units other_module1 o1(clk,..); other_module2 o2(.., clk,..); endmodule -51-
Procedural Statement For loop 의시작에서일단한번 statement 를실행하고 expression 이참일때만계속 loop 를실행 module count(y, start); output [3:0] Y; input start; reg [3:0] Y; wire start; integer i; initial Y = 0; always @(posedge start) for (i = 0; i < 3; i = i + 1) #10 Y = Y + 1; endmodule -52-
Blocking vs. Non-Blocking Blocking procedural assignment = 토큰사용 Evaluation과 assignment가동일한시뮬레이션스텝에서발생 Procedure 내에서 execution flow는 assignment가완료될때까지 block된다 -53-
Blocking vs. Non-Blocking Non-blocking procedural assignment <= 토큰사용 Evaluation 과 assignment 가두개의시뮬레이션스텝으로분리 우변값은즉시 evaluation 된다 좌변으로의 assignment는현재타임스텝의모든evaluation이완료될때까지연기된다 Procedure 내에서 execution flow는새로운 timing control을만날때까지계속진행된다 (non-block) -54-
Blocking vs. Non-Blocking 시뮬레이션스케줄링규칙각각의 verilog 시뮬레이션타임스탭은다음과같은 4 개의 queue 로구성된다 Queue1 모든 non-blocking assignment 의 RHS 를계산하고 procedural timing control 에의해서규정된시뮬레이션타임에 assign 이발생하도록 scheduling 모든 blocking assignment 의 RHS 를계산하고동시에 LHS 를 update 모든 continuous assignment 의 RHS 를계산하고동시에 LHS 를 update 모든 primitive 의 input, output 의변화를계산 $display, $write 처리 Queue2 모든 non-blocking assignment 의 LHS 를변화 Queue3 $monitor, $strobe 처리 reason_synchronize 로 PLI 를호출 Queue4 reason_rosynchronize 로 PLI 호출 -55-
Blocking vs. Non-Blocking module evaluates; reg a, b, c; initial begin a = 0; b = 1; c = 0; end always c = #5 ~c; always @(posedge c) begin a <= b; b <= a; end endmodule -56-
Blocking vs. Non-Blocking module evaluates; reg a, b, c; initial begin a = 0; b = 1; c = 0; end always c = #5 ~c; always @(posedge c) begin a = b; b = a; end endmodule -57-
Sequential Block vs. Parallel Block Sequential Block begin ~ end 사이의 statement 들은 sequential 하게동작 initial 과 always block 에 sequential 하게동작하기원하는다수의 statement 가존재할경우는 begin ~ end 로묶는다 Sequential block 과 parallel block 은중첩될수있다 -58-
Timing Control 과 Synthesis module mux_sample(f, sel, b, c); output f; input sel, b, c; reg f; always @(sel or b or c) if(sel == 1'b1) f = b; else f = c; endmodule module mux_sample(f, sel, b, c); output f; input sel, b, c; reg f; always @(sel or b or c) if(sel == 1'b1) #5 f = b; else #88 f = c; endmodule Synthesis tool 은 time delay 를무시 Synthesis tool은 combinational 입력으로부터출력까지의최소화하려는노력을하기때문 propagation 을 -59-
Procedural Block 과 Synthesis module mux_sample(f, sel, a, b, c, d); output f; input [1:0] sel; input a, b, c, d; reg f; always @(sel or a) if(sel == 2'b00) f = a; always @(sel or b) if(sel == 2'b01) f = b; always @(sel or c) if(sel == 2'b10) f = c; 하나의신호를 2 개이상의 always 문에서출력할때 always @(sel or d) if(sel == 2'b11) f = d; endmodule 시뮬레이션결과와 synthesis 결과가같지않을수있으므로피해야한다 -60-
Behavioral Construct 를사용한 Combinational Circuit 표현 Behavioral Construct (always, if) 를사용한 mux 표현 아래의 verilog code 는간단한 2:1 mux 를표현한것 아래의 verilog code 는합성가능 reg f를선언하였는데도불구하고 synthesis tool은 combinational 회로로인식 combinational 회로 : 출력이오직입력의함수에만의존 ( 이전출력값의함수가아님 ) module mux (f, sel, b, c); output f; input sel, b, c; reg f; always @ (sel or b or c) if (sel == 1) f = b; else f = c; endmodule -61-
Behavioral Construct 를사용한 Combinational Circuit 표현 Combinational 회로표현의규칙 initial 은합성불가능하므로 always 의경우만해당 Block 의모든입력 (always block 내 assignment 구문의 RHS 에사용된모든신호, 또는조건문의 RHS 에사용된신호 ) 이 sensitivity list 에존재해야한다 Block 의모든출력이모든 control path 에기술되어야한다 control path : always 구문이동작할때실행되는일련의동작 module mux (f, sel, b, c); output f; input sel, b, c; reg f; always @ (sel or b or c) if (sel == 1) control path1 f = b; else f = c; control path2 endmodule -62-
Behavioral Construct 를사용한 Combinational Circuit 표현 module blah (f, g, a, b, c); output f, g; input a, b, c; reg f, g; always @ (a or b or c) if (a == 1) f = b; else g = c; endmodule a == 0 이면 f = old value (seq.) module blah (f, g, a, b, c); output f, g; input a, b, c; reg f, g; always @ (a or b or c) if (a == 1) f = b; else f = c; endmodule -63-
Behavioral Construct 를사용한 Combinational Circuit 표현 다음과같이한다면? module sample(f, g, a, b, c); output f, g; input a, b, c; reg f, g; always @(a or b or c) begin f = 0 ; g = 0 ; if (a == 1) f = b; else g = c; end endmodule -Function 이복잡한경우모든 control path 에출력값을할당하였는지잘알지못함 - 모든출력값을 known value( 예에서는 0) 로할당하고각 control path 에서는필요한값만할당 - synthesis tool 은 combinational 회로로인식 -64-
Behavioral Construct 를사용한 Combinational Circuit 표현 Case 구문을사용한경우 마치 case 구문을사용하여진리표를표현하는것과같은의미 모든입력조합에대해서기술해주어야한다 module fred (f, a, b, c); output f; input a, b, c; reg f; always @ (a or b or c) case ({a, b, c}) 3 b000: f = 1 b0; 3 b001: f = 1 b1; 3 b010: f = 1 b1; 3 b011: f = 1 b1; 3 b100: f = 1 b1; 3 b101: f = 1 b0; 3 b110: f = 1 b0; 3 b111: f = 1 b1; endcase endmodule abc = 3 b1xz 와같은표현은 simulation 에서는의미를갖으나 synthesis 회로에서는의미를갖지않는다그러므로위의경우는 full case description 이라할수있다 -65-
Behavioral Construct 를사용한 Combinational Circuit 표현 module caseexample(f, a, b, c); output f; input a, b, c; reg f; always @ (a or b or c) case ({a, b, c}) 3 b001: f = 1 b1; 3 b010: f = 1 b1; 3 b011: f = 1 b1; 3 b100: f = 1 b1; 3 b111: f = 1 b1; 3 b110: f = 1 b0; default: f = 1 bx; endcase endmodule c ab 0 1 00 01 11 10 x 1 0 1 1 1 1 x 위와같이 default 를기술한경우는위와같은진리표를이용하여 combinational 회로를합성그러므로역시 full case description -66-
Behavioral Construct 를사용한 Combinational Circuit 표현 Full case description 을하지않은경우 module truth(f, a, b, c); output f; input a, b, c; reg f; always @(a or b or c) case({a, b, c}) 3'b000 : f = 1'b0; 3'b001 : f = 1'b1; 3'b010 : f = 1'b1; 3'b011 : f = 1'b1; 3'b100 : f = 1'b1; endcase endmodule latch 삽입 -67-
Verilog Coding Guideline for Synthesis 일반적으로 synthesis tool 에서합성지원되지않는 verilog 문법들 Initial Loops repeat forever While Data types event real time UDPs Fork join blocks Procedural assignments assign and desassign force and release disable Some operators / and % === and!== -68-
Verilog Coding Guideline for Synthesis 레지스터의초기화 신호의초기화를위해서 initial 을사용하지않는다 initial 은 synthesis 불가능 다음의 template 를사용 // Bad coding initial data <= 1 b0 ; // Good coding // Asynchronous RESET always @ (posedge RESET or poesedge clk) if (RESET) data <= 1 b0 ; else data <= data_in ; always @ (posedge clk) data <= data_in // Better coding // Synchronous RESET always @(poesedge clk) if (RESET) data <= 1 b0 ; else data <= data_in ; -69-
Verilog Coding Guideline for Synthesis 불필요한 latch 의사용을피하라 case 나 if-else statement 에 default value 를사용 모든입력조건에모든출력신호값을할당 // latch 를사용하여합성 always @ (d) begin case (d) 2 b00: z <= 1 b1; 2 b01: z <=1 b0; 2 b10: z <= 1 b1; s<= 1 b1; endcase end // latch 가사용되지않고합성 always @ (d) begin case (d) 2 b00: z <= 1 b1; s<=1 b0; 2 b01: z <=1 b0; s<=1 b0; 2 b10: z <= 1 b1; s<= 1 b1; defaults: z <= 1 b0; s<=1 b0; endcase end -70-
Verilog Coding Guideline for Synthesis Combinational feedback 이발생하지않도록하라 BAD SEQ COMB SEQ COMB COMB GOOD SEQ COMB COMB SEQ COMB -71-
Verilog Coding Guideline for Synthesis always @(posedge/negedge) block 에는 non-blocking assignment 를사용하는것이좋다 always @(posedge clk) begin b <= a ; c <= b ; end always @(posedge clk) begin c <= b ; b <= a ; end -72-
Verilog Coding Guideline for Synthesis always @(posedge clk) begin b = a ; c = b ; end always @(posedge clk) begin c = b ; b = a ; end -73-
Verilog Coding Guideline for Synthesis 이상적인 clock 기술구조 하나의 clock source 사용 Register 에서의출력 CLK -74-
Clock 을위한 Verilog Coding Guideline 피해야할 clock 기술구조 혼용된 clock edge 사용 Si D Q D Q Si CLK 이경우는 negative-edge 와 positive-edge 플립플롭이분리되는것이좋다 CLK -75-
Clock 을위한 Verilog Coding Guideline 피해야할 clock 기술구조 Gated clocks Skew 문제 Glitch 문제 Scan chain 을엮을수없는문제 U1 U2 Q CLK -76-
FSM 기술을위한 Verilog Coding Guideline Combinational port 와 sequential part 를분리 2-process FSM 기술, 3-process FSM 기술 State 변수를기술하기위해 parameter 사용 Current State Register (sequential) Next State Logic (combinational) clock Asynchronous reset Inputs Output Logic (combinational) Outputs <3-process FSM> -77-
FSM 기술을위한 Verilog Coding Guideline module FSM_S3(Clock, Reset, X, Y); input Clock, Reset, X; output [2:0] Y; reg [2:0] Y; reg [1:0] CS, NS; parameter [1:0] ST0 = 0, ST1 = 1, ST2 = 2, ST3 = 3; always @(X or CS) begin : COMB NS = ST0; case (CS) ST0 : begin NS = ST1; end ST1 : begin if (X) NS = ST3; else NS = ST2; end Next State Logic (combinational) -78-
FSM 기술을위한 Verilog Coding Guideline ST2 : begin NS = ST3; end ST3 : begin NS = ST0; end endcase end // end process COMB always @(posedge Clock or posedge Reset) begin : SEQ if (Reset) CS <= ST0; else CS <= NS; end Next State Logic (combinational) Current State Register (sequential) -79-
FSM 기술을위한 Verilog Coding Guideline always @(CS) begin : OUT case (CS) ST0 : Y = 1; ST1 : Y = 2; ST2 : Y = 3; ST3 : Y = 4; default : Y = 1; endcase end endmodule Output Logic (combinational) -80-