THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE. 2015 Jul.; 26(7), 636 645. http://dx.doi.org/10.5515/kjkiees.2015.26.7.636 ISSN 1226-3133 (Print) ISSN 2288-226X (Online) PCB EMI EMI Problem and Solutions of Unusual Harmonics in Low-Speed PCB 김찬수 이해영 Chan-Su Kim Hai-Young Lee* 요약,. 5 40 (db/decade) 5. PCB 10.,.. Abstract In this paper, unusual harmonics noise problem of digital electronic products in mass production was introduced and a practical solution was proposed. Generally, 5th or higher harmonics noise level has been ignored in circuit designs because over 5th harmonics noise decreases by 40 (db/decade). Through some measurements, it is confirmed that over 10th harmonics noise can propagate and radiate in case of a certain PCB or housing conditions. We propose a capacitively loaded micro-strip low pass filter for commercial products having spatial design constraints and measured the effectiveness. The proposed structure can solve both of the continual increment of harmonics noise level and the spatial design constraint of commercial products. We expect the proposed method be effectively used for various digital electronic products. Key words: EMC(Electromagnetic Compatibility), EMI(Electromagnetic Interference), LDWS(Lane Departure Warning System), Harmonics, GHz(Gigahertz). 서론,. EMC [1] [3],. LDWS(Lane Departure Warning System, ) ( ) (Hyundai Mobis Co., Ltd.), IT * (Department of Electrical and Computer Engineering, Ajou University) Manuscript received March 20, 2015 ; June 12, 2015 ; Accepted June 18, 2015. (ID No. 20150320-022) Corresponding Author: Hai-Young Lee (e-mail: hylee@ajou.ac.kr) 636 c Copyright The Korean Institute of Electromagnetic Engineering and Science. All Rights Reserved.
PCB EMI,. LDWS..,. PCB.. LDWS,, Windshield. 1 LDWS,. PCB., (rise-time),, 5 40 (db/decade),. PCB 10, EMI PCB. Tool, EMI., Antenna. Source,,., EMI.. 제품구조및사전해석결과 2-1 LDWS 제품구조 2 LDWS Block Diagram SDRAM Clock Pixel Clock. DDR- 3, DDR4 800 MHz, 130.5 MHz SDRAM. SDRAM Clock, 52 mm /20 SDRAM [4]. 3 LDWS Artwork Data, 6 Layer. 1, 3, 4, 6 Layer Signal, 2 Layer Ground, 5 Layer Power, Ground Layer Power Layer Return Current Plane. 2-2 PCB보드 PI 사전해석결과 PI(Power Integrity) LDWS PCB PI. 4 An- 그림 1. LDWS Fig. 1. LDWS figures and location in a vehicle. 그림 2. LDWS Fig. 2. Block diagram of LDWS. 637
THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE. vol. 26, no. 7, Jul. 2015. SI(Signal Integrity) LDWS PCB SI. 5 Ansys SIWAVE SDRAM SI., SI Setup time Hold time, SD- RAM Return Current Plane (Slot) SI 그림 3. LDWS Artwork data Fig. 3. Artwork data of LDWS. sys SIWAVE [5]. PCB PCB Decoupling Capacitor, Capacitor 4 Target. Target 100 MHz (1) Target [6] [10], 100 MHz (a) 2.5 GHz 300 Ω. 2-3 SDRAM SI 사전해석결과 (1) (b) 그림 4. LDWS PI Fig. 4. The PI simulation data of LDWS. (c) 그림 5. LDWS SI Fig. 5. The SI simulation data of LDWS. 638
PCB EMI [11].. EMII 측정결과및분석 3-1 EMI 실측정결과 6 LDWS EMI,,. EMI CISPR SPEC,,. 6 130.5 MHz SDRAM Clock. 30 960 MHz SDRAM Clock 130.5 MHz,,,. 130.5 MHz, 1.8 GHz. 1 SDRAM Clock. 1, SDRAM Clock 130.5 MHz. 7 - [12],[13], (Rise-time),, GHz,. (a) 30 200 MHz (b) 200 960 MHz SDRAM Clock (rise-time) 1 ns Knee 318 MHz 40 db/decade, 1.8 GHz. 2-2 2-3, TOOL, EMI,. 3-2 EMI 노이즈원인분석 GHz EMI (c) 1.45 2 GHz 그림 6. LDWS EMI Fig. 6. The first EMI measurements of LDWS. 639
THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE. vol. 26, no. 7, Jul. 2015. 표 1. SDRAM clock EMI Table 1. EMI measurements of SDRAM clock harmonics. Num EMI Peak level Frequency Harmonic frequency 1 15.0 130.5 1 OK 2-261 2 OK 3 15.1 391.5 3 OK 4 14 522 4 OK 5 13 652.5 5 OK 6 9.5 783 6 OK 7 15 913.5 7 OK 8-1,044 8-9 - 1,174.5 9-10 - 1,305 10-11 - 1,435.5 11-12 28 1,566 12 OK 13 16 1,696.5 13 OK 14 44.5 1,827 14 NG 15 42 1,957.5 15 NG 16 32 2,088 16 OK 17-2,218.5 17-18 14 2,349 18 OK 19 34.5 2,479.5 19 OK, 0.25 ( /4) /4 radiation. 8, /4 [14]. SDRAM Clock 52 mm, 4.5 PCB, /4 52 mm 679.9 MHz, 3 /4 52 mm 2,039 MHz, 5 /4 52 mm 3,397 MHz. EMI 1,827 MHz 1,957.5 MHz, /4 radiation., 9 SDRAM Clock. /4 radiation EMI., PCB. 4 그림 8. - Fig. 8. Radiation profile from signal line. 그림 7. - Fig. 7. Harmonics frequency-amplitude graph., [14]. 그림 9. SDRAM clock Fig. 9. Signal transmission response of SDRAM clock. 640
PCB EMI 그림 10. SDRAM clock Fig. 10. Impedance simulation data of SDRAM clock. Target, SDRAM Clock 10, 1.827 GHz, 1.9575 GHz 48.31 Ω, 31.12 Ω Peak. Peak PCB, EMI. GHz PCB, [15]. PCB Embedded Capacitance GHz, [16],[17]., Connector Hole Gap Slit. LDWS 2 mm.,, (2) Skin Depth Absorption Loss GHz., 1 GHz Skin Depth 2.5um, GHz EMI., 3D TOOL CST [18] 11. 11, SE(Shielding Effectiveness) [3]. 그림 11. LDWS shielding effectiveness Fig. 11. Shielding effectiveness of LDWS housing. 11, 1.7 GHz SE, 1.827 GHz, 1.9575 GHz SE0.02 db, 0.48 db,. m 3, EMI, PCB Peak. EMI Source, Route, Antenna 3 [19]. Antenna, PCB, PCB,. Source Route.. 문제해결방안및적용결과 4-1 문제해결방안제안 Source Route, Micro-strip (2) 641
THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE. vol. 26, no. 7, Jul. 2015. [20]. Chebyshev Response Passband Ripple 1 db, Cutoff Frequency 1 GHz 3, 12 [21]. Source Driver Output Impedance 50 Ω, 13 33 Ω Series Resistor SDRAM Clock. (3) PCB Micro- strip Width [22]. PCB FR4, H=0.19 mm, T=0.018 mm, =4.5. Effective Dielectric Constant, Guided Wavelength (4), (5) [20]. u=w/h W Micro-strip Width., (6) Micro-strip Length. 2, 14., PCB. High Impedance, 15. 16, 1.827 GHz, 1.9575 GHz 24.31 db, 25.39 db. 1.0 0.5 mm. ln 그림 12. 3 Chebyshev Fig. 12. 3rd Chebyshev lowpass filter. (3) 그림 13. Series resistor SDRAM clock Fig. 13. SDRAM clock impedance matching by series resistor. ln ln (4) GHz mm (5) sin (6a) 표 2. Table 2. Stepped impedance lowpass micro-strip filter design parameter. Characteristic impedance Guided wavelength Effective dielectric constant Micro-strip width Micro-strip length Low Z (Capacitor) Z Hign Z (Inductor) Ω Ω Ω mm - mm Capacitor - - 642
저속 PCB에서 이상 고조파의 EMI 문제 및 해결 방안 계단형 임피던스 저역통과 여파기 그림 14. Fig. 14. Stepped impedance lowpass micro-strip filter. 수정된 형상 그림 17. LDWS PCB Fig. 17. Improved LDWS PCB picture. 커패시터를 주기적으로 배치한 저역통과 여파기 그림 15. Fig. 15. Capacitively loaded micro-strip lowpass filter. 신호선의 주파수 전달 특성 그림 16. SDRAM clock Fig. 16. Signal transmission response of SDRAM clock. sin 의 최종 (6b) 4-2 해결 방안 적용 결과 그림 17은 본 방안이 적용된 PCB 실물 형상이고, 그림 18에 최종 EMI 결과를 나타내었다. EMI 측정결과를 보 면, 문제가 되었던 GHz 대역의 SDRAM Clock 신호의 고 조파가 전반적으로 감소하였음을 확인할 수 있다. Ⅴ. 결 측정 결과 그림 18. LDWS EMI Fig. 18. The final EMI measurements of LDWS. 론 본 논문에서는 비 고속 시스템에 해당하는 LDWS 제 품에서 GHz 대역의 이상 고조파로 인한 EMC 문제를 분 석하고, 해결 방안을 도출하였다. 일반적으로 GHz 대역 의 EMI 문제는 높은 주파수를 사용하는 고속 디지털 시 스템에서 주로 발생한다. 하지만 비록 제품이 상대적으로 낮은 주파수를 사용하고, 고속 시스템에 속하지 않더라도 제품의 형상과 구조에 따라 이상 고조파로 인한 EMI 문 제가 발생할 가능성이 있다. 현재 Antenna를 개선하는 방 안은 본 제품의 공간적 설계 제한 조건으로 인해 적용이 불가능하여 Source와 Route를 개선하는 방향으로 진행하 였다. 문제가 되는 Source 신호선에 커패시터를 주기적으 로 배치한 저역통과 여파기를 적용하였으며, EMI 문제 대역이 개선된 것을 확인하였다. 제안된 방법은 실 산업 현 장에서 자주 발생하는 공간적 설계 제한 조건이 있는 경 643
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PCB EMI 2008 2 : ( ) 2012 9 2015 7 : IT 2008 : ( ) [ 주관심분야 ] EMC, PCB Design & Analysis (SI, PI, EMI) 1980 2 : ( ) 1982 2 : ( ) 1982 1986 : 1989 12 : The University of Texas at Austin ( ) 1990 1992 : LG 1 1992 : 2010 : 2011 : [ 주관심분야 ] System in Package, /,, SI/EMI 645