THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE. 2019 Sep.; 30(9), 712 717. http://dx.doi.org/10.5515/kjkiees.2019.30.9.712 ISSN 1226-3133 (Print) ISSN 2288-226X (Online) MOS W-Band W-Band High-Gain Low-Noise Amplifier Design Using MOS Capacitor Neutralization Technique 박하정 김준성 박재현 김병성 Ha-Jung Park Jun-Seong Kim Jae-Hyun Park Byung-Sung Kim 요약 65-nm CMOS 4 80 GHz. MOS C gd. MOS well,. 83.2 GHz 28.43 db, 6.89 db. 1.2 V 50 mw DC. Abstract This study presents a four-stage common-source(cs) differential low-noise amplifiers at the 80 GHz band developed by using the 65-nm complementary metal oxide semiconductor(cmos) process. To improve the gain of CS structures in the millimeter wave band, the C gd capacitance between the gate and the drain is neutralized by using a cross-coupled MOS capacitor. By varying the Well bias configuration of MOS capacitor, the characteristics of the amplifier is observed, and the optimal bias condition is derived to achieve maximum gain and high stability. The implemented circuit showed a maximum gain of 28.43 db at 83.2 GHz and a simulated noise figure of 6.89 db. The low noise amplifier consumes 50 mw direct current(dc) power from a 1.2 V supply voltage. Key words: Low Noise Amplifier, CMOS, W-Band. 서론., [1]. 2019 (NO. 2002712). (College of Information & Communication Engineering, Sungkyunkwan University) Manuscript received September 5, 2019 ; Revised September 20, 2019 ; Accepted September 23, 2019. (ID No. 20190905-081) Corresponding Author: Byung-Sung Kim (e-mail: bskimice@skku.edu) 712 c Copyright The Korean Institute of Electromagnetic Engineering and Science. All Rights Reserved.
MOS W-Band C gd [2]. W-band FET MOS C gd. MOS MIM/ MOM well Q-factor., MOS,,. 1 poly 9 metal 65nm CMOS RF.. 회로설계 MOSFET,, C gs Q-factor.,. 150 μa/μm FET 24 μm [3]. FET, 1 1 μm. C gd, CMOS MOM, MIM MOSFET MOS. MIM C gd. MOM, FET C gd MOS 그림 1. 80 GHz 24 μm FET Fig. 1. Minimum noise figure of single common source FET with 24 μm gate width along the unit gate finger width at 80 GHz. FET C gd. MOSFET CMOS triple-well RF, well,. 2 MOS well. 2(a) P-well 0 V, N-well 1.2 V. 2(b) P-well, 2(c) P-well. 2(d) 2(f) P-well 2(a) 2(c), N-well 1.2 V. 5.59 kω. 3 MOS Q- factor, P-Well, N-well Vdd (c) Q-factor, P-well N-well (d) Q- 713
THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE. vol. 30, no. 9, Sep. 2019. R S, r g. 24 μm MOSFET C gd 5.63 ff, (1) C C C gd. 4 5 그림 2. Triple well MOSFET Fig. 2. Bias structure of triple well MOSFET. 그림 4. MOS Fig. 4. Maximum available gain due to the change of MOS capacitor gate width. 그림 3. MOS well Q-factor Fig. 3. Q-factor depending on the well bias structures of MOS capacitor. factor. (d). Cc (1) [4]. (1) 그림 5. MOS Fig. 5. Stability factor along the change of MOS capacitor gate width. 714
MOS W-Band. 1 μm MOS 6 μm 16 μm. 80 GHz MOS 14 μm 5. 5 MOS 12 μm. MOS 6.98 ff. 6 4,. 50 Ω 1:2., MOSFET.,, C 1 C 2 [5].. 79 GHz, 83.2 GHz 28.43 db 그림 7. CMOS Fig. 7. Die photo of the fabricated CMOS low noise amplifier.. 측정및시뮬레이션결과 7 65-nm CMOS. S- 110 GHz Anritsu MS4647A -. 8 Corner analysis, 9 4 그림 8. Fig. 8. Simulated noise figure depending on the process coner. 그림 6. Fig. 6. Schematic of low noise amplifier. 715
THE JOURNAL OF KOREAN INSTITUTE OF ELECTROMAGNETIC ENGINEERING AND SCIENCE. vol. 30, no. 9, Sep. 2019. 표 1. Table 1. Performance comparison with prior arts. Ref. Process Type Peak gain (db) Peak gain frequency (GHz) 3-dB BW (GHz) Noise figure db) P1dB (dbm) [1] 65-nm CMOS 6-stage single-ended cascode 22 84 20 6.8 10.4-21 [2] 65-nm CMOS 3-stage differential CS 23 63 6 5.3* 3* 32 This work 65-nm CMOS 4-stage differential CS 28.43 83.2 2.6 6.89 7.64* 21* 50 * Simulated value. PDC (mw) 1.2 V 50 mw DC. References 그림 9. S- Fig. 9. Measured and simulated S-parameter result..,. 3 db 81.5 GHz 84.1 GHz. 1.. 결론 65-nm CMOS MOS, MOS. 83.2 GHz Peak gain 28.43 db, 3 db 2.6 GHz. [1] C. J. Lee, H. J. Lee, J. G. Lee, T. H. Jang, and C. S. Park, "A W-band CMOS low power wideband low noise amplifier with 22 db gain and 3 db bandwidth of 20 GHz," in 2015 Asia-Pacific Microwave Conference(APMC), Nanjing, 2015, pp. 1-3. [2] D. W. Kim, H. W. Seo, J. S. Kim, and B. S. Kim, "Design of V-band differential low noise amplifier using 65-nm CMOS," The Journal of Korean Institute of Electromagnetic Engineering and Science, vol. 28, no. 10, 832-835, Oct. 2017. [3] T. Yao, M. Gordon, K. Yau, M. T. Yang, and S. P. Voinigescu, "60-GHz PA and LNA in 90-nm RF-CMOS," in IEEE Radio Frequency Integrated Circuits(RFIC) Symposium, San Francisco, CA, Jun. 2006, p. 4. [4] W. L. Chan, J. R. Long, "58 65 GHz neutralized CMOS power amplifier with PAE above 10% at I V supply," IEEE Journal of Solid-State Circuits, vol. 45, no. 3, pp. 554-564, Mar. 2010. [5] S. Aloui, E. Kerherve, R. Plana, and D. Belot, "RF-pad, transmission lines and balun optimization for 60 GHz CMOS power amplifier," in 2010 IEEE Radio Frequency Integrated Circuits Symposium, Anaheim, CA, May 2010, pp. 211-214. 716
MOS W-Band [ / ] https://orcid.org/0000-0001-7375-766x 2017 2 : ( ) 2018 3 : [ 주관심분야 ] [ / ] https://orcid.org/0000-0002-8303-6273 2016 2 : ( ) 20116 3 : [ 주관심분야 ] [ / ] https://orcid.org/0000-0003-0036-4034 2014 2 : ( ) 2014 3 : [ 주관심분야 ] [ / ] https://orcid.org/0000-0003-3084-6499 1989 2 : ( ) 1991 2 : ( ) 1997 2 : ( ) 1997 3 : [ 주관심분야 ] RFIC, RF 717