삼성기초VHDL이론.PDF

VHDL System ASIC Design Lab. : jcho@asiclab.inchon.ac.kr. Chap. 1 Chap. 2 Chap. 3 Digital SystemVHDL Modeling Chap. 4 Test Bench Model 1

Chap. 1 ASIC (1) 1-Chip Format Source encode Encrypt Channel encode Multi plex Modulate Frequency spread Multiple access X M T Synchronization Format Source decode Decrypt Channel decodel Demodulate Demultiplex Frequency despread Multiple access R C V VHDLASIC NO.-4 2

ASIC (2) Wireless Audiovisual Terminal Camera LCD senser A/D preprocessing D/A H.263/MPEG- 4 Encoder H.263/MPEG- 4 Decoder display processing Audio Out Audio In D/A A/D G.723.1 H.223/H.245/ Link/Network Protocol control user interface OFDM modem transceiver H.324 CODEC : Video Audio Data Digital Communication Module : Data, Error Micro-Controller : 16-Bit ProcessorCamera, LCD Interface Chips Analog Front End Module : A/D, D/A VHDLASIC NO.-5 System Level Behavioral Level RTL Level Logic Level Circuit Level Layout Level Level Graphical Representation System Partioning,Pipelining Behavioral Scheduling,Allocation RTL State Machines,Logic and RTL Multi-level, 2-level Optimization Port1 Port2 Port3 Port1 Port2 Port3 Mux1 R1 R2 R3 ALU Output + + - < Output Mux2 + ADDER HDL, Graphical specifications HDL, Bubble diagrams Logic Technology mapping/ translation a b c d e f Logic equations, HDL, Gates Implementation Place and Route Layout CIF/GDSII Graphic Diagram (HDL : Hardware Description Language) VHDLASIC NO.-6 3

2 FA D D FA D D ASIC...???...!! 1?? Q( x)? e x 2? y /2 dy architecture rtl of... signal s0, s1, s2 : std_logi process (clock,reset)... Behavioral Register Transfer Level VHDL, FPGA VHDL Physical ASIC System Board ASIC VHDLASIC NO.-7 Digital ASIC Digital ASIC Hierarchical cells Generators : Memory PLA Sparse logic Gate matrix Gate arrays Sea of gates Compacted arrays Anti-fuse based Memory-based VHDLASIC NO.-8 4

Digital ASIC ASIC Custom Cell-based Prediffused Prewired Density Performance Very High Very High High High High High Medium - Low Medium - Low Flexibility Very High High Medium Low Design time Manufacturing time Very Long Medium Short Medium Short Short Very Short Very Short Cost - low volume Very High High High Low Cost - high volume Low Low Low High VHDLASIC NO.-9 Boding Diagram Standard-Cell Design VHDLASIC NO.-10 5

Sea-of-Gate Design Boding Diagram : FLEX Decoder Chip VHDLASIC NO.-11-1 : System(Algorithm) Level C, MATLAB, SPW COSSAP System Level library sub-block system (, BER ) hardwarecomplexityperformance data-busbit size System Chip COSSAP DS/SS Base Band MODEM Modeling VHDLASIC NO.-12 6

-2 : Behavioral Compiler System Level Data Path Module Behavioral Compiler Option RTL RTL RTL RTL RTL RTL RTL Behavioral Source Behavioral Behavioral Synthesis Synthesis RTL RTL RTL RTL RTL RTL Design Compiler Netlist VHDLASIC NO.-13-2 : Behavioral Compiler Design Flow Behavioral Compiler Design Flow Operator to State Binding Variable to Register Binding Function Unit Sharing Control Logic FSM Specification Behavioral Simulation Implementation Behavioral Compiler Optional RTL Simulation HDL Synthesis & Test Gate_Level Simulation Gate_Level Optimization Silicon Vendor Place & Route VHDLASIC NO.-14 7

-2 : Behavioral Compiler RTL.????? Data Path Module RTL Controller Module RTL FSM Table Model VHDLASIC NO.-15-3 : Register-Transfer Level RTL Target Architecture D Q Selector D Q Register RF Memory D Q Nextstate logic state register Output logic Register VHDLASIC NO.-16 8

-3 : Register-Transfer Level Synthesis VHDL Hardware Logic state M A R Target Architecture M R : Basic Gates, Modular Units (mux, decoder, arithmetic units) : F/Fs, Registers, Counters, FSM(Finite State Machine) : ROM, RAM Bus : 3-Buffer VHDLASIC NO.-17-3 : Design Compiler Design Flow3 Design Flow RTL VHDL Simulation Gate Level,,Power Design Library : FPGA, ASIC Component Delay Timing Simulation Physical Design EDIF FPGA Physical Design FPGA Tool Compile Device Option Layout Data Simulation Target Board Emulation ASIC ASIC Physical Design Design HouseEDIF Wire Delay Simulation Sign-off ASIC Test Board, VHDLASIC NO.-18 9

HDL VHDL HDL VHDL :, synthesis sub-set VHDLmodeling guide. Verilog : VHDL, gate simulation design kitgolden simulator VHDL 1983 1984 1985 10 11 12 V1.0 V2.0 2 4 5 6 7 8 12 V3.0 Orono V3.5 Workshop Critical Design Review V4.0 V5.0 V6.0 V7.0 1 8 V7.2 1986 1987 2 6 10 12 1 5 Preliminary Draft IEEE Standard Standard Ballot 12 Final IEEE Standard 1992 VHDL '92 Value 1987 STD-1076 Version STD library 2-Value, { 0, 1 } 1990 Value IEEE library 9-value, { U, X, 0, 1, Z, W, L, H, - } VHDLASIC NO.-19 Design Design Entity Hardware : NOT gate, ALU, 8051 Micro-Controller, DSP Board, Digital TV System VHDL Design Entity : entity declaration design unit : architecture body design unit entity unitarchitecture unit : configuration design unit VHDLASIC NO.-20 10

Design Entity Subprogram,, Component VHDL Interface Package Declaration Design Unit Sub-Program Algorithm Package Body Design Unit VHDLASIC NO.-21 VHDL 5 Design Unit Hardware 3 Unit entity declaration unit interface architecture body unit configuration declaration unit entity unitarchitecture unit simulation Software 2 Unit package declaration unit design entity package body unit subprogram 2 Unit entity unit 9-Value Package Visibility I/O architecture unit : Behavioral View Model : Structural View Model VHDLASIC NO.-22 11

System System IP Macro Component Critical Path Block Block 4,000~5,000 GateOptimization (n, k, d) Reed-Solomon Decoder r(x) s 1 r? (x) s 2 x ( ) s 2t x ( ) Design Tree Model VHDLASIC NO.-23 VHDL Model (1) Design TreeFully VHDL Design NodeEntity Unit + Architecture Unit VHDLASIC NO.-24 12

VHDL Model (2) Design Tree1-Level VHDL Root Design Node Entity Unit + Architecture Unit Root Design NodeConcurrent VHDL : (B3 BlockCritical Path ) B3 Behavioral View Model VHDLASIC NO.-25 VHDL System : SimulationDocumentation Chip : Simulation, Synthesis Documentation Chip IP(Intellectual Property) Model Re-Use Synthesis VHDL Modeling VHDLASIC NO.-26 13

Full Adder 2 VHDL VHDLASIC NO.-27 SimulationSynthesis (1) Simulation Waveform 1-Level VHDL LSI-10K Library : 3.0 VHDLASIC NO.-28 14

SimulationSynthesis (2) VHDL Structural View Node Behavioral View Node (HA: Half Adder, OR2: 2-input OR) LSI-10K Library : 1.5*2 + 0.5 = 3.5 Optimization VHDLASIC NO.-29 VHDL library IEEE; use IEEE.std_logic_1164.all; entity EX is port (A, B, C, D : in std_logic; Y1, Y2 : out std_logic); end EX; architecture RTL of EX is process (A, B, C, D) variable TMP: std_logic_vector(3 downto 0); TMP := A & B & C & D; case TMP is when "0000" => Y1<='1'; Y2<='0'; when "0001" => Y1<='1'; Y2<='0'; when "0010" => Y1<='1'; Y2<='0'; when "0011" => Y1<='1'; Y2<= 0'; when "0100" => Y1<='1'; Y2<='0'; when "0101" => Y1<='1'; Y2<='0'; when "0110" => Y1<='1'; Y2<='0'; when "0111" => Y1<='1'; Y2<='0'; when "1000" => Y1<='1'; Y2<='0'; when "1001" => Y1<='0'; Y2<='1'; when "1010" => Y1<='0'; Y2<='1'; when "1011" => Y1<='1'; Y2<='1'; when "1100" => Y1<='1'; Y2<= 0'; when "1101" => Y1<='1'; Y2<='0'; when "1110" => Y1<='1'; Y2<='0'; when others => Y1<='1'; Y2<='0'; end case; end RTL; VHDLASIC NO.-30 15

Target Library : LSI_10K Area Area Design Constraint 5-cells(Area : 7.0), Critical Path(2.38ns) Timing Design Constraint 8-cells(Area : 15.0), Critical Path(0.84ns) VHDLASIC NO.-31 FPGA Fast Prototyping FPGA Board Reed-Solomon Decoder VHDLASIC NO.-32 16

ASIC Reed-Solomon Decoder Bonding Diagram VHDLASIC NO.-33 Chap. 2 VHDL 17

Character Set, Lexical Elements Identifier Character Sets Upper-Case Letters Lower-Case Letters Special Characters Space Character Format Effectors Lexical Elements Delimiter Single Character Compound Character Identifier Reserved Identifier Identifier Literal VHDL-87 Reserved Word abs access after alias all and architecture array assert attribute block body buffer bus case component configuration constant disconnect downto else elsif end entity exit file for function generate generic guarded if in inout is label library linkage loop map mod nand new next nor not null of on open or others out package port procedure process range record register rem report return select severity signal subtype then to transport type units until use variable wait when while with xor VHDLASIC NO.-35 VHDL-93 Reserved Word Identifier VHDL-93 Reserved Word group impure inertial literal postponed pure reject rol ror shared sla sll sra srl unaffected xnor Identifier Alphabet. Alphabet. Alphabet, _., _. Alphabet. COUNT cout c_out AB2_5C VHSIC X1 FFT Decoder A_B_C xyz h333 STORE_NEXT_ITEM :. 2CA My-name H$B LOOP Decode_ N#3 VHDLASIC NO.-36 18

VHDL Literal Literal Tree VHDLASIC NO.-37 Class Syntax Data_Class Object_Identifier : Data_Type [ := initial value ] ; signal A: std_logic; constant B: std_logic_vector(3 downto 0) := 0001 ; Data Class Signal Simulation Dynamic Data H/W Variable Simulation Dynamic Data H/W File Simulation Vector File Constant Static Data H/W object Constant H/W entity,architecture,process package,function,procedure block Signal entity, architecture, package, block Variable process, function, procedure VHDLASIC NO.-38 19

Data Data : Data Type Group, Package Data Type VHDL Data Type : ++ TypeSynthesis Tool Scalar Data Types Enumeration Type, Numeric type, Physical Type ++ Composite Data Types Array Type, Record Type Access Data Type ++ File Data Type ++ Type package standard package 1987 std_logic_1164 1993 Standard Package package STANDARD is type BOOLEAN is (FALSE, TRUE); type BIT is ( 0, 1 ); type CHARACTER is ( ); type SEVERITY_LEVEL is (NOTE, WARNING, ERROR, FAILURE); type INTEGER is implementation_defined ; type REAL is implementation_defined ; type TIME is range implementation_defined ; units fs: ps = 1000 fs; end units; subtype DELAY_LENGTH is TIME; function NOW return time; subtype NATURAL is integer range 0 to integer high; subtype POSITIVE is integer range 1 to integer high; type STRING is array(positive range <>) of character; type BIT_VECTOR is array(natural range <>) of bit; end STANDARD; VHDLASIC NO.-39 1993 PackageType Std_logic_1164 Package package STD_LOGIC_1164 is type STD_ULOGIC is ( U, --Uninitialized X, --Forcing Unknown 0, --Forcing 0 1, --Forcing 1 Z, --High Impedance W, --Weak Unknown L, --Weak 0 H, --Weak 1 - --Don t care ); type STD_ULOGIC_VECTOR is array(natural range <>) of std_ulogic; function resolved(s: std_ulogic _vector) return std_ulogic; subtype STD_ULOGIC is resolved std_ulogic; type STD_LOGIC_VECTOR is array(natural range <>) of std_logic; subtype X01 is resolved std_ulogic range X to 1 ; subtype X01Z is resolved std_ulogic range X to Z ; subtype UX01 is resolved std_ulogic range U to 1 ; subtype UX01Z is resolved std_ulogic range U to Z ; function and (l: std_logic; r: std_logic) return std_logic; ; function and (l: std_logic_vector; r: std_logic_vector) return std_logic_vector; ; function Is_X (s: std_ulogic) return boolean; end STD_LOGIC_1164; VHDLASIC NO.-40 20

Data Type (1) Integer Data Type Enumeration Data Type type COUNTVALUE is range 0 to 15; FSM type TWENTIES is range 20 to 29; Synthesis tool bit type STATE_NAME is (A, B, C, D); 0 2 (0 ) element 1 Integer 0 ~ 15 type STATE is (S0, S1, S2); signal C_STATE, N_STATE : STATE; VHDLASIC NO.-41 Data Type (2) 8*5 Bit2 Memory : -1 8*5 Bit2 Memory : -2 Word Addressing Mode Bit Addressing Mode Memory type MEMORY4 is -1 array(0 to 7, 4 downto 0) of std_logic; subtype WORD1 is std_logic_vector(4 downto 0); Bit-addressing Mode 2 Memory type MEMORY1 is array(0 to 7) of WORD; -2 type WORD2 is array(4 downto 0) of std_logic; type MEMORY2 is array(0 to 7) of WORD; -3 type MEMORY3 is array(0 to 7) of std_logic_vector(4 downto 0); Composite Record Data Type type FloatPointType is record SIGN : std_logic; EXPONENT : unsigned(0 to 6); FRACTION : unsigned(24 downto 1); end record; Composite Array Data Type type unsigned is array(natural range <>) of std_logic; type unsigned_word is array(natural range 7 downto 0) of std_logic; VHDLASIC NO.-42 21

Entity Declaration Unit Entity Unit Syntax entity ENTITY_NAME is [ generic ( LIST_OF_GENERICS_AND_THEIR_TYPES ) ; ] [ port ( LIST_OF_PORTS_AND_THEIR_MODE ) ; ] [ DECLARATIONS ] [ { ENTITY_STATEMENT } ] end [ ENTITY_NAME ] ; VHDLASIC NO.-43 Out ModeBuffer Mode Out ModeBuffer Mode out mode buffer mode Buffer Mode Buffer Mode, Buffer Mode. Buffer Mode Buffer ModeOut Mode VHDLASIC NO.-44 22

Entity Declaration Unit D Flip-FlopEntity Unit Generic DecoderEntity Unit D Q SIZEIN A GENERIC_ DECODER SIZEOUT B CLK CLR Q -- 9-value Package Visibility library IEEE; use IEEE.std_logic_1164.ALL; -- Pin Name, Mode, Data Type entity DFF is port (D : in std_logic; CLK : in std_logic; CLR : in std_logic; -- D, CLK, CLR : in std_logic; Q, QBAR : out std_logic); end DFF; EN library IEEE; use IEEE.std_logic_1164.ALL; entity GENERIC_DECODER is -- Static Information generic (SIZEIN, SIZEOUT : integer); -- Dynamic Pin Data port (EN: in std_logic; A: in std_logic_vector(sizein-1 downto 0); B : out std_logic_vector(sizeout-1 downto 0)); end GENERIC_DECODER; VHDLASIC NO.-45 Architecture Body Unit Syntax architecture A_NAME of E_NAME is [ DECLARATIONS ] {CONCURRENT_STATEMENT} end [A_NAME] ; Behavioral view Q= 1 x= 1, YZ 1 Data-flow view Boolean state equation Structural view and gateor gate and or gatebehavioral View Data-flow View Mixed view Behavioral View Data-flow View Structural View. VHDLASIC NO.-46 23

Architecture Body Unit Entity design unit library IEEE; use IEEE.std_logic_1164.all; entity EXAMPLE is port (X, Y, Z: in std_logic; Q: out std_logic); end EXAMPLE; Behavioral View architecture RTL1 of EXAMPLE is process (X, Y, Z) if X= 1 then Q <= 1 ; elsif (Y= 1 and Z= 1 ) then Q <= 1 ; else Q <= 0 ; end RTL1; Data-flow View architecture RTL2 of EXAMPLE is Q <= X or (Y AND Z); end RTL2; Structural View architecture RTL3 of EXAMPLE is component OR2 port (I1, I2: in std_logic; O1: out std_logic); end component; component AND2 port (I1, I2: in std_logic; O1: out std_logic); end component; for U0: OR2 use entity work.or2(rtl); for U1: AND2 use entity work.and2(rtl); signal S1: std_logic; U0: OR2 port map (X, S1, Q); U1: AND2 port map (Y, Z, S1); end RTL3; VHDLASIC NO.-47 Configuration Entity Unit Architecture Unit2 Simulation Architecture Unit Component Object Link Component Object Entity Unit EXAMPLE 3 Architecture Unit Simulation Entity Unit Architecture Unit Architecture Unit Configuration Specification Configuration Unit Configuration Declaration Unit VHDLASIC NO.-48 24

Configuration Specification : Architecture UnitStructural View component compile library entity unit architecture unit component binding 1-Level architecture unit Syntax for INSTANTIATION_LIST : COMPONENT_NAME [ use entity ENTITY_NAME { ( ARCHITECTURE_NAME ) } ] [ generic map ( GENERIC_ASSOCIATION_LIST ) ] [ port map ( PORT_ASSOCIATION_LIST ) ] ; for U0 : NAND1, NAND2 use entity work.nand_gate(rtl); for U1 : INV1, INV2, INV3 use entity work.inverter; for ALL : NOR use configuration LIB1.NOR_C; NOR componentcompilelibrary LIB1 for others : NOT use entity work.not(rtl); VHDLASIC NO.-49 Configuration Declaration Unit : Behavioral View : configuration TOP of XDOWN is for BEHAVIORAL end for; end TOP; Structural View : design entity configuration configuration FA_C of FA_E is for FA_A for u1,u2: HA use entity WORK.HA_E(HA_A) generic map (3 ns, 2 ns); for HA_A for u1: XOR2 use entity WORK.XOR2_E(XOR2_A) generic map (3 ns); end for; for u2: AND2 use entity WORK.AND2_E(AND2_A) generic map (2 ns); end for; end for; end for; for u3: OR2 use entity WORK.OR2_E(OR2_A) generic map (2 ns); end for; end for; end; Generate configuration declaration unit : generate VHDLASIC NO.-50 25

Source filecompiled file VDHL source filecompile library, compiled file (intermediate format) library WORK library VHDL library WORK IEEE VHDL (VASG) library 2-value STD 9-value IEEE VHDL Analyzer Design units VHDL Analyzer Intermediate format VHDL Design file A design unit is: - entity declaration - architecture body - configuration declaration - package declaration - package body Working library, WORK LIB1 LIB2 IEEE STD Design libraries VHDLASIC NO.-51 Library Library Visibility STD library VHDL library textio IEEE library std_logic_1164 std_logic_arith std_logic_unsigned ASIC vendor library WORK library directory logic gateentity, architecture user library package, entity, architecture VHDL Code Package Unit Visibility packagework library design unit. use WORK.package_name.item_name; packagelib2compile, CodeLIB1 Compile design unit. library LIB2; use LIB2.package_name.item_name; VHDLASIC NO.-52 26

Library Visibility Entity Unit architectureconfiguration unit --library visibility library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.std_logic_unsigned.all; --entity unit entity ADD_SUB is port ( A, B : in std_logic_vector(3 downto 0); SEL : in std_logic; S : out std_logic_vector(3 downto 0); CF, ZF : out std_logic); end ADD_SUB; Package Declaration Unit package body unit library IEEE;use IEEE.std_logic_1164.ALL; use IEEE.std_logic_arith.all; use IEEE.std_logic_signed.all; package PACK_MATCH is function COMP2C ( A: std_logic_vector) return std_logic_vector; function TWO_MUL ( A: std_logic_vector; B: std_logic) return std_logic_vector; end PACK_MATCH; VHDLASIC NO.-53 Structural View Structural View VHDL Component Architecture Unit Component D.B. Wire Architecture Unit Port Map Component Component I/O Port Formal Name: Pin Name component HA port (A, B: in std_logic; C, D: out std_logic); end component; Component Configuration for U0: HA use entity work.ha(rtl); Component 3 Component Instantiation Actual Name: Wire Name PinWire H/W if for generate Component Instantiation PinWire 2 Positional Association Mapping Named Association Mappin WireData Type Signal. VHDLASIC NO.-54 27

Component Instantiation VHDL library IEEE; use IEEE.std_logic_1164.all; entity FA is port (A, B, CIN : in std_logic; SUM, COUT : out std_logic); end FA; -- architecture RTL of FA is component HA port ( A, B : in std_logic; C, S : out std_logic); end component; component OR2 port ( A, B: in std_logic; Y : out std_logic); end component; for U0, U1: HA use entity work.ha(rtl); for U2: OR2 use entity work.or2(rtl); signal S1, S2, S3 : std_logic; --Positional Association Mapping U0 : HA port map (A, B, S1, S2); U1 : HA port map (CIN, S2, S3, SUM); U2 : OR2 port map (S1, S3, COUT); --Named Association Mapping --U0 : HA port map (A=>A, B=>B, -- C=>S1, S=>S2); --U1 : HA port map (A=>CIN, B=>S1, -- C=>S3, S=>SUM); --U2 : OR2 port map (A=>S1, B=>S3, -- Y=>COUT); end RTL; Compile HAOR2 VHDL Component Compile HAOR2FA Component Component Compile VHDLASIC NO.-55 Unconnected Port Unconnected Port Pin Wire Port Unconnected Port Unconnected Port architecture RTL of EX1 is component EX2 port (CLK,PRESET,RESET,D: PRSET in std_logic; D D Q Q Q, QBAR : out std_logic); end component; for U1: EX2 use entity work.dsr(rtl); CLK Qbar signal VCC : std_logic; RESET --VHDL-87 / CLR Unconnected Output Port VCC <= 1 ; Unconnected Input Port VHDL Unconnected Input Port VCC 1 U1 : EX2 port map (D => D, CLK =>CLK, PRESET =>VCC, RESET=>CLR, Q=>Q, QBAR=>open); GND 0 --VHDL-93 Unconnected Output Port Reserved IdentifierOPEN --U1 : EX2 port map (D => D, -- CLK=>CLK, PRESET => 1, -- RESET=>CLR, Q=>Q, -- QBAR=>open); end RTL; VHDLASIC NO.-56 28

Generic Map Command Generic Behavioral entity AND_GATE is generic (TDELAY : time := 10 ns; N : positive := 2); port (A : in std_logic_vector(n-1 downto 0); C : out std_logic); end AND_GATE; architecture RTL of AND_GATE is P0 : process (A) variable INT : std_logic; INT := 1; for I in (A length-1) downto 0 loop if (A(I)= 0 ) then INT := 0 ; end loop; C <= INT after Tdelay; end RTL; Generic Map Structural entity EX is port (D1, D2, D3, D4, D5 : in std_logic; Q1, Q2 : out std_logic); end EX; architecture RTL of EX is component AND_COMP generic (TDELAY : time; N : positive); port (A : in std_logic_vector(n-1 downto 0); C : out std_logic); end component; for all : AND_COMP use entity work.and_gate(rtl); U1: AND_COMP generic map (n=>2, TDELAY=>8 ns) port map (A(0)=>D1, A(1)=>D2, C=>Q1); U2: AND_COMP generic map (n=>3, TDELAY=>12 ns) port map (A(0)=>D3, A(1)=>D4, A(2)=>D5, C=>Q2); end RTL; VHDLASIC NO.-57 For..Generate Structure View 4-Bit Ripple Carry Adder ArchitectureConfiguration Unit ComponentSymbol architecture RTL1 of FA4 is NameFormal Name -- FA Component.. signal TMP : std_logic_vector(4 downto0); Component Instantiation TMP(0) <= 0 ;. G: for I in 0 to 3 generate L : FA port map ( X(I), Y(I), TMP(I), Z(I), TMP(I+1)); end generate; COUT <= TMP(4); end RTL1; -- configuration CONF_FA4 of FA4 is for RTL for G for L: FA use entity work.fa(rtl); end for; end for; end for; end CONF_FA4; Port Map Configuration VHDLASIC NO.-58 29

If For..Generate Structure View 4-Bit Ripple Carry Adder Architecture Unit Component Symbol architecture RTL1 of FA4 is Name. -- FA, HA Component Component -- Instantiation signal T : std_logic_vector(4 downto 1);. G0: for I in 0 to 3 generate G1 : if I=0 generate L0 : HA port map (X(I),Y(I),Z(I),T(I+1)); end generate; G2 : if I>=1 and I<=3 generate L1 : FA port map (X(I),Y(I),T(I),Z(I),T(I+1)); end generate; end generate; COUT <= TMP(4); end RTL1; VHDLASIC NO.-59 Generate Configuration Declaration Unit Configuration Unit configuration CONF_FA4 of FA4 is for RTL1 for G0 for G1 for L0: HA use entity work.ha(rtl); end for; end for; for G2 for L1: FA use entity work.fa(rtl); end for; end for; end for; end for; end CONF_FA4; Component component configuration architecture RTL of TB_FA4 is signal X, Y: std_logic_vector(n-1 downto 0); signal Z: std_logic_vector(n-1 downto 0); signal COUT: std_logic; component FA4 generic(n: integer := 4); port (X: in std_logic_vector(n-1 downto 0); Y: in std_logic_vector(n-1 downto 0); Z: out std_logic_vector(n-1 downto 0); COUT: out std_logic); end component; for U0: FA4 use configuration work.conf_fa4; U0: FA4 port map (X, Y, Z, COUT); X <= 0011, 1010 after 40 ns; Y <= 1000, 1110 after 20 ns; end RTL; VHDLASIC NO.-60 30

H/W Sensitivity Signal Simulation reset Spreading Code Active State: chip clock 8-Bit Shift Register Suspend State: Sensitivity Signal 8-Bit Shift Register I È»êµÈ Reset= 0 Chip Clock I-Data Falling Edge Q Sensitivity Signal È»êµÈ Q-Data Shift,. 2 XOR Gate Group Block Shift Register Block Register, I Q XOR Gate, reset, chip clock. XOR Gates Block VHDL I, Q Shift Register 3 Concurrent 2 Concurrent 1 Concurrent VHDLASIC NO.-61 VHDL Behavioral View Concurrent signal assignment statement basic signal assignment conditional signal assignment selected signal assignment process statement with many sequential statements concurrent subprogram call statement block statement basic block guarded block signal assignment concurrent assert statement Structural View Concurrent component instantiation statement Generate statement Behavioral View process function procedure subprogram wait statement Vector basic signal assignment statement variable assignment statement if statement case statement loop statements for..loop statement while loop statement infinite loop statement next statement, exit statement null statement sequential subprogram call statement sequential assert statement VHDLASIC NO.-62 31

Data Operator Logical Operators not and or nand nor xor xnor(vhdl-93) Operand Type : std_logic, boolean Result Type : std_logic, boolean Relational Operators = /= < <= > >= Operand Type : any type Result Type: boolean Arithmetic Operators + - * / ** MOD REM ABS Operand Type : integer, real, physical Result Type: integer, real, physical Concatenation Operators : & Operand Type : array of any type Result Type : array of any type MODREM A = B*N + (A mod B) (N: ) A = (A/B)*B + (A rem B) A=10, B=3: A mod B = 1, A rem B = 1 A=-10, B=3: A mod B = 2, A rem B = -1 A=11, B=- 4: A mod B = -1, A rem B = 3 operator reset= 0 or (clk= 0 and clk event) A <= ((B nand C) nand D) nand E; A <= (B and C) or (D and E) VHDLASIC NO.-63 Predefined Type and Array Attributes Attribute type attribute, array attribute, signal attribute, entity attribute Array Attribute Type. type COLOR is (RED, ORANGE, YELLOW, GREEN, BLUE, INDIGO, VIOLET); type STATE is (S0, S1, S2, S3, S4); type INDEXD is range 7 downto 0; Signal Type Attribute Return Value COLOR pos(green) = 3 COLOR val(3) = GREEN STATE pos(s2) = 2 STATE val(0) = S0 COLOR left= RED STATE left= S0 STATE right = S4 COLOR low = RED COLOR high = VIORET STATE high = S4 COLOR pred(green) = YELLOW STATE succ(s3) = S4 COLOR leftof (GREEN) = YELLOW STATE rightof(s2) = S3 INDEXD left= 7 INDEXD right = 0 INDEXD low = 0 INDEXD high = 7 INDEXD pred(6) = 5 INDEXD leftof(6) = 7 INDEXD succ(6) = 7 INDEXD rightof(6) = 5 INDEXD range = 7 downto 0 INDEXD reverse_range = 0 to 7 INDEXD length = 8 VHDLASIC NO.-64 32

Predefined Signal Attributes X2 active Simulation Cycle X2Transaction True X3 event Simulation Cycle X3Event True X2 stable(5 ns) Simulation Cycle 5 ns X2Event True X2 quiet(5 ns) Simulation Cycle 5 ns X2Transaction True X2 last_event Simulation Cycle Event X2 last_active Simulation Cycle Active X2 last_value Simulation Cycle Event VHDLASIC NO.-65 Predefined Signal Attributes Signal X1 Simulation = 15 ns Attribute X1 stable(8 ns) : FALSE X1 stable(2 ns) : TRUE X1 event : FALSE X1 last_event : 5 ns X1 last_value : 1 Simulation = 20 ns Attribute X1 event and X1= 1 : TRUE X1= 1 and (not X1 stable) : TRUE Simulation = 25 ns Attribute X1 event and X1= 0 : TRUE X1= 0 and (not X1 stable) : TRUE X1 delayed(2 ns) Value2 ns delay VHDLASIC NO.-66 33

Delay Delay Selection Delay Model (VHDL-87) Inertial Delay : VHDL default delay delay noise. delay. Component delay. Transport Delay delay. Interconnect delay modeling. Internal Delay Delta Delay : concurrent event driven simulation delay. Simulation : Plot. B <= transport A after 3 ns; C <= A after 3 ns; D <= A; VHDLASIC NO.-67 Delay Model (VHDL-93) VHDL-87 Inertial Delay Model Reject Delay Model A B A 10 20 30 40 50 60 [ns] b1 <= inertial a after 10 ns; b2 <= transport a after 10 ns; b3 <= reject 4 ns inertial a after 10 ns; B1 B2 B3 VHDLASIC NO.-68 34

Delta Delay Model VHDL Simulation Engine Delay Model A A B c <= a and b; d <= not c; & C D B 10 20 30 40 50 60 [ns] 30 ns + 1 delta 57 ns + 1 delta C D 30 ns + 2 delta 57 ns + 2 delta VHDLASIC NO.-69 architecture RTL of ADDER is signal S0, S1 : std_logic; Basic Signal Assignment Full-Adder Gate Signal Assignment Sensitivity Signal Aggregate : Target Signal Source Assign architecture RTL of EX is signal A : std_logic_vector( 4 downto 0); signal B : std_logic_vector( 4 downto 0); A <= (others => 0 ); Basic Signal Assignment Architecture Unit -- A <= 00000 ; -- A <= ( 0, 0, 0, 0, 0 ); --gatesignal assignment SUM <= S0 xor CIN; COUT <= S1 or (S0 and CIN); S0 <= A xor B; S1 <= A and B; end RTL; B <= (1=>C(2), 3=>C(1), others => D(0)); -- B <= D(0)&C(1)&D(0)&C(2)&D(0); end RTL; Source Target Signal. VHDLASIC NO.-70 35

Conditional Signal Assignment Syntax signal_identifier <= waveform_1 when condition_1 else waveform_2 when condition_2 else waveform_(n-1) when condition_(n-1) else waveform_n ; D Type Flip-FlopVHDL Symbol architecture A2 of DFF is D Q Q <= 0 when CLR= 0 else D when (CLK= 0 and CLK EVENT) else CLK Q Q; CLR -- D when (CLK= 0 and CLK EVENT); Valid in VHDL-93 QBAR <= not Q; end A2; Data Selector Conditional Signal Assignment MUXOUT <= I0 when (SEL= 0 ) else I1; -- when (SEL= 1 ) else X ; VHDLASIC NO.-71 Selected Signal Assignment Syntax with expression select signal_identifier <= waveform1 when expression_1,... waveform(n-1) when expression(n-1), waveform(n) when others ; 2*1 MUX library IEEE; use IEEE.std_logic_1164.ALL; entity MUX21 is port (SEL, A, B : in std_logic; C : out std_logic); end MUX21; architecture RTL of MUX21 is with SEL select C <= A after 10 ns when 0, B after 10 ns when others; end RTL; Half-Adder library IEEE; use IEEE.std_logic_1164.ALL; entity HA is port (A, B : in std_logic; SUM, COUT : out std_logic); end HA; architecture RTL of HA is signal TMP1, TMP2 : std_logic_vector(1 downto 0); TMP1 <= A & B; with TMP1 select TMP2 <= 00 when 00, 01 when 01, 01 when 10, 10 when others; (COUT, SUM) <= TMP2; end RTL; VHDLASIC NO.-72 36

Syntax [ Label : ] process [ ( Sensitivity_Signals ) ] -- declaration statements -- sequential activity statements end process [ Label ] ; Process Sensitivity Signal 1 Wait. Simulation Wait. Wait Simulation. Stimulus Vector Sensitivity Signal Half-Adder Sensitivity Signal process (A, B) process (A) Wait. Simulation SUM <= A xor B; SUM<=A xor B; Signal COUT <= A and B; COUT<=A and B; 1. Process Sensitivity Signal List Simulation ( ) Signal Event Synthesis ( ) Event Process Simulation. H/W VHDLASIC NO.-73 Signal Variable Assignment (1) Assignment : Target IdentifierObject 2 Signal Assignment [label:] signal_identifier <= [transport] expression [after expression]; Variable Assignment [label:] variable_identifier := value_expression; 2 Assignment Code -1 process variable num,sum:integer := 0; variable_process signal_process wait for 10 ns; time num sum time num sum num := num + 1; 0 0 0 0 0 0 sum := sum + num; 10 1 1 10 0 0 10+ 1 1 10+ 1 0 -- 20 2 3 20 1 0 process 20+ 2 3 20+ 2 1 wait for 10 ns; 30 3 6 30 2 1 num <= num + 1; 30+ 3 6 30+ 3 3 sum <= sum + num; VHDLASIC NO.-74 37

Signal Variable Assignment Signal Assignment Variable Assignment VHDLASIC NO.-75 Simulation Waveform Signal Assignment Simulation Waveform Variable Assignment Simulation Waveform VHDLASIC NO.-76 38

Wait Syntax wait [ on list ] [ until condition ] [ for time ] ; wait; SimulationRestart. wait on A; Signal A Simulation. wait until (CLK= 0 and CLK event); CLK SignalFalling Edge Simulation. wait for 100 ns; 100 nssimulation,. wait until A= 1 for 50 ns; 50 ns A A= 1. wait on A until (C= 1 ) for 50 ns; 50 ns A C= 1. Wait ( ) Synthesis Code : Clock wait Tool wait until CLK Edge Test Bench Modeling VHDLASIC NO.-77 Process Process Simulation Simulation process (A) process C1<=NOT A; C2<=NOT A; wait on A; A C1 10 20 30 40 50 60 [ns] process wait on A; C3<=NOT A; process process wait until A= 1 ; C5<=NOT A; C4<=not A; wait until A= 1 for 10 ns; C2 C3 C4 C5 10 ns 20 ns VHDLASIC NO.-78 39

Clock Wait Test Bench Modeling clock VHDL : CLK1, CLK2, CLK3, CLK4, CLK5, CLK6 0. process process CLK1 <= not CLK1; CLK2 <= not CLK2 after 25 ns; wait for 25 ns; wait on CLK2; -- -- process (CLK3) CLK3 <= not CLK3 after 25 ns; CLK4 <= not CLK4 after 25 ns; -- -- process process if (now = 0 ns) then CLK5 <= 0 ; wait for 20 ns; CLK6 <= 0 ; wait for 100 ns; CLK5 <= 1 ; wait for 30 ns; else CLK6 <= NOT CLK6; wait for 25 ns; end if Quiz: Simulation. VHDLASIC NO.-79 If Syntax if...then if... then...else if then elsif elsif else if then.if then end if. Latch IF -1: 2*1 MUX process (A, B, SEL) if SEL= 0 then Y <= A; else Y <= B; -2: 4*1 MUX process (SEL, A, B, C, D) if SEL= 00 then Y <= A; elsif SEL= 01 then Y <= B; elsif SEL= 10 then Y <= C; else Y <= D; -3: Latch process (EN, D) if EN= 1 THEN Q <= D; end if VHDLASIC NO.-80 40

Case Syntax caseexpression is when condition_1 => (sequential_statements;).. when condition_(n-1) => (sequential_statements;) when others => (sequential_statements;) end case ; when condition when Value => when Value Value Value => when Value to Value => when others => Truth Table 1 - Bit & operator Multi-Bits Variable expression 1-Bit Half-Adder architecture RTL1 of EX is --signal TMP1 : -- std_logic_vector(1 downto 0); --TMP1 <= A & B; --process (TMP1) process (A, B) variable TMP1, TMP2 : std_logic_vector(1 downto 0); TMP1 := A & B; case TMP1 is when 00 => TMP2 := 00 ; when 01 10 => TMP2 := 01 ; when others => TMP2 := 10 ; end case; (COUT, SUM) <= TMP2; end RTL; VHDLASIC NO.-81 For..Loop Syntax For..Loop [Label:] Data-flow Graph for loop_parameter in discrete_range loop VHDL. --sequential statements end loop [Label] ; Range integer_expression to ( downto) integer_expression array_attribute range array_attribute reverse_range loop_parameter Signal Variable. Signal Assignment Data-Flow For..Loop VHDLASIC NO.-82 41

For..Loop (1) VHDLASIC NO.-83 For..Loop (2) VHDLASIC NO.-84 42

While..Loop While..Loop Syntax [Label:] while condition loop --sequential statements end loop [Label] ; Infinite Loop process (N) variable TMP, I : integer; 1 ~ N TMP := 0; I := 0; entity ADD_LOOP is FIRST: loop port ( N : in integer; I := I + 1; SUM : out integer); TMP := TMP + 1; end ADD_LOOP; exit when (I = N) ; architecture RTL of ADD_LOOP is end loop FIRST; process (N) variable TMP, I : integer; Advanced Synthesis Tool TMP := 0; I := 1; while (I <= N) loop Behavioral Compiler TMP := TMP + I; I := I + 1; end loop; SUM <= TMP; end RTL; VHDLASIC NO.-85 NextExit Next Syntax next; nextloop_label ; next when boolean_expression ; next loop_label when boolean_expression ; LBL1 : process (S) variable TMP, J : integer := 0; TMP := 0; J := 0; A_LOOP: for I in 0 to 7 loop J := J + 1; if J > S then next A_LOOP; TMP := TMP + 1; end loop; end process LBL1; Exit Syntax exit; exit loop_label ; exit when boolean_expression ; exit loop_label when boolean_expression ; LBL2 : process (S) variable SUM, CNT : integer := 0; SUM:= 0; CNT:= 0; FIRST: loop CNT:=CNT+1; SUM:=SUM+CNT; exit when SUM > 100; end loop FIRST; --SECOND: loop -- CNT:=CNT+1; SUM:=SUM+CNT; -- if SUM > 100 then exit; --end loop SECOND; end process LBL2; VHDLASIC NO.-86 43

Block Script File read -f vhdl blk_fa.vhd group -hdl_block nand_1 group -hdl_block nand_2 group -hdl_block or2 /* create_clock clk*/ max_delay 0 -to all_outputs() compile -map_effort high create_schematic write -f db write -f edif -hierarchy -o blk_fa.edf Guarded Block Statement D_FF: block(clk= 0 and clk event) Q <= guarded D; end block; VHDLASIC NO.-87 Assert (1) Syntax assertcondition ; assertcondition report message ; assertcondition severity level ; assertcondition report message severity level ; Passive : H/W Concurrent, Sequential Assert D Flip-FlopAssert Setup Time Violation Setup Time CLK D Setup Setup Assert library IEEE; use IEEE.std_logic_1164.all; entity DFF_A_SR is generic (D_SETUP : time := 2 NS); port (SD_N, RD_N, CLK, DIN : in std_logic; Q, Q_N : out std_logic); assert (SD_N='1' or RD_N='1') report "PRESET and CLEAR are both '0' ; process (CLK, DIN) variable D_CHANGE : time := 0 ns; variable D_VALUE, CLK_VALUE : std_logic; if (D_VALUE /= DIN) then D_CHANGE := now; D_VALUE := DIN; if (CLK_VALUE /= CLK) then CLK_VALUE := CLK; if (CLK='1') then assert (now - D_CHANGE >= D_SETUP) report "SETUP VIOLATION ; end DFF_A_SR; VHDLASIC NO.-88 44

Assert (2) Assert VHDLASIC NO.-89 Package Package Syntax package package_name is --exported_subprogram_declarations --exported_constant_declarations --exported_components --exported_type_declarations --attribute_declarations --attribute_specifications end [package_name] ; package body package_name is --exported_subprogram_bodies --internal_subprogram_declarations --internal_subprogram_bodies --internal_constant_declarations --internal_components --internal_type_declarations end [package_name] ; Package package EX_PKG is subtype INT8 is INTEGER range 0 to 255; constant ZERO : INT8 := 0; constant MAX : INT8 := 100; procedure Increment (variable Count: inout INT8); end EX_PKG; Package package body EX_PKG is procedure Increment (variable Count: inout INT8) is if (Count >= MAX) then Count := Zero; else Count := Count + 1; end Increment; end EX_PKG; VHDLASIC NO.-90 45

Predefined Package Predefined Packages Package Group Package. Library Name : STD $/synopsys/packages/ieee/src/*.vhd Package Name standard std_logic_1164.vhd textio textio package std_logic_arith.vhd visibility. std_logic_signed.vhd Library Name : IEEE std_logic_unsigned.vhd Package Name std_logic_textio.vhd std_logic_1164 std_logic_textio Visibility. Synopsys Package. Library Name : IEEE Package Name std_logic_unsigned std_logic_signed std_logic_arith VHDLASIC NO.-91 Unsigned Data Data Type: std_logic_vector Package: std_logic_unsigned VHDL library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity TB_UNSIGNED is end TB_UNSIGNED; architecture RTL of TB_UNSIGNED is signal s1, s2 : std_logic_vector(3 downto 0); signal a, b : std_logic_vector(4 downto 0); signal c, d : std_logic_vector(7 downto 0); process s1 <= "0011"; s2 <= "0101"; wait for 50 ns; s1 <= "1101"; s2 <= "0101"; wait for 50 ns; s1 <= "1101"; s2 <= "1011"; wait for 50 ns; s1 <= "0011"; s2 <= "1011"; wait for 50 ns; a <= ('0'&s1) + s2; b <= ('0'&s1) - s2; c <= s1 * s2; d <= s1 * "1000"; end RTL; Data Type: unsigned Package: std_logic_arith VHDL library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity TB_ARITH_UNSIGNED is end TB_ARITH_UNSIGNED; architecture RTL of TB_ARITH_UNSIGNED is signal s1, s2 : unsigned(3 downto 0); signal a, b : unsigned(4 downto 0); signal c : unsigned(7 downto0); process s1 <= "0011"; s2 <= "0101"; wait for 50 ns; s1 <= "1101"; s2 <= "0101"; wait for 50 ns; s1 <= "1101"; s2 <= "1011"; wait for 50 ns; s1 <= "0011"; s2 <= "1011"; wait for 50 ns; a <= ('0'&s1) + s2; b <= ('0'&s1) - s2; c <= s1 * s2; end RTL; VHDLASIC NO.-92 46

Unsigned Data Simulation std_logic_vector std_logic_unsigned package Simulation unsigned std_logic_arith package simulation VHDLASIC NO.-93 Signed Data Data Type: std_logic_vector Package: std_logic_signed VHDL library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; entity TB_SIGNED is end TB_SIGNED; architecture RTL of TB_SIGNED is signal s1, s2 : std_logic_vector(3 downto 0); signal a,b : std_logic_vector(4 downto 0); signal c, d : std_logic_vector(7 downto 0); process s1 <= "0011"; s2 <= "0101"; wait for 50 ns; s1 <= "1101"; s2 <= "0101"; wait for 50 ns; s1 <= "1101"; s2 <= "1011"; wait for 50 ns; s1 <= "0011"; s2 <= "1011"; wait for 50 ns; a <= (s1(3)&s1) + (s2(3)&s2); b <= (s1(3)&s1) - (s2(3)& s2); c <= s1 * s2; d <= s1 * "1000"; end RTL; Data Type: signed Package: std_logic_arith VHDL library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity TB_ARITH_SIGNED is end TB_ARITH_SIGNED; architecture RTL of TB_ARITH_SIGNED is signal s1, s2 : signed(3 downto 0); signal a, b : signed(4 downto 0); signal c : signed(7 downto 0); process s1 <= "0011"; s2 <= "0101"; wait for 50 ns; s1 <= "1101"; s2 <= "0101"; wait for 50 ns; s1 <= "1101"; s2 <= "1011"; wait for 50 ns; s1 <= "0011"; s2 <= "1011"; wait for 50 ns; a <= (s1(3)&s1) + (s2(3)&s2); b <= (s1(3)&s1) - (s2(3)& s2); c <= s1 * s2; end RTL; VHDLASIC NO.-94 47

Signed Data Simulation std_logic_vector std_logic_signed package simulation signed std_logic_arith package simulation VHDLASIC NO.-95 Subprogram Function Subprogram Subprogram Parameter Function Data Mode Procedure in. Subprogram Data Object Package : constant signal Package : constant Architecture Formal NameActual Name Process Function Syntax signal : signal constant : Package function name (formal_parameter_list) signal,constant,variable return data_type is Function Visibility Package Package function name (formal_parameter_list) Package return data_type is Package Body -- declarative statements Package Body -- sequential statements Architecture -- including return expression Architecture end name ; Process Process VHDLASIC NO.-96 48

Function Subprogram Function Subprogram package MYPACK is function MAX (A, B: in std_logic_vector) return std_logic_vector; function EQUAL (A, B : in std_logic_vector) return boolean; end; package body MYPACK is function MAX (A, B: in std_logic_vector) return std_logic_vector is if A > B then return (A); else return (B); end MAX ; function EQAUL(A, B : in std_logic_vector) return boolean is return (A=B); end EQUAL; end MYPACK; Function Subprogram library IEEE; use IEEE.std_logic_1164.all; use work.mypack.all; entity EX is port (D1, D2: in std_logic_vector(3 downto 0); DATA1, DATA2: in std_logic_vector(7 downto 0); Q: out std_logic_vector(3 downto 0); DATA_OUT: out boolean); end EX; architecture RTL of EX is Q <= MAX(d1, d2); --Concurrent function call process (DATA1, DATA2) DATA_OUT <= EQUAL(DATA1, DATA2); --Sequential function call end RTL; VHDLASIC NO.-97 Procedure Subprogram Procedure Syntax Package procedure name (formal_parameter_list) ; Package procedure name (formal_parameter_list) is -- declarative statements -- sequential statements end name ; Parameter Data Mode in, out, inout. in mode Data Class Modein, constant, signal, variable. Modein, constant Modeinout out, variable, signal. Modeinout out, variable Formal NameActual Name signal : signal variable : variable constant : signal,constant,variable Procedure Visibility Package Package Package Body Package Body Architecture Architecture Process Process VHDLASIC NO.-98 49

Procedure Subprogram (1) Procedure package MYPACK is procedure COMPUTE (A, B: in integer; MEAN, MAX: out integer); end MYPACK; package body MYPACK is procedure COMPUTE (A, B: in integer; MEAN, MAX: out integer) is MEAN := (A+B)/2; if A> B then MAX := A; else MAX := B; end COMPUTE; end MYPACK; Procedure use work.mypack.all; entity EX is port (D1, D2, D3, D4: in integer; Q1, Q2, Q3, Q4: out integer); architecture RTL1 of EX is COMPUTE(D1, D2, Q1, Q2); --, Q1, Q2 not variables --Concurrent procedure call process(d3, D4) variable A, B: integer; COMPUTE(D3, D4, A, B); --, A and B variables --Sequential procedure call Q3 <= A; Q4 <= B; end RTL1; VHDLASIC NO.-99 Procedure Subprogram (2) Procedure package MYPACK is procedure COMPUTE (A, B: in integer; signal MEAN, MAX: out integer); end MYPACK; package body MYPACK is procedure COMPUTE (A, B: in integer; signal MEAN, MAX: out integer) is MEAN <= (A+B)/2; if A> B then MAX <= A; else MAX <= B; end COMPUTE; end MYPACK; Procedure use work.mypack.all; entity EX is port (D1, D2, D3, D4: in integer; Q1, Q2, Q3, Q4: out integer); architecture RTL2 of EX is COMPUTE(D1, D2, Q1, Q2); --, Q1 and Q2 signals --Concurrent procedure call process(d3, D4) COMPUTE(D3, D4, Q3, Q4); --, Q3 and Q4 signals --Sequential procedure call end RTL2; VHDLASIC NO.-100 50

Procedure Subprogram (3) library IEEE; use IEEE.std_logic_1164.ALL; package EXAMPLE is procedure RCA (A, B : in std_logic_vector; CIN : in std_logic; SUM : out std_logic_vector; COUT : out std_logic); end EXAMPLE; package body EXAMPLE is function XOR3 (A, B, C : in std_logic) return std_logic is return (A xor B xor C); end XOR3; procedure RCA (A, B : in std_logic_vector; CIN : in std_logic; SUM : out std_logic_vector; COUT : out std_logic) is variable C: std_logic_vector((a high-a low+1) downto0); C(0) := CIN; for I in 0 to (A high-a low) loop SUM(I+SUM low) := XOR3(A(I+A low), B(I+B low), C(I)); C(I+1) := (A(I+A low) and (I+B low)) or (C(I) and (A(I+A low) or B(I+B low))); end loop; COUT := C(C high); end RCA; end EXAMPLE; library IEEE; use IEEE.std_logic_1164.ALL; use work.example.all; entity ADDER_TEST is port ( A, B: in std_logic_vector(15 downto 0); CIN : in std_logic; SUM : out std_logic_vector(15 downto 0); COUT : out std_logic); end ADDER_TEST; architecture RTL of ADDER_TEST is process (A,B,CIN) variable TMP_SUM: std_logic_vector(sum range); variable TMP_COUT : std_logic; RCA(A, B, CIN, TMP_SUM, TMP_COUT); SUM <= TMP_SUM; COUT <= TMP_COUT; end RTL; VHDLASIC NO.-101 Operator Overload VHDL Compiler data Compile VHDL Code+ type Operator CompilerOperandData Type overload Function. function Type Function Function Function Algorithm,. Function Analysis Error Message. Function Function Synopsys Vendor Algorithm. Package C <= A + B, A, Bstd_logic_vector function + (L: std_logic_vector, R: std_logic_vector) A std_logic_vector, B integer return std_logic_vector; function + (L: std_logic_vector, R: integer) Function Name return std_logic_vector; VHDLASIC NO.-102 51

Subprogram Overload Subprogram, Formal Parameter Return Value Data Type Subprogram library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; package EXAMPLE is function CONV_2COMP (A : std_logic_vector; K : integer) return std_logic_vector; function CONV_2COMP (A : integer; K : integer) return std_logic_vector; end EXAMPLE; package body EXAMPLE is function CONV_2COMP (A : std_logic_vector; K : integer) return std_logic_vector is return (not (A(K-1) downto 0)+1); end; -- function CONV_2COMP (A : integer; K : integer) return std_logic_vector is return (not conv_std_logic_vector(a,k)+1); end; end EXAMPLE; VHDL Compiler B <= CONV_2COMP(A, 8);. Astd_logic_vector Ainteger VHDLASIC NO.-103 Chap 3. Digital SystemVHDL Modeling 52

Digital SystemRTL -1 4 Process -2 2 Process VHDLASIC NO.-105 Digital SystemVHDL Modeling Template H/W Model VHDL Modeling Entity + Architecture Entity Unit Visibility 9-value Visibility Arithmetic Operator Visibility Visibility, Block Diagram Generic, Port Data DataIdentifier, Mode, Type Architecture Unit entity name is port ( ); end name ; architecture architecture_name of name is (: signal); Package -- sync : process (clock, reset ) Basic Modeling Template library IEEE; use IEEE.std_logic_1164.ALL; VHDL statements for state elements end process sync; -- ( ) -- comb : process ( ) (: variable) end process comb; end architecture_name ; VHDLASIC NO.-106 53

4-Bit Up-Counter VHDL Modeling Counter Table RST 0 1 1 Block Diagram LOADB ENB DIN CLK 4 X Counter RST ENB CLK VHDL library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.std_logic_unsigned.all; entity COUNTER is port ( RST,CLK,LOADB,ENB: in std_logic; DIN : in std_logic_vector(3 downto 0); DOUT : out std_logic_vector(3 downto 0)); end COUNTER; X 1 1 LOADB 4 X 0 1 DOUT DOUT "0000" DIN DOUT+1 architecture RTL of COUNTER is signal T1,T2: std_logic_vector(3 downto 0); A: process (RST, CLK) if RST = '0' then T1 <= (others => '0'); elsif CLK'event and CLK = '1' then if ENB = 1' then T1 <= T2; -- B: process (LOADB, DIN, T1) if LOADB= 0 then T2 <= DIN; else T2 <= T1 + 1; -- DOUT <= T1; end RTL; VHDLASIC NO.-107 Gate-Level Gate Logic Operator Boolean Equation Wire Signal Signal Assign Shift Data library IEEE; use IEEE.std_logic_1164.ALL; Arithmetic Logic entity ADDER is 3-state Buffer port (A, B, CIN : in std_logic; SUM, COUT : out std_logic); end ADDER; architecture RTL1 of ADDER is -- Wire Signal signal S0, S1, S2 : std_logic; --GateLogical Operator S0 <= A xor B; S1 <= A and B; SUM <= S0 xor CIN; S2 <= S0 and CIN; COUT <= S1 or S2; end RTL1; VHDLASIC NO.-108 54

Boolean Equation VHDL Equation sum? abc in? abc in? abc in? abc in cout? abc in? abc in? abc in? abc in Boolean EquationData Flow Signal Assign architecture RTL2 of ADDER is SUM <= (not A and not B and Cin) or (not A and B and not Cin) or (A and B and not Cin) or (A and B and Cin); COUT <= (not A and B and Cin) or (A and not B and Cin) or (A and B and not Cin) or (A and B and C); end RTL2; Multi-Bit Entity Unit entity MULTIBIT is port (A,B,C : IN std_logic_vector(3 DOWNTO 0); Z: OUT std_logic_vector(3 DOWNTO 0)); end MULTIBIT; 2 Architecture Unit architecture RTL2 of MULTIBIT is --Multi-Bit. Z <= A or (B nand C); end RTL2; -- architecture RTL1 of MULTBIT is --Bit Equation Z(3) <= A(3) nor (B(3) nand C(3)); Z(2) <= A(2) nor (B(2) nand C(2)); Z(1) <= A(1) nor (B(1) nand C(1)); Z(0) <= A(0) nor (B(0) nand C(0)); end RTL1; VHDLASIC NO.-109 Truth Table VHDL 1-Bit Truth Table a b cin sum cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 1 - Bit & Variable Case Signal Assign Variable Assign end case; end RTL2; Architecture Unit architecture RTL2 of ADDER is process (A, B, CIN) variable TMP : std_logic_vector(2 downto 0); -- variable. TMP := A & B & CIN; case TMP is when "000" => SUM <= 0 ; COUT <='0'; when "001" "010" "100" => SUM <='1'; COUT <='0'; when "011" "101" "110" => SUM <='0'; COUT <='1'; when others => SUM <='1'; COUT <='1'; VHDLASIC NO.-110 55

VHDL 4*2 Priority Encoder ProcessIF a b c d enc_out 1 - - - 0 00 - - 0 1 01-0 1 1 10 0 1 1 1 11 Conditional Signal Assign Process IF Conditional Signal Assign architecture RTL1 of PRIO_ENC is ENC_OUT <= "00" when D = '0' else "01" when C = '0' else "10" when B = '0' else "11 ; end RTL1; architecture RTL2 of PRIO_ENC is process (A,B,C,D) if D='0' then ENC_OUT <= "00"; elsif C='0' then ENC_OUT <= "01"; elsif B='0' then ENC_OUT <= "10"; else ENC_OUT <= "11"; end RTL2; VHDLASIC NO.-111 (1) Enable 4*1 MUX ENABLE SEL Y 0 00 l0 0 01 l1 0 10 l2 0 11 l3 1 -- "0000" ProcessCase process(sel,enable,l0,l1,l2,l3) if ENABLE='0' then case SEL is when "00" => Y <= l0; when "01" => Y <= l1; when "10" => Y <= l2; when others => Y <= l3; end case; else Y <= "0000"; Selected Signal Assign architecture RTL2 of MUX41 is signal TMP : std_logic_vector(1 downto 0); with SEL select TMP <= l0 when "00", l1 when "01", l2 when "10", l3 when others; with ENABLE select Y <= TMP when '0, "0000" when others; end RTL2; MUX MUXComponent, Structural Modeling process case, Tool VHDLASIC NO.-112 56

(2) Enable 2*4 DEC Enable G DATA Y 0 0 0 0 1 00 01 10 11 -- "1110" "1101" "1011" "0111" "1111" Process process(g,data) if G='0' then case DATA is when "00" => Y <= "1110"; when "01" => Y <= "1101"; when "10" => Y <= "1011"; when others => Y <= "0111"; end case; else Y <= "1111"; Selected Signal Assign architecture RTL2 of EDECODER is signal TMP : std_logic_vector(2 downto 0); TMP <= G & DATA; with TMP select Y <= "1110" when "000", "1101" when "001", "1011" when "010", "0111" when "011", "1111" when others; end RTL2; BCD-to-7 Segment Decoder Don t Care VHDL.. VHDLASIC NO.-113 Shift Data VHDL Shift Data Basic Signal Assign & Operator & Operator : Shift Rotate. -- DATA4(7 downto 3) <= DATA1(4 downto 0); -- DATA4(2 downto 0) <= DATA1(7 downto 5); DATA4 <= DATA1(4 downto 0) & DATA1(7 downto 5); -- DATA5(7 downto 5) <= 000 ; -- DATA5(4 downto 0) <= DATA2(7 downto 3); DATA5 <= "000" & DATA2(7 downto 3); -- DATA6(7) <= DATA3(7); -- DATA6(6 downto 3) <= DATA3(3 downto 0); -- DATA6(2 downto 0) <= "000 ; DATA6 <= DATA3(7) & DATA3(3 downto 0)& "000 ; VHDLASIC NO.-114 57

Arithmetic VHDL 8 ALU 000 op1 + op2 001 op1-1 010 op1 - op2 011 op1 + 1 100 op1 and op2 101 op1 or op2 110 not op1 111 op1 Entity Unit library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.std_logic_unsigned.all; entity SIM_ALU is port (OP1,OP2:in std_logic_vector(7 downto 0); CIN : in std_logic; SEL : in std_logic_vector(2 downto 0); ALU_OUT : out std_logic_vector(7 downto 0); ZERO_FLAG : out std_logic ); end SIM_ALU; Case architecture RTL of SIM_ALU is process (OP1, OP2, CIN, SEL) variable TMP:std_logic_vector(7 downto 0); case SEL is when 000 =>TMP:= OP1+OP2+CIN; when 001 =>TMP:= OP1-1; when 010 =>TMP:= OP1-OP2+CIN; when 011 =>TMP:= OP1+1; when 100 =>TMP:= OP1 and OP2; when 101 =>TMP:= OP1 or OP2; when 110 =>TMP:= not OP1; when others =>TMP:= OP1; end case; ALU_OUT <= TMP; if TMP=0 then ZERO_FLAG <= 1 ; else ZERO_FLAG <= 0 ; end RTL; VHDLASIC NO.-115 3-State Buffer VHDL Resolved Signal Data Source2 Wire architecture RTL2 of TRISTATE is Resolved Signal 3-State Buffer MUX Y2 D2 Y1 D1 resolved signal TBUS Selected Signal Assign architecture RTL1 of TRISTATE is TBUS<= D1 when (Y1= 1 ) else Z ; TBUS<= D2 when (Y1= 0 and Y2= 1 ) else Z ; end RTL1; Process IF 3-BufferOFF Z process (Y1, D1) if (Y1= 1 ) then TBUS<=D1; else TBUS<= Z ; process (Y1, Y2, D2) if (Y1= 0 and Y2= 1 ) then TBUS<=D2; else TBUS<= Z ; end RTL2; Resolved Function 0 1 VHDLASIC NO.-116 58

VHDL : ROM ROM address bus : N-bit data bus : M-bit Entity Unit library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.std_logic_unsigned.ALL; entity ROM is generic (N: integer := 3; M: integer := 5); port ( ADDR: in std_logic_vector(n-1 downto 0); CE_N, OE_N : in std_logic; DATA : out std_logic_vector(m-1 downto 0)); end ROM; Architecture Unit 2 ROM ROM addressinteger architecture RTL of ROM is subtype WORD is std_logic_vector(m-1 downto 0); type TABLE is array(0 to 2**N-1) of WORD; -- type TABLE is array(0 to 2**N-1) of -- std_logic_vector(m-1 downto 0); constant ROM_DATA : TABLE := TABLE ( 10101, 10000, 11111, 11011, 10001, 01100, 00101, 10011 ); process (CE_N,OE_N,ADDR) if CE_N= 0 and OE_N= 0 then DATA <= ROM_DATA(conv_integer(ADDR)); else DATA <= (others=> Z ); end RTL; VHDLASIC NO.-117 VHDL : RAM RAM address bus : 8-bit data bus : 8-bit ADDRESS RAM 8 8 /RD /CE /WR Entity Unit library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.std_logic_unsigned.ALL; entity RAM is port ( ADDR : in std_logic_vector(7 downto 0); CE_N, RD_N, WR_N : in std_logic; DATA : inout std_logic_vector(7 downto 0)); end RAM; DATA Architecture Unit 2 RAM addressinteger Read Data Bus Bit Z : Resolved Signal architecture RTL of RAM is subtype RAM_WORD is std_logic_vector(7 downto 0); type RAM_TABLE is array(0 to 255) of RAM_WORD; signal RAM_DATA : RAM_TABLE; process (CE_N,RD_N,WR_N,ADDR,DATA) variable TMP : integer; DATA <= ZZZZZZZZ ; TMP := conv _integer(addr); if CE_N= 0 and RD_N= 0 then DATA <= RAM_DATA(TMP); elsif CE_N= 0 and WR_N= 0 then RAM_DATA(TMP) <= DATA; end RTL; VHDLASIC NO.-118 59

Latch VHDL D-Latch G G o 1 D Q Latch Process IF architecture RTL1 of DLATCH1 is process (G, D) if G= 1 then Q <= D; QBAR <= not D; end RTL1; E Q(t+1) Q(t) D Signal Assign architecture RTL2 of DLATCH1 is signal TMP : std_logic; TMP<=D when G= 1 else TMP; Q <= TMP; QBAR <= not TMP; end RTL2; Latch architecture RTL of EX is signal A, B, C, D, E: std_logic_vector(1 downto 0); process (C, D, E, EN) if EN= 1 then A <= C; B <= D; else A <= E; end RTL; VHDLASIC NO.-119 Flip-Flop VHDL Synchronous D Flip-Flop Asynchronous D Flip-Flop d D Q q in_data d q FD clk CLK clk clk reset data reset VHDL A1: process (CLK) if (CLK= 1 and CLK event) then Q <= D; A2: process wait until CLK= 1 ; Q <= D; VHDL (Synopsys Model) A1: process (RESET, CLK) if RESET= 1 then DATA <= 0 ; elsif (CLK= 1 and CLK event) then DATA <= IN_DATA; VHDLASIC NO.-120 60

Flip-Flop VHDL (1) -1 architecture RTL1 of EX is signal A, B: std_logic_vector(3 downto 0); process (CLK) if (CLK= 1 AND CLK EVENT) then if Q(3)/= 1 then Q <= A + B; end RTL1;. -2 architecture RTL2 of EX is signal A, B: std_logic_vector(3 downto 0); process (CLK) variable INT: std_logic_vector(3 downto 0); if (CLK= 1 AND CLK EVENT) then if INT(3)/= 1 then INT := A + B; Q <= INT; end RTL2;. VHDLASIC NO.-121 Flip-Flop VHDL (2) -3 architecture RTL3 of EX is process (RESET_N, CLK) if (RESET_N= 0 ) then Q1 <= 0 ; Q2 <= 0 ; elsif (CLK= 1 AND CLK EVENT) then Q1 <= A and B; Q2 <= C; end RTL3;. -4 architecture RTL4 of EX is signal Q1, I2: std_logic; process (CLK) if (CLK= 1 AND CLK EVENT) then Q1 <= D; I2 <= Q1 and A; Q2 <= I2 and B; end RTL4;. VHDLASIC NO.-122 61

Variable Signal Assignment Flip-Flop SignalShift-Register --4 Flip-Flop library IEEE; use IEEE.std_logic_1164.all; entity SHREG4 is port ( D_IN, CLK : in std_logic; D_OUT: out std_logic); end SHREG4; architecture RTL of SHREG4 is signal S0, S1, S2: std_logic; process (CLK) if (CLK= 1 and CLK event) then S0 <= D_IN; S1 <= S0; S2 <= S1; D_OUT <= S2; end RTL;. VariableShift-Register --1 Flip-Flop process (CLK) variable S0, S1, S2: std_logic; if (CLK= 1 and CLK event) then S0 := D_IN; S1 := S0; S2 := S1; D_OUT <= S2; --4 Flip-Flop process (CLK) variable S0, S1, S2: std_logic; if (CLK= 1 and CLK event) then D_OUT <= S2; S2 := S1; S1 := S0; S0 := D_IN;,,. VHDLASIC NO.-123 Register VHDL Multi-Bits Register Shift-Register FIFO Cycle Buffer 8-Bit Register RESET LD ENABLE CLK REG 0 1 1 1 1-1 0 0 0 - - 0 1 1 - - -? (x)? (o) 00000000 LDDATA REG REG REGIN library IEEE; use IEEE.std_logic_1164.ALL; entity REGISTER1 is port (RESET, LD, ENABLE, CLK : in std_logic; REGIN : in std_logic_vector(7 downto 0); REG : out std_logic_vector(7 downto 0)); end REGISTER1; architecture RTL2 of REGISTER1 is process (RESET, LD, CLK) if RESET= 0 then REG <= (others => 0 ); elsif LD= 1 then REG <= LDDATA; elsif ENABLE= 1 then if (CLK= 0 and CLK event) then REG <= REGIN; end RTL2; VHDLASIC NO.-124 62

Counter VHDL Out Mode library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.std_logic_unsigned.all; entity CNT8 is port (RESET,CLK: in std_logic; CNT: out std_logic_vector(2 downto 0)); end CNT8; architecture RTL1 of CNT8 is signal TMP1,TMP2: std_logic_vector(2 downto 0); CNT <= TMP2; TMP1 <= TMP2 + 1 ; process (RESET, CLK) if (RESET= 0 ) then TMP2 <= 000 ; elsif (CLK= 1 and CLK event) then TMP2 <= TMP1; end RTL1; Buffer Mode Signal. Buffer Mode : library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.std_logic_unsigned.all; entity CNT8 is port (RESET,CLK: in std_logic; CNT: buffer std_logic_vector(2 downto 0)); end CNT8; architecture RTL2 of CNT8 is process (RESET, CLK) if (RESET= 0 ) then CNT <= 000 ; elsif (CLK= 1 and CLK event) then CNT <= CNT + 1 ; end RTL2; VHDLASIC NO.-125 Counter VHDL 8Ripple Counter CLK RESET D Q Q Generate D Flip-Flop architecture RTL1 of DFFR is signal TMP_Q : std_logic; Q <= TMP_Q; QBAR <= not TMP_Q; process (RESET, CLK) if (RESET= 0 ) then TMP_Q <= 0 ; elsif (CLK= 1 and CLK event) then TMP_Q <= D; end RTL1; D Q Q D Q Q Generate architecture RTL2 of RPLCNT8 is -- Clock Wire signal CNTB: std_logic_vector(3 downto 0); -- D Flip-Flop Component component DFFR port (RESET, CLK, D : in std_logic; Q, QBAR : out std_logic); end component; -- Component Specification for U: use entity DFFR work.dffr(rtl1); CNTB(0) <= CLK; GEN1: for I in 0 to 2 generate U: DFFR port map (CLK => CNTB(I), RESET => RESET, D => CNTB(I+1), Q => CNT(I), QBAR => CNTB(I+1)); end generate GEN1; end RTL2; VHDLASIC NO.-126 63

Finite State Machine (1) State Diagram FSMHardware Moore Type Machine Mealy Type Machine State Register Symbolic State Name Enumeration Data Type Symbolic State Modeling library IEEE; use IEEE.std_logic_1164.ALL; entity MEALYFSM is port (RESET, CLK, X : in std_logic; Z : out std_logic); end MEALYFSM; architecture RTL1 of MEALYFSM is --Symbolic State Name Type type STATE is (S0, S1, S2); --State Signal signal C_STATE, N_STATE : STATE; VHDLASIC NO.-127 Finite State Machine (2) SYNC: process (RESET, CLK) if RESET= 0 then C_STATE <= S0; elsif CLK= 0 and CLK event then C_STATE <= N_STATE; COMB : process (C_STATE, X) case C_STATE is when S0 => Z <= 0 ; if X= 0 then N_STATE <= S0; else N_STATE <= S1; when S1 => if X= 0 then N_STATE <= S0; Z <= 0 ; else N_STATE <= S2; Z <= 1 ; when others => if X= 0 then N_STATE <= S0; Z<= 0 ; else N_STATE <= S1; Z <= 1 ; end case; end RTL1; State Code Assignment Tool Tool Symbolic State Name Simulation Code Assign Symbolic Name Synthesis Binary CodeAssign State Name Binary CodeEncoding. S0=(00), S1=(01), S2=(10) VHDLASIC NO.-128 64

Finite State Machine (3) State Code State Code Assignment -1 library IEEE; use IEEE.std_logic_1164.ALL; entity MEALYFSM is port (RESET, CLK, X : in std_logic; Z : out std_logic); end MEALYFSM; architecture RTL2 of MEALYFSM is constant S0: std_logic_vector(1 downto 0) := 00 ; constant S1: std_logic_vector(1 downto 0) := 01 ; constant S2: std_logic_vector(1 downto 0) := 11 ; signal C_STATE, N_STATE : std_logic_vector(1 downto 0); -- VHDL Code end RTL2; State Code Assignment -2 library IEEE; use IEEE.std_logic_1164.ALL; entity MEALYFSM is port (RESET, CLK, X : in std_logic; Z : out std_logic); end MEALYFSM; architecture RTL3 of MEALYFSM is --Symbolic State Name Type type STATE is (S0, S1, S2); attribute ENUM_ENCODING: string; attribute ENUM_ENCODING of STATE: type is 00 01 11 ; -- State Signal signal C_STATE, N_STATE : STATE; -- VHDL Code end RTL3; VHDLASIC NO.-129 Chap. 4 VHDL Test Bench Model 65

H/W S/W H/W Model Signal generator Prototype Oscilloscope S/W Model Nodes In signal file "Signal generator" Computer model Netlist (schematic) "Prototype" Out signal file "Oscilloscope" VHDLASIC NO.-131 VHDLTest Bench Modeling Test Harness Test Vectors File Synthesis Hardware VHDL Model Simulation Data Vector Generation VHDL Model Test Harness Array Vector System File Vector Simulation Tool VHDL Model Simulation Simulation File assert Pass/Fail VHDLASIC NO.-132 66

Test Vector 3 VHDL Case1 : Clock signal clock, reset : std_logic:='0'; clock <= not clock after 20 ns; reset <= '1' after 120 ns; reset 0 40ns 120ns clock time 20ns case2 : Random (1 ) x <= "00", "01" after 50 ns, "10" after 100 ns, "11" after 200 ns, "10" after 220 ns; 00 01 10 11 10 x 0 50ns 100ns 200ns 220ns case3 : Random ( ) process a <= '0'; b <= '1'; wait for 50 ns; a <= '1'; wait for 70 ns; b <= '0'; wait for 100 ns; a <= '0'; wait for 50 ns; time a 0 50ns 120ns 220ns 270ns b time VHDLASIC NO.-133 Test Vector Modeling --9-value visibility library IEEE; use IEEE.std_logic_1164.ALL; --entity unit entity TB is port (CLOCK1 : buffer std_logic := 0 ; CLOCK2, RESET1, RESET2 : out std_logic ; ENABLE : out std_logic; A_DATA, B_DATA : out std_logic_vector(7 downto 0)); end TB; --architecture unit architecture TB_A of TB is CLOCK1 <= not CLOCK1 after 20 ns; RESET1 <= 0, '1' after 100 ns; process if now = 0 ns then CLOCK2 <= '0'; wait for 250 ns; else CLOCK2 <= '1'; wait for 20 ns; CLOCK2 <= '0'; wait for 20 ns; process A_DATA <= "00101101"; B_DATA <= "10110110"; wait for 120 ns; A_DATA <= "11011011"; wait for 30 ns; B_DATA <= "00001010"; wait for 90 ns; A_DATA <= "00011011"; wait for 150 ns; process if now = 0 ns then RESET2 <= '0'; ENABLE <= '0'; wait for 50 ns; else RESET2 <= '1'; ENABLE <= '1'; wait for 300 ns; ENABLE <= '0' after 200 ns, '1' after 400 ns; wait for 800 ns; RESET2 <= '0', '1' after 150 ns; ENABLE <= '0' after 50 ns; wait for 200 ns; end TB_A; VHDLASIC NO.-134 67

Test Vector Waveform Test Vector Waveform CLOCK1, CLOCK2 RESET1, RESET2 A_DATA, B_DATA Data Process VHDLASIC NO.-135-1 : Booth Multiplier Booth Multiplier Algorithm VHDLASIC NO.-136 68

-1 : Booth Multiplier VHDL library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.numeric_std.ALL; -- entity BOOTH is generic (N : integer := 8); port (RESET, CLOCK, LOAD : in std_logic; MULTIPLICAND, MULTIPLIER : in std_logic_vector(n-1 downto 0); PRODUCT : out std_logic_vector(2*n-1 downto 0)); end BOOTH; -- architecture RTL of BOOTH is signal Q1 : std_logic; signal AC, BR : std_logic_vector(n-1 downto 0); signal QR : std_logic_vector(n-1 downto 0); signal SC : integer; process (RESET, CLOCK) variable TMP_AC : std_logic_vector(n -1 downto 0); if RESET='0' then BR <= (OTHERS => '0'); QR <= (OTHERS => '0'); AC <= (OTHERS => '0'); Q1 <= '0'; SC <= N; PRODUCT <= (OTHERS => '0'); elsif (CLOCK='1' AND CLOCK'event) then if LOAD='1' then BR <= MULTIPLICAND; QR <= MULTIPLIER; AC <= (OTHERS => '0'); Q1 <= '0'; SC <= N; PRODUCT <= (OTHERS => '0'); else if (SC=0) then PRODUCT <= AC & QR; else if QR(0)='0' and Q1='1' then TMP_AC := AC + BR; elsif QR(0)='1' and Q1='0' then TMP_AC := AC + not BR + '1'; else TMP_AC := AC; Q1 <= QR(0); QR <= TMP_AC(0) & QR(N-1 downto 1); AC <= TMP_AC(N -1) & TMP_AC(N-1 downto 1); SC <= SC - 1; end RTL; -- VHDLASIC NO.-137-1 : Test Bench Vector library IEEE; use IEEE.std_logic_1164.ALL; library IEEE.numeric_std.ALL; entity VEC_GEN is port ( CLOCK, RESET, LOAD : out std_logic; A_PORT, B_PORT : out std_logic_vector(7downto0)); end VEC_GEN; architecture VEC_GEN_A of VEC_GEN is signal CLOCK_S : std_logic := '0'; RESET <= '1' after 50 ns; CLOCK_S <= not CLOCK_S after 2 ns; CLOCK <= CLOCK_S; LOAD <= '0', '1' after 20 ns, '0' after 70 ns, '1' after 210 ns, '0' after 250 ns, '1' after 390 ns, '0' after 430 ns, '1' after 570 ns, '0' after 610 ns; A_PORT_DRV : process A_PORT <= "00000101"; A_PORT <= "11111011"; B_PORT_DRV : process B_PORT <= "00000011"; B_PORT <= "11111101"; end VEC_GEN_A; wait for 200 NS; wait for 400 NS; wait for 400 NS; wait for 400 NS; Test Bench library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.numeric_std.ALL; entity TB_BOOTH1 is end TB_BOOTH1; architecture TB_BOOTH1_A of TB_BOOTH1 is component BOOTH generic (n : integer := 8); port (RESET, CLOCK, LOAD : in std_logic; MULTIPLICAND, MULTIPLIER : in std_logic_vector(n-1 downto 0); PRODUCT : out std_logic_vector(2*n-1 downto0)); end component; -- Vector Generation Block signal A_PORT, B_PORT: std_logic_vector(7downto 0); signal MUL_OUT : std_logic_vector(15 downto 0); signal RESET, CLOCK, LOAD : std_logic; for u0 : BOOTH use entity work.booth(rtl); for u1 : VEC_GEN use entity work.vec_gen(vec_gen_a); u0 : BOOTH port map(reset, CLOCK, LOAD, A_PORT, B_PORT, MUL_OUT); u1 : VEC_GEN port map ( CLOCK, RESET, LOAD, A_PORT, B_PORT ); end TB_BOOTH1_A; VHDLASIC NO.-138 69

-1 : Test Bench VHDL Simulation VHDL Functional Simulation Simulation -1 : (+5) = (00000101) 2, (+3)=(00000011) 2 = (00000000_00001111) 2 Simulation -2 : (-5) = (11111011) 2, (+3)=(00000011) 2 = (11111111_11110001) 2 Simulation -3 : (-5) = (11111011) 2, (-3)=(11111101) 2 Simulation -4 : (+5) = (00000101) 2, (-3)=(11111101) 2 VHDLASIC NO.-139-1 : ASSERT Test Bench Compare library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.numeric_std.ALL; entity COMP is port ( RESET, LOAD : in std_logic; A_PORT, B_PORT : in signed(7 downto 0); MUL_OUT : in signed(15 downto 0)); end COMP; architecture COMP_A of COMP is constant CLOCK_PERIOD : time := 5 ns; process wait on RESET, LOAD; if RESET='0' then wait for (CLOCK_PERIOD); assert (MUL_OUT=0) report "assert violation-1"; elsif LOAD='1' then wait for (CLOCK_PERIOD); assert (MUL_OUT=0) report "assert violation-2"; else wait until (LOAD='0' and load'event); wait on MUL_OUT; assert (MUL_OUT=(A_PORT*B_PORT)) report "assert violation-3"; end COMP_A; Test Bench library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.numeric_std.ALL; entity TB_BOOTH2 is end TB_BOOTH2; architecture TB_BOOTH2_A of TB_BOOTH2 is -- Compare Component component COMP port ( RESET, LOAD : in std_logic; A_PORT, B_PORT : in signed(7 downto 0); MUL_OUT : in signed(15 downto 0)); end component; signal A_PORT, B_PORT: signed(7downto 0); signal MUL_OUT : signed(15 downto0); signal RESET, CLOCK, LOAD: std_logic; for u0 : BOOTH use entity work.booth(rtl); for u1 : VEC_GEN use entity work.vec_gen(vec_gen_a); for u2 : COMP use entity work.comp(comp_a); u0 : BOOTH port map(reset, CLOCK, LOAD, A_PORT, B_PORT, MUL_OUT); u1 : VEC_GEN port map ( CLOCK, RESET, LOAD, A_PORT, B_PORT ); u2 : COMP port map ( RESET, LOAD, A_PORT, B_PORT, MUL_OUT ); end TB_BOOTH2_A; VHDLASIC NO.-140 70